1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation on the rights to use, copy, modify, merge, 10 * publish, distribute, sublicense, and/or sell copies of the Software, 11 * and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 21 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 22 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 28 #ifdef HAVE_CONFIG_H 29 #include "config.h" 30 #endif 31 32 #include <string.h> 33 34 #include "xf86.h" 35 #include "xf86_OSproc.h" 36 37 #include "atipciids.h" 38 #include "radeon.h" 39 #include "radeon_reg.h" 40 #include "radeon_macros.h" 41 #include "radeon_probe.h" 42 #include "radeon_atombios.h" 43 44 typedef enum 45 { 46 DDC_NONE_DETECTED, 47 DDC_MONID, 48 DDC_DVI, 49 DDC_VGA, 50 DDC_CRT2, 51 DDC_LCD, 52 DDC_GPIO, 53 } RADEONLegacyDDCType; 54 55 typedef enum 56 { 57 CONNECTOR_NONE_LEGACY, 58 CONNECTOR_PROPRIETARY_LEGACY, 59 CONNECTOR_CRT_LEGACY, 60 CONNECTOR_DVI_I_LEGACY, 61 CONNECTOR_DVI_D_LEGACY, 62 CONNECTOR_CTV_LEGACY, 63 CONNECTOR_STV_LEGACY, 64 CONNECTOR_UNSUPPORTED_LEGACY 65 } RADEONLegacyConnectorType; 66 67 static Bool 68 radeon_read_bios(ScrnInfoPtr pScrn) 69 { 70 RADEONInfoPtr info = RADEONPTR(pScrn); 71 72 #ifdef XSERVER_LIBPCIACCESS 73 if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { 74 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 75 "Failed to read PCI ROM!\n"); 76 return FALSE; 77 } 78 #else 79 xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); 80 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 81 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 82 "Video BIOS not detected in PCI space!\n"); 83 if (xf86IsEntityPrimary(info->pEnt->index)) { 84 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 85 "Attempting to read Video BIOS from " 86 "legacy ISA space!\n"); 87 info->BIOSAddr = 0x000c0000; 88 xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, 89 RADEON_VBIOS_SIZE, info->VBIOS); 90 } 91 } 92 #endif 93 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) 94 return FALSE; 95 else 96 return TRUE; 97 } 98 99 static Bool 100 radeon_read_disabled_bios(ScrnInfoPtr pScrn) 101 { 102 RADEONInfoPtr info = RADEONPTR(pScrn); 103 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 104 unsigned char *RADEONMMIO = info->MMIO; 105 Bool ret; 106 107 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); 108 109 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 110 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 111 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 112 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 113 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 114 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 115 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 116 uint32_t cg_spll_func_cntl = 0; 117 uint32_t cg_spll_status; 118 119 /* disable VIP */ 120 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 121 122 /* enable the rom */ 123 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 124 125 /* Disable VGA mode */ 126 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 127 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 128 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 129 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 130 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 131 132 if (info->ChipFamily == CHIP_FAMILY_RV730) { 133 cg_spll_func_cntl = INREG(R600_CG_SPLL_FUNC_CNTL); 134 135 /* enable bypass mode */ 136 OUTREG(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); 137 138 /* wait for SPLL_CHG_STATUS to change to 1 */ 139 cg_spll_status = 0; 140 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 141 cg_spll_status = INREG(R600_CG_SPLL_STATUS); 142 143 OUTREG(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 144 } else 145 OUTREG(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 146 147 ret = radeon_read_bios(pScrn); 148 149 /* restore regs */ 150 if (info->ChipFamily == CHIP_FAMILY_RV730) { 151 OUTREG(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 152 153 /* wait for SPLL_CHG_STATUS to change to 1 */ 154 cg_spll_status = 0; 155 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 156 cg_spll_status = INREG(R600_CG_SPLL_STATUS); 157 } 158 OUTREG(RADEON_VIPH_CONTROL, viph_control); 159 OUTREG(RADEON_BUS_CNTL, bus_cntl); 160 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 161 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 162 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 163 OUTREG(R600_ROM_CNTL, rom_cntl); 164 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 165 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 166 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 167 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 168 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 169 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 170 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 171 uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); 172 uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); 173 uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 174 uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); 175 uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); 176 uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); 177 178 /* disable VIP */ 179 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 180 181 /* enable the rom */ 182 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 183 184 /* Disable VGA mode */ 185 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 186 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 187 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 188 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 189 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 190 191 OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 192 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 193 R600_SCK_OVERWRITE)); 194 195 OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 196 197 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); 198 199 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); 200 201 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); 202 203 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); 204 205 OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 206 207 ret = radeon_read_bios(pScrn); 208 209 /* restore regs */ 210 OUTREG(RADEON_VIPH_CONTROL, viph_control); 211 OUTREG(RADEON_BUS_CNTL, bus_cntl); 212 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 213 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 214 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 215 OUTREG(R600_ROM_CNTL, rom_cntl); 216 OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); 217 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 218 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 219 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 220 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 221 OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 222 223 } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { 224 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 225 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 226 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 227 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 228 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 229 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 230 uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); 231 uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); 232 uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); 233 234 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 235 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 236 237 OUTREG(RADEON_GPIOPAD_A, 0); 238 OUTREG(RADEON_GPIOPAD_EN, 0); 239 OUTREG(RADEON_GPIOPAD_MASK, 0); 240 241 /* disable VIP */ 242 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 243 244 /* enable the rom */ 245 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 246 247 /* Disable VGA mode */ 248 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 249 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 250 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 251 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 252 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 253 254 ret = radeon_read_bios(pScrn); 255 256 /* restore regs */ 257 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 258 OUTREG(RADEON_VIPH_CONTROL, viph_control); 259 OUTREG(RADEON_BUS_CNTL, bus_cntl); 260 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 261 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 262 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 263 OUTREG(RADEON_GPIOPAD_A, gpiopad_a); 264 OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); 265 OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); 266 267 } else { 268 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 269 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 270 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 271 uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 272 uint32_t crtc2_gen_cntl = 0; 273 uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 274 uint32_t fp2_gen_cntl = 0; 275 276 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 277 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); 278 279 if (pRADEONEnt->HasCRTC2) 280 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 281 282 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 283 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 284 285 /* disable VIP */ 286 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 287 288 /* enable the rom */ 289 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 290 291 /* Turn off mem requests and CRTC for both controllers */ 292 OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 293 (RADEON_CRTC_DISP_REQ_EN_B | 294 RADEON_CRTC_EXT_DISP_EN))); 295 if (pRADEONEnt->HasCRTC2) 296 OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 297 RADEON_CRTC2_DISP_REQ_EN_B)); 298 299 /* Turn off CRTC */ 300 OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 301 (RADEON_CRTC_SYNC_TRISTAT | 302 RADEON_CRTC_DISPLAY_DIS))); 303 304 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 305 OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 306 307 ret = radeon_read_bios(pScrn); 308 309 /* restore regs */ 310 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 311 OUTREG(RADEON_VIPH_CONTROL, viph_control); 312 OUTREG(RADEON_BUS_CNTL, bus_cntl); 313 OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 314 if (pRADEONEnt->HasCRTC2) 315 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 316 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 317 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 318 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 319 } 320 return ret; 321 } 322 323 Bool 324 radeon_card_posted(ScrnInfoPtr pScrn) 325 { 326 RADEONInfoPtr info = RADEONPTR(pScrn); 327 unsigned char *RADEONMMIO = info->MMIO; 328 uint32_t reg; 329 330 /* first check CRTCs */ 331 if (IS_AVIVO_VARIANT) { 332 reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); 333 if (reg & AVIVO_CRTC_EN) 334 return TRUE; 335 } else { 336 reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); 337 if (reg & RADEON_CRTC_EN) 338 return TRUE; 339 } 340 341 /* then check MEM_SIZE, in case something turned the crtcs off */ 342 if (info->ChipFamily >= CHIP_FAMILY_R600) 343 reg = INREG(R600_CONFIG_MEMSIZE); 344 else 345 reg = INREG(RADEON_CONFIG_MEMSIZE); 346 347 if (reg) 348 return TRUE; 349 350 return FALSE; 351 } 352 353 /* Read the Video BIOS block and the FP registers (if applicable). */ 354 Bool 355 RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 356 { 357 RADEONInfoPtr info = RADEONPTR(pScrn); 358 int tmp; 359 unsigned short dptr; 360 361 #ifdef XSERVER_LIBPCIACCESS 362 int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; 363 info->VBIOS = malloc(size); 364 #else 365 info->VBIOS = malloc(RADEON_VBIOS_SIZE); 366 #endif 367 if (!info->VBIOS) { 368 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 369 "Cannot allocate space for hold Video BIOS!\n"); 370 return FALSE; 371 } else { 372 if (pInt10) { 373 info->BIOSAddr = pInt10->BIOSseg << 4; 374 (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), 375 RADEON_VBIOS_SIZE); 376 } else if (!radeon_read_bios(pScrn)) 377 (void)radeon_read_disabled_bios(pScrn); 378 } 379 380 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 381 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 382 "Unrecognized BIOS signature, BIOS data will not be used\n"); 383 free (info->VBIOS); 384 info->VBIOS = NULL; 385 return FALSE; 386 } 387 388 /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */ 389 dptr = RADEON_BIOS16(0x18); 390 /* If PCI data signature is wrong assume x86 video BIOS anyway */ 391 if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 392 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 393 "ROM PCI data signature incorrect, ignoring\n"); 394 } 395 else if (info->VBIOS[dptr + 0x14] != 0x0) { 396 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 397 "Not an x86 BIOS ROM image, BIOS data will not be used\n"); 398 free (info->VBIOS); 399 info->VBIOS = NULL; 400 return FALSE; 401 } 402 403 if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48); 404 405 if(!info->ROMHeaderStart) { 406 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 407 "Invalid ROM pointer, BIOS data will not be used\n"); 408 free (info->VBIOS); 409 info->VBIOS = NULL; 410 return FALSE; 411 } 412 413 tmp = info->ROMHeaderStart + 4; 414 if ((RADEON_BIOS8(tmp) == 'A' && 415 RADEON_BIOS8(tmp+1) == 'T' && 416 RADEON_BIOS8(tmp+2) == 'O' && 417 RADEON_BIOS8(tmp+3) == 'M') || 418 (RADEON_BIOS8(tmp) == 'M' && 419 RADEON_BIOS8(tmp+1) == 'O' && 420 RADEON_BIOS8(tmp+2) == 'T' && 421 RADEON_BIOS8(tmp+3) == 'A')) 422 info->IsAtomBios = TRUE; 423 else 424 info->IsAtomBios = FALSE; 425 426 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", 427 info->IsAtomBios ? "ATOM":"Legacy"); 428 429 if (info->IsAtomBios) { 430 AtomBiosArgRec atomBiosArg; 431 432 if (RHDAtomBiosFunc(pScrn, NULL, ATOMBIOS_INIT, &atomBiosArg) 433 == ATOM_SUCCESS) { 434 info->atomBIOS = atomBiosArg.atomhandle; 435 } 436 437 atomBiosArg.fb.start = info->FbFreeStart; 438 atomBiosArg.fb.size = info->FbFreeSize; 439 if (RHDAtomBiosFunc(pScrn, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, 440 &atomBiosArg) == ATOM_SUCCESS) { 441 442 info->FbFreeStart = atomBiosArg.fb.start; 443 info->FbFreeSize = atomBiosArg.fb.size; 444 } 445 446 RHDAtomBiosFunc(pScrn, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, 447 &atomBiosArg); 448 RHDAtomBiosFunc(pScrn, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, 449 &atomBiosArg); 450 RHDAtomBiosFunc(pScrn, info->atomBIOS, 451 GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 452 RHDAtomBiosFunc(pScrn, info->atomBIOS, 453 GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 454 RHDAtomBiosFunc(pScrn, info->atomBIOS, 455 GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 456 RHDAtomBiosFunc(pScrn, info->atomBIOS, 457 GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 458 RHDAtomBiosFunc(pScrn, info->atomBIOS, 459 GET_MAX_PIXEL_CLK, &atomBiosArg); 460 RHDAtomBiosFunc(pScrn, info->atomBIOS, 461 GET_REF_CLOCK, &atomBiosArg); 462 463 info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); 464 } 465 466 /* We are a bit too quick at using this "unposted" to re-post the 467 * card. This causes some problems with VT switch on some machines, 468 * so let's work around this for now by only POSTing if none of the 469 * CRTCs are enabled 470 */ 471 if ((!radeon_card_posted(pScrn)) && info->VBIOS) { 472 if (info->IsAtomBios) { 473 if (!rhdAtomASICInit(info->atomBIOS)) 474 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 475 "%s: AsicInit failed.\n",__func__); 476 } else { 477 #if 0 478 /* FIX ME */ 479 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); 480 RADEONGetBIOSInitTableOffsets(pScrn); 481 RADEONPostCardFromBIOSTables(pScrn); 482 #endif 483 } 484 } 485 486 return TRUE; 487 } 488 489 static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 490 { 491 RADEONInfoPtr info = RADEONPTR (pScrn); 492 493 if (!info->VBIOS) return FALSE; 494 495 if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) 496 return TRUE; 497 498 if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn)) 499 return TRUE; 500 501 return FALSE; 502 } 503 504 static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) 505 { 506 RADEONInfoPtr info = RADEONPTR (pScrn); 507 508 /* XPRESS DDC quirks */ 509 if ((info->ChipFamily == CHIP_FAMILY_RS400 || 510 info->ChipFamily == CHIP_FAMILY_RS480) && 511 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 512 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 513 } else if ((info->ChipFamily == CHIP_FAMILY_RS400 || 514 info->ChipFamily == CHIP_FAMILY_RS480) && 515 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) { 516 info->BiosConnector[index].ddc_i2c.valid = TRUE; 517 info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8); 518 info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80; 519 info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8); 520 info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80; 521 info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8); 522 info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80; 523 info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8); 524 info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80; 525 info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 526 info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 527 info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A; 528 info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A; 529 info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN; 530 info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN; 531 info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 532 info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 533 } 534 535 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 536 if ((IS_R300_VARIANT) && 537 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) 538 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 539 540 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 541 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 542 if (info->Chipset == PCI_CHIP_RN50_515E && 543 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) { 544 if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && 545 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 546 info->BiosConnector[index].valid = FALSE; 547 } 548 } 549 550 /* X300 card with extra non-existent DVI port */ 551 if (info->Chipset == PCI_CHIP_RV370_5B60 && 552 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && 553 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && 554 index == 2) { 555 if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { 556 info->BiosConnector[index].valid = FALSE; 557 } 558 } 559 560 /* r200 card with primary dac routed to both VGA and DVI - disable load detection 561 * otherwise you end up detecing load if either port is attached 562 */ 563 if (info->Chipset == PCI_CHIP_R200_QL && 564 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1569 && 565 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x514c && 566 (info->BiosConnector[index].devices & ATOM_DEVICE_CRT1_SUPPORT)) { 567 info->BiosConnector[index].load_detection = FALSE; 568 } 569 570 } 571 572 static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 573 { 574 RADEONInfoPtr info = RADEONPTR (pScrn); 575 int offset, i, entry, tmp, tmp0, tmp1; 576 RADEONLegacyDDCType DDCType; 577 RADEONLegacyConnectorType ConnectorType; 578 579 if (!info->VBIOS) return FALSE; 580 581 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x50); 582 if (offset) { 583 for (i = 0; i < 4; i++) { 584 entry = offset + 2 + i*2; 585 586 if (!RADEON_BIOS16(entry)) { 587 break; 588 } 589 info->BiosConnector[i].valid = TRUE; 590 tmp = RADEON_BIOS16(entry); 591 info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; 592 ConnectorType = (tmp >> 12) & 0xf; 593 switch (ConnectorType) { 594 case CONNECTOR_PROPRIETARY_LEGACY: 595 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 596 if ((tmp >> 4) & 0x1) { 597 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 598 if (!radeon_add_encoder(pScrn, 599 radeon_get_encoder_id_from_supported_device(pScrn, 600 ATOM_DEVICE_DFP2_SUPPORT, 601 0), 602 ATOM_DEVICE_DFP2_SUPPORT)) 603 return FALSE; 604 } else { 605 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 606 if (!radeon_add_encoder(pScrn, 607 radeon_get_encoder_id_from_supported_device(pScrn, 608 ATOM_DEVICE_DFP1_SUPPORT, 609 0), 610 ATOM_DEVICE_DFP1_SUPPORT)) 611 return FALSE; 612 } 613 break; 614 case CONNECTOR_CRT_LEGACY: 615 info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; 616 if (tmp & 0x1) { 617 info->BiosConnector[i].load_detection = FALSE; 618 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 619 if (!radeon_add_encoder(pScrn, 620 radeon_get_encoder_id_from_supported_device(pScrn, 621 ATOM_DEVICE_CRT2_SUPPORT, 622 2), 623 ATOM_DEVICE_CRT2_SUPPORT)) 624 return FALSE; 625 } else { 626 info->BiosConnector[i].load_detection = TRUE; 627 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 628 if (!radeon_add_encoder(pScrn, 629 radeon_get_encoder_id_from_supported_device(pScrn, 630 ATOM_DEVICE_CRT1_SUPPORT, 631 1), 632 ATOM_DEVICE_CRT1_SUPPORT)) 633 return FALSE; 634 } 635 break; 636 case CONNECTOR_DVI_I_LEGACY: 637 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; 638 if (tmp & 0x1) { 639 info->BiosConnector[i].load_detection = FALSE; 640 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 641 if (!radeon_add_encoder(pScrn, 642 radeon_get_encoder_id_from_supported_device(pScrn, 643 ATOM_DEVICE_CRT2_SUPPORT, 644 2), 645 ATOM_DEVICE_CRT2_SUPPORT)) 646 return FALSE; 647 } else { 648 info->BiosConnector[i].load_detection = TRUE; 649 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 650 if (!radeon_add_encoder(pScrn, 651 radeon_get_encoder_id_from_supported_device(pScrn, 652 ATOM_DEVICE_CRT1_SUPPORT, 653 1), 654 ATOM_DEVICE_CRT1_SUPPORT)) 655 return FALSE; 656 } 657 if ((tmp >> 4) & 0x1) { 658 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 659 if (!radeon_add_encoder(pScrn, 660 radeon_get_encoder_id_from_supported_device(pScrn, 661 ATOM_DEVICE_DFP2_SUPPORT, 662 0), 663 ATOM_DEVICE_DFP2_SUPPORT)) 664 return FALSE; 665 } else { 666 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 667 if (!radeon_add_encoder(pScrn, 668 radeon_get_encoder_id_from_supported_device(pScrn, 669 ATOM_DEVICE_DFP1_SUPPORT, 670 0), 671 ATOM_DEVICE_DFP1_SUPPORT)) 672 return FALSE; 673 } 674 break; 675 case CONNECTOR_DVI_D_LEGACY: 676 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 677 if ((tmp >> 4) & 0x1) { 678 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 679 if (!radeon_add_encoder(pScrn, 680 radeon_get_encoder_id_from_supported_device(pScrn, 681 ATOM_DEVICE_DFP2_SUPPORT, 682 0), 683 ATOM_DEVICE_DFP2_SUPPORT)) 684 return FALSE; 685 } else { 686 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 687 if (!radeon_add_encoder(pScrn, 688 radeon_get_encoder_id_from_supported_device(pScrn, 689 ATOM_DEVICE_DFP1_SUPPORT, 690 0), 691 ATOM_DEVICE_DFP1_SUPPORT)) 692 return FALSE; 693 } 694 break; 695 case CONNECTOR_CTV_LEGACY: 696 info->BiosConnector[i].ConnectorType = CONNECTOR_CTV; 697 info->BiosConnector[i].load_detection = FALSE; 698 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 699 if (!radeon_add_encoder(pScrn, 700 radeon_get_encoder_id_from_supported_device(pScrn, 701 ATOM_DEVICE_TV1_SUPPORT, 702 2), 703 ATOM_DEVICE_TV1_SUPPORT)) 704 return FALSE; 705 break; 706 case CONNECTOR_STV_LEGACY: 707 info->BiosConnector[i].ConnectorType = CONNECTOR_STV; 708 info->BiosConnector[i].load_detection = FALSE; 709 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 710 if (!radeon_add_encoder(pScrn, 711 radeon_get_encoder_id_from_supported_device(pScrn, 712 ATOM_DEVICE_TV1_SUPPORT, 713 2), 714 ATOM_DEVICE_TV1_SUPPORT)) 715 return FALSE; 716 break; 717 default: 718 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType); 719 info->BiosConnector[i].valid = FALSE; 720 break; 721 } 722 723 info->BiosConnector[i].ddc_i2c.valid = FALSE; 724 725 DDCType = (tmp >> 8) & 0xf; 726 switch (DDCType) { 727 case DDC_MONID: 728 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 729 break; 730 case DDC_DVI: 731 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 732 break; 733 case DDC_VGA: 734 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 735 break; 736 case DDC_CRT2: 737 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 738 break; 739 default: 740 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 741 break; 742 } 743 744 RADEONApplyLegacyQuirks(pScrn, i); 745 746 } 747 } else { 748 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); 749 750 /* old radeons and r128 didn't use connector tables you just check 751 * for LVDS, DVI, TV, etc. tables 752 */ 753 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 754 if (offset) { 755 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 756 "Found DFP table, assuming DVI connector\n"); 757 info->BiosConnector[0].valid = TRUE; 758 info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; 759 info->BiosConnector[0].load_detection = TRUE; 760 info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 761 info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; 762 if (!radeon_add_encoder(pScrn, 763 radeon_get_encoder_id_from_supported_device(pScrn, 764 ATOM_DEVICE_DFP1_SUPPORT, 765 0), 766 ATOM_DEVICE_DFP1_SUPPORT)) 767 return FALSE; 768 if (!radeon_add_encoder(pScrn, 769 radeon_get_encoder_id_from_supported_device(pScrn, 770 ATOM_DEVICE_CRT1_SUPPORT, 771 1), 772 ATOM_DEVICE_CRT1_SUPPORT)) 773 return FALSE; 774 } else 775 return FALSE; 776 } 777 778 /* check LVDS table */ 779 /* IGP can be mobile or desktop so check the connectors */ 780 if (info->IsMobility || info->IsIGP) { 781 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 782 if (offset) { 783 info->BiosConnector[4].valid = TRUE; 784 info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS; 785 info->BiosConnector[4].ddc_i2c.valid = FALSE; 786 787 info->BiosConnector[4].devices = ATOM_DEVICE_LCD1_SUPPORT; 788 if (!radeon_add_encoder(pScrn, 789 radeon_get_encoder_id_from_supported_device(pScrn, 790 ATOM_DEVICE_LCD1_SUPPORT, 791 0), 792 ATOM_DEVICE_LCD1_SUPPORT)) 793 return FALSE; 794 795 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 796 if (tmp) { 797 tmp0 = RADEON_BIOS16(tmp + 0x15); 798 if (tmp0) { 799 tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; 800 if (tmp1) { 801 DDCType = tmp1; 802 switch (DDCType) { 803 case DDC_NONE_DETECTED: 804 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); 805 break; 806 case DDC_MONID: 807 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 808 break; 809 case DDC_DVI: 810 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 811 break; 812 case DDC_VGA: 813 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 814 break; 815 case DDC_CRT2: 816 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 817 break; 818 case DDC_LCD: 819 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); 820 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 821 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 822 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 823 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 824 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 825 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 826 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 827 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 828 break; 829 case DDC_GPIO: 830 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); 831 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 832 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 833 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 834 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 835 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 836 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 837 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 838 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 839 break; 840 default: 841 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 842 break; 843 } 844 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); 845 } 846 } 847 } else 848 info->BiosConnector[4].ddc_i2c.valid = FALSE; 849 } 850 } 851 852 /* check TV table */ 853 if (info->InternalTVOut) { 854 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 855 if (offset) { 856 if (RADEON_BIOS8(offset + 6) == 'T') { 857 info->BiosConnector[5].valid = TRUE; 858 /* assume s-video for now */ 859 info->BiosConnector[5].ConnectorType = CONNECTOR_STV; 860 info->BiosConnector[5].load_detection = FALSE; 861 info->BiosConnector[5].ddc_i2c.valid = FALSE; 862 info->BiosConnector[5].devices = ATOM_DEVICE_TV1_SUPPORT; 863 if (!radeon_add_encoder(pScrn, 864 radeon_get_encoder_id_from_supported_device(pScrn, 865 ATOM_DEVICE_TV1_SUPPORT, 866 2), 867 ATOM_DEVICE_TV1_SUPPORT)) 868 return FALSE; 869 } 870 } 871 } 872 873 return TRUE; 874 } 875 876 Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 877 { 878 RADEONInfoPtr info = RADEONPTR (pScrn); 879 880 if(!info->VBIOS) return FALSE; 881 882 if (info->IsAtomBios) 883 return RADEONGetATOMConnectorInfoFromBIOS(pScrn); 884 else 885 return RADEONGetLegacyConnectorInfoFromBIOS(pScrn); 886 } 887 888 Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) { 889 ScrnInfoPtr pScrn = output->scrn; 890 RADEONInfoPtr info = RADEONPTR(pScrn); 891 RADEONOutputPrivatePtr radeon_output = output->driver_private; 892 radeon_tvout_ptr tvout = &radeon_output->tvout; 893 int offset, refclk, stds; 894 895 if (!info->VBIOS) return FALSE; 896 897 if (info->IsAtomBios) 898 return RADEONGetATOMTVInfo(output); 899 else { 900 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 901 if (offset) { 902 if (RADEON_BIOS8(offset + 6) == 'T') { 903 switch (RADEON_BIOS8(offset + 7) & 0xf) { 904 case 1: 905 tvout->default_tvStd = TV_STD_NTSC; 906 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n"); 907 break; 908 case 2: 909 tvout->default_tvStd = TV_STD_PAL; 910 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n"); 911 break; 912 case 3: 913 tvout->default_tvStd = TV_STD_PAL_M; 914 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n"); 915 break; 916 case 4: 917 tvout->default_tvStd = TV_STD_PAL_60; 918 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n"); 919 break; 920 case 5: 921 tvout->default_tvStd = TV_STD_NTSC_J; 922 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n"); 923 break; 924 case 6: 925 tvout->default_tvStd = TV_STD_SCART_PAL; 926 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n"); 927 break; 928 default: 929 tvout->default_tvStd = TV_STD_NTSC; 930 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n"); 931 break; 932 } 933 tvout->tvStd = tvout->default_tvStd; 934 935 refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3; 936 if (refclk == 0) 937 tvout->TVRefClk = 29.498928713; /* MHz */ 938 else if (refclk == 1) 939 tvout->TVRefClk = 28.636360000; 940 else if (refclk == 2) 941 tvout->TVRefClk = 14.318180000; 942 else if (refclk == 3) 943 tvout->TVRefClk = 27.000000000; 944 945 tvout->SupportedTVStds = tvout->default_tvStd; 946 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: "); 947 stds = RADEON_BIOS8(offset + 10) & 0x1f; 948 if (stds & TV_STD_NTSC) { 949 tvout->SupportedTVStds |= TV_STD_NTSC; 950 ErrorF("NTSC "); 951 } 952 if (stds & TV_STD_PAL) { 953 tvout->SupportedTVStds |= TV_STD_PAL; 954 ErrorF("PAL "); 955 } 956 if (stds & TV_STD_PAL_M) { 957 tvout->SupportedTVStds |= TV_STD_PAL_M; 958 ErrorF("PAL-M "); 959 } 960 if (stds & TV_STD_PAL_60) { 961 tvout->SupportedTVStds |= TV_STD_PAL_60; 962 ErrorF("PAL-60 "); 963 } 964 if (stds & TV_STD_NTSC_J) { 965 tvout->SupportedTVStds |= TV_STD_NTSC_J; 966 ErrorF("NTSC-J "); 967 } 968 if (stds & TV_STD_SCART_PAL) { 969 tvout->SupportedTVStds |= TV_STD_SCART_PAL; 970 ErrorF("SCART-PAL"); 971 } 972 ErrorF("\n"); 973 974 return TRUE; 975 } 976 } 977 } 978 return FALSE; 979 } 980 981 /* Read PLL parameters from BIOS block. Default to typical values if there 982 is no BIOS. */ 983 Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) 984 { 985 RADEONInfoPtr info = RADEONPTR (pScrn); 986 RADEONPLLPtr pll = &info->pll; 987 uint16_t pll_info_block; 988 989 if (!info->VBIOS) { 990 return FALSE; 991 } else { 992 if (info->IsAtomBios) { 993 return RADEONGetATOMClockInfo(pScrn); 994 } else { 995 int rev; 996 997 pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); 998 999 rev = RADEON_BIOS8(pll_info_block); 1000 1001 pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); 1002 pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); 1003 pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); 1004 pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); 1005 1006 if (rev > 9) { 1007 pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36); 1008 pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a); 1009 } else { 1010 pll->pll_in_min = 40; 1011 pll->pll_in_max = 500; 1012 } 1013 1014 pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); 1015 1016 info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; 1017 info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; 1018 } 1019 1020 if (info->sclk == 0) info->sclk = 200; 1021 if (info->mclk == 0) info->mclk = 200; 1022 } 1023 1024 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_out_pll: %u, " 1025 "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, " 1026 "sclk: %f, mclk: %f\n", 1027 pll->reference_freq, (unsigned)pll->pll_out_min, 1028 (unsigned)pll->pll_out_max, (unsigned)pll->pll_in_min, 1029 (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk); 1030 1031 return TRUE; 1032 } 1033 1034 Bool RADEONGetDAC2InfoFromBIOS (ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) 1035 { 1036 RADEONInfoPtr info = RADEONPTR(pScrn); 1037 int offset, rev, bg, dac; 1038 1039 if (!info->VBIOS) return FALSE; 1040 1041 if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TVDAC_ADJ, FALSE)) 1042 return FALSE; 1043 1044 if (info->IsAtomBios) { 1045 /* not implemented yet */ 1046 return FALSE; 1047 } else { 1048 /* first check TV table */ 1049 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 1050 if (offset) { 1051 rev = RADEON_BIOS8(offset + 0x3); 1052 if (rev > 4) { 1053 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1054 dac = RADEON_BIOS8(offset + 0xd) & 0xf; 1055 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1056 1057 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1058 dac = RADEON_BIOS8(offset + 0xf) & 0xf; 1059 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1060 1061 bg = RADEON_BIOS8(offset + 0x10) & 0xf; 1062 dac = RADEON_BIOS8(offset + 0x11) & 0xf; 1063 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1064 1065 return TRUE; 1066 } else if (rev > 1) { 1067 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1068 dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; 1069 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1070 1071 bg = RADEON_BIOS8(offset + 0xd) & 0xf; 1072 dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf; 1073 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1074 1075 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1076 dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf; 1077 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1078 1079 return TRUE; 1080 } 1081 } 1082 /* then check CRT table */ 1083 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x60); 1084 if (offset) { 1085 rev = RADEON_BIOS8(offset) & 0x3; 1086 if (rev < 2) { 1087 bg = RADEON_BIOS8(offset + 0x3) & 0xf; 1088 dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf; 1089 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1090 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1091 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1092 1093 return TRUE; 1094 } else { 1095 bg = RADEON_BIOS8(offset + 0x4) & 0xf; 1096 dac = RADEON_BIOS8(offset + 0x5) & 0xf; 1097 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1098 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1099 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1100 1101 return TRUE; 1102 } 1103 } 1104 } 1105 1106 return FALSE; 1107 } 1108 1109 Bool 1110 RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) 1111 { 1112 RADEONInfoPtr info = RADEONPTR(pScrn); 1113 radeon_native_mode_ptr native_mode = &lvds->native_mode; 1114 unsigned long tmp, i; 1115 1116 if (!info->VBIOS) 1117 return FALSE; 1118 1119 if (!info->IsAtomBios) { 1120 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 1121 1122 if (!tmp) { 1123 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1124 "No Panel Info Table found in BIOS!\n"); 1125 return FALSE; 1126 } else { 1127 char stmp[30]; 1128 int tmp0; 1129 1130 for (i = 0; i < 24; i++) 1131 stmp[i] = RADEON_BIOS8(tmp+i+1); 1132 stmp[24] = 0; 1133 1134 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1135 "Panel ID string: %s\n", stmp); 1136 1137 native_mode->PanelXRes = RADEON_BIOS16(tmp+25); 1138 native_mode->PanelYRes = RADEON_BIOS16(tmp+27); 1139 xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", 1140 native_mode->PanelXRes, native_mode->PanelYRes); 1141 1142 lvds->PanelPwrDly = RADEON_BIOS16(tmp+44); 1143 if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0) 1144 lvds->PanelPwrDly = 2000; 1145 1146 /* some panels only work well with certain divider combinations. 1147 */ 1148 info->RefDivider = RADEON_BIOS16(tmp+46); 1149 info->PostDivider = RADEON_BIOS8(tmp+48); 1150 info->FeedbackDivider = RADEON_BIOS16(tmp+49); 1151 if ((info->RefDivider != 0) && 1152 (info->FeedbackDivider > 3)) { 1153 info->UseBiosDividers = TRUE; 1154 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1155 "BIOS provided dividers will be used.\n"); 1156 } 1157 1158 /* We don't use a while loop here just in case we have a corrupted BIOS image. 1159 The max number of table entries is 23 at present, but may grow in future. 1160 To ensure it works with future revisions we loop it to 32. 1161 */ 1162 for (i = 0; i < 32; i++) { 1163 tmp0 = RADEON_BIOS16(tmp+64+i*2); 1164 if (tmp0 == 0) break; 1165 if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) && 1166 (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) { 1167 native_mode->HBlank = (RADEON_BIOS16(tmp0+17) - 1168 RADEON_BIOS16(tmp0+19)) * 8; 1169 native_mode->HOverPlus = (RADEON_BIOS16(tmp0+21) - 1170 RADEON_BIOS16(tmp0+19) - 1) * 8; 1171 native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; 1172 native_mode->VBlank = (RADEON_BIOS16(tmp0+24) - 1173 RADEON_BIOS16(tmp0+26)); 1174 native_mode->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - 1175 RADEON_BIOS16(tmp0+26)); 1176 native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); 1177 native_mode->DotClock = RADEON_BIOS16(tmp0+9) * 10; 1178 native_mode->Flags = 0; 1179 } 1180 } 1181 } 1182 1183 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1184 "LVDS Info:\n" 1185 "XRes: %d, YRes: %d, DotClock: %d\n" 1186 "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" 1187 "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", 1188 native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock, 1189 native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth, 1190 native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); 1191 1192 return TRUE; 1193 } 1194 return FALSE; 1195 } 1196 1197 xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) 1198 { 1199 ScrnInfoPtr pScrn = output->scrn; 1200 RADEONInfoPtr info = RADEONPTR(pScrn); 1201 unsigned long tmp; 1202 unsigned char edid[256]; 1203 xf86MonPtr mon = NULL; 1204 1205 if (!info->VBIOS) 1206 return mon; 1207 1208 if (!info->IsAtomBios) { 1209 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c); 1210 if (tmp) { 1211 memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256); 1212 if (edid[1] == 0xff) 1213 mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); 1214 } 1215 } 1216 1217 return mon; 1218 } 1219 1220 Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) 1221 { 1222 RADEONInfoPtr info = RADEONPTR(pScrn); 1223 uint32_t tmp, maxfreq; 1224 int i, n; 1225 1226 if (!info->VBIOS) return FALSE; 1227 1228 if (info->IsAtomBios) { 1229 if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) { 1230 1231 maxfreq = RADEON_BIOS16(tmp+4); 1232 1233 for (i=0; i<4; i++) { 1234 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6); 1235 /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */ 1236 tmds->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) | 1237 ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) | 1238 ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | 1239 ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); 1240 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1241 "TMDS PLL from BIOS: %u %x\n", 1242 (unsigned)tmds->tmds_pll[i].freq, 1243 (unsigned)tmds->tmds_pll[i].value); 1244 1245 if (maxfreq == tmds->tmds_pll[i].freq) { 1246 tmds->tmds_pll[i].freq = 0xffffffff; 1247 break; 1248 } 1249 } 1250 return TRUE; 1251 } 1252 } else { 1253 1254 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 1255 if (tmp) { 1256 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1257 "DFP table revision: %d\n", RADEON_BIOS8(tmp)); 1258 if (RADEON_BIOS8(tmp) == 3) { 1259 n = RADEON_BIOS8(tmp + 5) + 1; 1260 if (n > 4) n = 4; 1261 for (i=0; i<n; i++) { 1262 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); 1263 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); 1264 } 1265 return TRUE; 1266 } else if (RADEON_BIOS8(tmp) == 4) { 1267 int stride = 0; 1268 n = RADEON_BIOS8(tmp + 5) + 1; 1269 if (n > 4) n = 4; 1270 for (i=0; i<n; i++) { 1271 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); 1272 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); 1273 if (i == 0) stride += 10; 1274 else stride += 6; 1275 } 1276 return TRUE; 1277 } 1278 } 1279 } 1280 return FALSE; 1281 } 1282 1283 static RADEONI2CBusRec 1284 RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id) 1285 { 1286 RADEONInfoPtr info = RADEONPTR (pScrn); 1287 int offset, blocks, i; 1288 RADEONI2CBusRec i2c; 1289 1290 memset(&i2c, 0, sizeof(RADEONI2CBusRec)); 1291 i2c.valid = FALSE; 1292 1293 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70); 1294 if (offset) { 1295 blocks = RADEON_BIOS8(offset + 2); 1296 for (i = 0; i < blocks; i++) { 1297 int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0); 1298 if (id == i2c_id) { 1299 int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3); 1300 int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4); 1301 1302 i2c.mask_clk_mask = (1 << clock_shift); 1303 i2c.mask_data_mask = (1 << data_shift); 1304 i2c.a_clk_mask = (1 << clock_shift); 1305 i2c.a_data_mask = (1 << data_shift); 1306 i2c.put_clk_mask = (1 << clock_shift); 1307 i2c.put_data_mask = (1 << data_shift); 1308 i2c.get_clk_mask = (1 << clock_shift); 1309 i2c.get_data_mask = (1 << data_shift); 1310 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 1311 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 1312 i2c.a_clk_reg = RADEON_GPIOPAD_A; 1313 i2c.a_data_reg = RADEON_GPIOPAD_A; 1314 i2c.put_clk_reg = RADEON_GPIOPAD_EN; 1315 i2c.put_data_reg = RADEON_GPIOPAD_EN; 1316 i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 1317 i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 1318 i2c.valid = TRUE; 1319 break; 1320 } 1321 } 1322 } 1323 return i2c; 1324 } 1325 1326 Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) 1327 { 1328 RADEONInfoPtr info = RADEONPTR(pScrn); 1329 int offset, table_start, max_freq, gpio_reg, flags; 1330 1331 if (!info->VBIOS) 1332 return FALSE; 1333 1334 if (info->IsAtomBios) 1335 return FALSE; 1336 else if (info->IsIGP) { 1337 /* RS4xx TMDS stuff is in the mobile table */ 1338 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1339 if (offset) { 1340 int rev = RADEON_BIOS8(offset); 1341 if (rev >= 6) { 1342 offset = RADEON_BIOS16(offset + 0x17); 1343 if (offset) { 1344 offset = RADEON_BIOS16(offset + 2); 1345 rev = RADEON_BIOS8(offset); 1346 if (offset && (rev > 1)) { 1347 int blocks = RADEON_BIOS8(offset + 3); 1348 int index = offset + 4; 1349 dvo->dvo_i2c.valid = FALSE; 1350 while (blocks > 0) { 1351 int id = RADEON_BIOS16(index); 1352 index += 2; 1353 switch (id >> 13) { 1354 case 0: 1355 index += 6; 1356 break; 1357 case 2: 1358 index += 10; 1359 break; 1360 case 3: 1361 index += 2; 1362 break; 1363 case 4: 1364 index += 2; 1365 break; 1366 case 6: 1367 dvo->dvo_i2c_slave_addr = 1368 RADEON_BIOS16(index) & 0xff; 1369 index += 2; 1370 dvo->dvo_i2c = 1371 RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index)); 1372 return TRUE; 1373 default: 1374 break; 1375 } 1376 blocks--; 1377 } 1378 } 1379 } 1380 } 1381 } else { 1382 dvo->dvo_i2c_slave_addr = 0x70; 1383 dvo->dvo_i2c = RADEONLookupI2CBlock(pScrn, 136); 1384 info->ext_tmds_chip = RADEON_SIL_164; 1385 } 1386 } else { 1387 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1388 if (offset) { 1389 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1390 "External TMDS Table revision: %d\n", 1391 RADEON_BIOS8(offset)); 1392 table_start = offset+4; 1393 max_freq = RADEON_BIOS16(table_start); 1394 dvo->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2); 1395 dvo->dvo_i2c.valid = FALSE; 1396 gpio_reg = RADEON_BIOS8(table_start+3); 1397 if (gpio_reg == 1) 1398 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1399 else if (gpio_reg == 2) 1400 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 1401 else if (gpio_reg == 3) 1402 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1403 else if (gpio_reg == 4) { 1404 if (IS_R300_VARIANT) 1405 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1406 else 1407 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 1408 } else if (gpio_reg == 5) { 1409 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1410 "unsupported MM gpio_reg\n"); 1411 return FALSE; 1412 } else { 1413 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1414 "Unknown gpio reg: %d\n", gpio_reg); 1415 return FALSE; 1416 } 1417 flags = RADEON_BIOS8(table_start+5); 1418 dvo->dvo_duallink = flags & 0x01; 1419 if (dvo->dvo_duallink) { 1420 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1421 "Duallink TMDS detected\n"); 1422 } 1423 return TRUE; 1424 } 1425 } 1426 1427 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1428 "No External TMDS Table found\n"); 1429 1430 return FALSE; 1431 } 1432 1433 Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) 1434 { 1435 ScrnInfoPtr pScrn = output->scrn; 1436 RADEONInfoPtr info = RADEONPTR(pScrn); 1437 unsigned char *RADEONMMIO = info->MMIO; 1438 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1439 radeon_dvo_ptr dvo = NULL; 1440 int offset, index, id; 1441 uint32_t val, reg, and_mask, or_mask; 1442 1443 if (radeon_encoder == NULL) 1444 return FALSE; 1445 1446 dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; 1447 1448 if (dvo == NULL) 1449 return FALSE; 1450 1451 if (!info->VBIOS) 1452 return FALSE; 1453 1454 if (info->IsAtomBios) 1455 return FALSE; 1456 else if (info->IsIGP) { 1457 /* RS4xx TMDS stuff is in the mobile table */ 1458 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1459 if (offset) { 1460 int rev = RADEON_BIOS8(offset); 1461 if (rev >= 6) { 1462 offset = RADEON_BIOS16(offset + 0x17); 1463 if (offset) { 1464 offset = RADEON_BIOS16(offset + 2); 1465 rev = RADEON_BIOS8(offset); 1466 if (offset && (rev > 1)) { 1467 int blocks = RADEON_BIOS8(offset + 3); 1468 index = offset + 4; 1469 while (blocks > 0) { 1470 id = RADEON_BIOS16(index); 1471 index += 2; 1472 switch (id >> 13) { 1473 case 0: 1474 reg = (id & 0x1fff) * 4; 1475 val = RADEON_BIOS32(index); 1476 index += 4; 1477 ErrorF("MMIO: 0x%x 0x%x\n", 1478 (unsigned)reg, (unsigned)val); 1479 OUTREG(reg, val); 1480 break; 1481 case 2: 1482 reg = (id & 0x1fff) * 4; 1483 and_mask = RADEON_BIOS32(index); 1484 index += 4; 1485 or_mask = RADEON_BIOS32(index); 1486 index += 4; 1487 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1488 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1489 val = INREG(reg); 1490 val = (val & and_mask) | or_mask; 1491 OUTREG(reg, val); 1492 break; 1493 case 3: 1494 val = RADEON_BIOS16(index); 1495 index += 2; 1496 ErrorF("delay: %u\n", (unsigned)val); 1497 usleep(val); 1498 break; 1499 case 4: 1500 val = RADEON_BIOS16(index); 1501 index += 2; 1502 ErrorF("delay: %u\n", (unsigned)val * 1000); 1503 usleep(val * 1000); 1504 break; 1505 case 6: 1506 index++; 1507 reg = RADEON_BIOS8(index); 1508 index++; 1509 val = RADEON_BIOS8(index); 1510 index++; 1511 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1512 (unsigned)val); 1513 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1514 break; 1515 default: 1516 ErrorF("unknown id %d\n", id>>13); 1517 return FALSE; 1518 } 1519 blocks--; 1520 } 1521 return TRUE; 1522 } 1523 } 1524 } 1525 } 1526 } else { 1527 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1528 if (offset) { 1529 index = offset+10; 1530 id = RADEON_BIOS16(index); 1531 while (id != 0xffff) { 1532 index += 2; 1533 switch(id >> 13) { 1534 case 0: 1535 reg = (id & 0x1fff) * 4; 1536 val = RADEON_BIOS32(index); 1537 index += 4; 1538 ErrorF("MMIO: 0x%x 0x%x\n", 1539 (unsigned)reg, (unsigned)val); 1540 OUTREG(reg, val); 1541 break; 1542 case 2: 1543 reg = (id & 0x1fff) * 4; 1544 and_mask = RADEON_BIOS32(index); 1545 index += 4; 1546 or_mask = RADEON_BIOS32(index); 1547 index += 4; 1548 val = INREG(reg); 1549 val = (val & and_mask) | or_mask; 1550 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1551 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1552 OUTREG(reg, val); 1553 break; 1554 case 4: 1555 val = RADEON_BIOS16(index); 1556 index += 2; 1557 ErrorF("delay: %u\n", (unsigned)val); 1558 usleep(val); 1559 break; 1560 case 5: 1561 reg = id & 0x1fff; 1562 and_mask = RADEON_BIOS32(index); 1563 index += 4; 1564 or_mask = RADEON_BIOS32(index); 1565 index += 4; 1566 ErrorF("PLL mask: 0x%x 0x%x 0x%x\n", 1567 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1568 val = INPLL(pScrn, reg); 1569 val = (val & and_mask) | or_mask; 1570 OUTPLL(pScrn, reg, val); 1571 break; 1572 case 6: 1573 reg = id & 0x1fff; 1574 val = RADEON_BIOS8(index); 1575 index += 1; 1576 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1577 (unsigned)val); 1578 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1579 break; 1580 default: 1581 ErrorF("unknown id %d\n", id>>13); 1582 return FALSE; 1583 }; 1584 id = RADEON_BIOS16(index); 1585 } 1586 return TRUE; 1587 } 1588 } 1589 1590 return FALSE; 1591 } 1592 1593 /* support for init from bios tables 1594 * 1595 * Based heavily on the netbsd radeonfb driver 1596 * Written by Garrett D'Amore 1597 * Copyright (c) 2006 Itronix Inc. 1598 * 1599 */ 1600 1601 /* bios table defines */ 1602 1603 #define RADEON_TABLE_ENTRY_FLAG_MASK 0xe000 1604 #define RADEON_TABLE_ENTRY_INDEX_MASK 0x1fff 1605 #define RADEON_TABLE_ENTRY_COMMAND_MASK 0x00ff 1606 1607 #define RADEON_TABLE_FLAG_WRITE_INDEXED 0x0000 1608 #define RADEON_TABLE_FLAG_WRITE_DIRECT 0x2000 1609 #define RADEON_TABLE_FLAG_MASK_INDEXED 0x4000 1610 #define RADEON_TABLE_FLAG_MASK_DIRECT 0x6000 1611 #define RADEON_TABLE_FLAG_DELAY 0x8000 1612 #define RADEON_TABLE_FLAG_SCOMMAND 0xa000 1613 1614 #define RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK 0x03 1615 #define RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE 0x08 1616 1617 #define RADEON_PLL_FLAG_MASK 0xc0 1618 #define RADEON_PLL_INDEX_MASK 0x3f 1619 1620 #define RADEON_PLL_FLAG_WRITE 0x00 1621 #define RADEON_PLL_FLAG_MASK_BYTE 0x40 1622 #define RADEON_PLL_FLAG_WAIT 0x80 1623 1624 #define RADEON_PLL_WAIT_150MKS 1 1625 #define RADEON_PLL_WAIT_5MS 2 1626 #define RADEON_PLL_WAIT_MC_BUSY_MASK 3 1627 #define RADEON_PLL_WAIT_DLL_READY_MASK 4 1628 #define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 1629 1630 static uint16_t 1631 RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) 1632 { 1633 RADEONInfoPtr info = RADEONPTR (pScrn); 1634 uint8_t revision = RADEON_BIOS8(offset - 1); 1635 1636 if (revision > 0x10) { 1637 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1638 "Bad revision %d for BIOS table\n", revision); 1639 return 0; 1640 } 1641 1642 if (offset < 0x60) { 1643 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1644 "Bad offset 0x%x for BIOS Table\n", offset); 1645 return 0; 1646 } 1647 1648 return offset; 1649 } 1650 1651 Bool 1652 RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) 1653 { 1654 RADEONInfoPtr info = RADEONPTR (pScrn); 1655 uint8_t val; 1656 1657 if (!info->VBIOS) { 1658 return FALSE; 1659 } else { 1660 if (info->IsAtomBios) { 1661 return FALSE; 1662 } else { 1663 info->BiosTable.revision = RADEON_BIOS8(info->ROMHeaderStart + 4); 1664 info->BiosTable.rr1_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x0c); 1665 if (info->BiosTable.rr1_offset) { 1666 info->BiosTable.rr1_offset = 1667 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr1_offset); 1668 } 1669 if (info->BiosTable.revision > 0x09) 1670 return TRUE; 1671 info->BiosTable.rr2_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x4e); 1672 if (info->BiosTable.rr2_offset) { 1673 info->BiosTable.rr2_offset = 1674 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr2_offset); 1675 } 1676 info->BiosTable.dyn_clk_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x52); 1677 if (info->BiosTable.dyn_clk_offset) { 1678 info->BiosTable.dyn_clk_offset = 1679 RADEONValidateBIOSOffset(pScrn, info->BiosTable.dyn_clk_offset); 1680 } 1681 info->BiosTable.pll_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x46); 1682 if (info->BiosTable.pll_offset) { 1683 info->BiosTable.pll_offset = 1684 RADEONValidateBIOSOffset(pScrn, info->BiosTable.pll_offset); 1685 } 1686 info->BiosTable.mem_config_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x48); 1687 if (info->BiosTable.mem_config_offset) { 1688 info->BiosTable.mem_config_offset = 1689 RADEONValidateBIOSOffset(pScrn, info->BiosTable.mem_config_offset); 1690 } 1691 if (info->BiosTable.mem_config_offset) { 1692 info->BiosTable.mem_reset_offset = info->BiosTable.mem_config_offset; 1693 if (info->BiosTable.mem_reset_offset) { 1694 while (RADEON_BIOS8(info->BiosTable.mem_reset_offset)) 1695 info->BiosTable.mem_reset_offset++; 1696 info->BiosTable.mem_reset_offset++; 1697 info->BiosTable.mem_reset_offset += 2; 1698 } 1699 } 1700 if (info->BiosTable.mem_config_offset) { 1701 info->BiosTable.short_mem_offset = info->BiosTable.mem_config_offset; 1702 if ((info->BiosTable.short_mem_offset != 0) && 1703 (RADEON_BIOS8(info->BiosTable.short_mem_offset - 2) <= 64)) 1704 info->BiosTable.short_mem_offset += 1705 RADEON_BIOS8(info->BiosTable.short_mem_offset - 3); 1706 } 1707 if (info->BiosTable.rr2_offset) { 1708 info->BiosTable.rr3_offset = info->BiosTable.rr2_offset; 1709 if (info->BiosTable.rr3_offset) { 1710 while ((val = RADEON_BIOS8(info->BiosTable.rr3_offset + 1)) != 0) { 1711 if (val & 0x40) 1712 info->BiosTable.rr3_offset += 10; 1713 else if (val & 0x80) 1714 info->BiosTable.rr3_offset += 4; 1715 else 1716 info->BiosTable.rr3_offset += 6; 1717 } 1718 info->BiosTable.rr3_offset += 2; 1719 } 1720 } 1721 1722 if (info->BiosTable.rr3_offset) { 1723 info->BiosTable.rr4_offset = info->BiosTable.rr3_offset; 1724 if (info->BiosTable.rr4_offset) { 1725 while ((val = RADEON_BIOS8(info->BiosTable.rr4_offset + 1)) != 0) { 1726 if (val & 0x40) 1727 info->BiosTable.rr4_offset += 10; 1728 else if (val & 0x80) 1729 info->BiosTable.rr4_offset += 4; 1730 else 1731 info->BiosTable.rr4_offset += 6; 1732 } 1733 info->BiosTable.rr4_offset += 2; 1734 } 1735 } 1736 1737 if (info->BiosTable.rr3_offset + 1 == info->BiosTable.pll_offset) { 1738 info->BiosTable.rr3_offset = 0; 1739 info->BiosTable.rr4_offset = 0; 1740 } 1741 1742 return TRUE; 1743 1744 } 1745 } 1746 } 1747 1748 static void 1749 RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1750 { 1751 RADEONInfoPtr info = RADEONPTR (pScrn); 1752 unsigned char *RADEONMMIO = info->MMIO; 1753 uint16_t offset = table_offset; 1754 uint16_t value, flag, index, count; 1755 uint32_t andmask, ormask, val, channel_complete_mask; 1756 uint8_t command; 1757 1758 if (offset == 0) 1759 return; 1760 1761 while ((value = RADEON_BIOS16(offset)) != 0) { 1762 flag = value & RADEON_TABLE_ENTRY_FLAG_MASK; 1763 index = value & RADEON_TABLE_ENTRY_INDEX_MASK; 1764 command = value & RADEON_TABLE_ENTRY_COMMAND_MASK; 1765 1766 offset += 2; 1767 1768 switch (flag) { 1769 case RADEON_TABLE_FLAG_WRITE_INDEXED: 1770 val = RADEON_BIOS32(offset); 1771 ErrorF("WRITE INDEXED: 0x%x 0x%x\n", 1772 index, (unsigned)val); 1773 OUTREG(RADEON_MM_INDEX, index); 1774 OUTREG(RADEON_MM_DATA, val); 1775 offset += 4; 1776 break; 1777 1778 case RADEON_TABLE_FLAG_WRITE_DIRECT: 1779 val = RADEON_BIOS32(offset); 1780 ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val); 1781 OUTREG(index, val); 1782 offset += 4; 1783 break; 1784 1785 case RADEON_TABLE_FLAG_MASK_INDEXED: 1786 andmask = RADEON_BIOS32(offset); 1787 offset += 4; 1788 ormask = RADEON_BIOS32(offset); 1789 offset += 4; 1790 ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n", 1791 index, (unsigned)andmask, (unsigned)ormask); 1792 OUTREG(RADEON_MM_INDEX, index); 1793 val = INREG(RADEON_MM_DATA); 1794 val = (val & andmask) | ormask; 1795 OUTREG(RADEON_MM_DATA, val); 1796 break; 1797 1798 case RADEON_TABLE_FLAG_MASK_DIRECT: 1799 andmask = RADEON_BIOS32(offset); 1800 offset += 4; 1801 ormask = RADEON_BIOS32(offset); 1802 offset += 4; 1803 ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", 1804 index, (unsigned)andmask, (unsigned)ormask); 1805 val = INREG(index); 1806 val = (val & andmask) | ormask; 1807 OUTREG(index, val); 1808 break; 1809 1810 case RADEON_TABLE_FLAG_DELAY: 1811 count = RADEON_BIOS16(offset); 1812 ErrorF("delay: %d\n", count); 1813 usleep(count); 1814 offset += 2; 1815 break; 1816 1817 case RADEON_TABLE_FLAG_SCOMMAND: 1818 ErrorF("SCOMMAND 0x%x\n", command); 1819 switch (command) { 1820 case RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK: 1821 count = RADEON_BIOS16(offset); 1822 ErrorF("SCOMMAND_WAIT_MC_BUSY_MASK %d\n", count); 1823 while (count--) { 1824 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1825 RADEON_MC_BUSY)) 1826 break; 1827 } 1828 break; 1829 1830 case RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE: 1831 count = RADEON_BIOS16(offset); 1832 ErrorF("SCOMMAND_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1833 /* may need to take into account how many memory channels 1834 * each card has 1835 */ 1836 if (IS_R300_VARIANT) 1837 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1838 else 1839 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1840 while (count--) { 1841 /* XXX: may need indexed access */ 1842 if ((INREG(RADEON_MEM_STR_CNTL) & 1843 channel_complete_mask) == 1844 channel_complete_mask) 1845 break; 1846 } 1847 break; 1848 1849 } 1850 offset += 2; 1851 break; 1852 } 1853 } 1854 } 1855 1856 static void 1857 RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1858 { 1859 RADEONInfoPtr info = RADEONPTR (pScrn); 1860 unsigned char *RADEONMMIO = info->MMIO; 1861 uint16_t offset = table_offset; 1862 uint16_t count; 1863 uint32_t ormask, val, channel_complete_mask; 1864 uint8_t index; 1865 1866 if (offset == 0) 1867 return; 1868 1869 while ((index = RADEON_BIOS8(offset)) != 0xff) { 1870 offset++; 1871 if (index == 0x0f) { 1872 count = 20000; 1873 ErrorF("MEM_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1874 /* may need to take into account how many memory channels 1875 * each card has 1876 */ 1877 if (IS_R300_VARIANT) 1878 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1879 else 1880 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1881 while (count--) { 1882 /* XXX: may need indexed access */ 1883 if ((INREG(RADEON_MEM_STR_CNTL) & 1884 channel_complete_mask) == 1885 channel_complete_mask) 1886 break; 1887 } 1888 } else { 1889 ormask = RADEON_BIOS16(offset); 1890 offset += 2; 1891 1892 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1893 RADEON_SDRAM_MODE_MASK, (unsigned)ormask); 1894 1895 /* can this use direct access? */ 1896 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1897 val = INREG(RADEON_MM_DATA); 1898 val = (val & RADEON_SDRAM_MODE_MASK) | ormask; 1899 OUTREG(RADEON_MM_DATA, val); 1900 1901 ormask = (uint32_t)index << 24; 1902 1903 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1904 RADEON_B3MEM_RESET_MASK, (unsigned)ormask); 1905 1906 /* can this use direct access? */ 1907 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1908 val = INREG(RADEON_MM_DATA); 1909 val = (val & RADEON_B3MEM_RESET_MASK) | ormask; 1910 OUTREG(RADEON_MM_DATA, val); 1911 } 1912 } 1913 } 1914 1915 static void 1916 RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1917 { 1918 RADEONInfoPtr info = RADEONPTR (pScrn); 1919 uint16_t offset = table_offset; 1920 uint8_t index, shift; 1921 uint32_t andmask, ormask, val, clk_pwrmgt_cntl; 1922 uint16_t count; 1923 1924 if (offset == 0) 1925 return; 1926 1927 while ((index = RADEON_BIOS8(offset)) != 0) { 1928 offset++; 1929 1930 switch (index & RADEON_PLL_FLAG_MASK) { 1931 case RADEON_PLL_FLAG_WAIT: 1932 switch (index & RADEON_PLL_INDEX_MASK) { 1933 case RADEON_PLL_WAIT_150MKS: 1934 ErrorF("delay: 150 us\n"); 1935 usleep(150); 1936 break; 1937 case RADEON_PLL_WAIT_5MS: 1938 ErrorF("delay: 5 ms\n"); 1939 usleep(5000); 1940 break; 1941 1942 case RADEON_PLL_WAIT_MC_BUSY_MASK: 1943 count = 1000; 1944 ErrorF("PLL_WAIT_MC_BUSY_MASK %d\n", count); 1945 while (count--) { 1946 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1947 RADEON_MC_BUSY)) 1948 break; 1949 } 1950 break; 1951 1952 case RADEON_PLL_WAIT_DLL_READY_MASK: 1953 count = 1000; 1954 ErrorF("PLL_WAIT_DLL_READY_MASK %d\n", count); 1955 while (count--) { 1956 if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1957 RADEON_DLL_READY) 1958 break; 1959 } 1960 break; 1961 1962 case RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24: 1963 ErrorF("PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24\n"); 1964 clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 1965 if (clk_pwrmgt_cntl & RADEON_CG_NO1_DEBUG_0) { 1966 val = INPLL(pScrn, RADEON_MCLK_CNTL); 1967 /* is this right? */ 1968 val = (val & 0xFFFF0000) | 0x1111; /* seems like we should clear these... */ 1969 OUTPLL(pScrn, RADEON_MCLK_CNTL, val); 1970 usleep(10000); 1971 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, 1972 clk_pwrmgt_cntl & ~RADEON_CG_NO1_DEBUG_0); 1973 usleep(10000); 1974 } 1975 break; 1976 } 1977 break; 1978 1979 case RADEON_PLL_FLAG_MASK_BYTE: 1980 shift = RADEON_BIOS8(offset) * 8; 1981 offset++; 1982 1983 andmask = 1984 (((uint32_t)RADEON_BIOS8(offset)) << shift) | 1985 ~((uint32_t)0xff << shift); 1986 offset++; 1987 1988 ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; 1989 offset++; 1990 1991 ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", 1992 index, shift, (unsigned)andmask, (unsigned)ormask); 1993 val = INPLL(pScrn, index); 1994 val = (val & andmask) | ormask; 1995 OUTPLL(pScrn, index, val); 1996 break; 1997 1998 case RADEON_PLL_FLAG_WRITE: 1999 val = RADEON_BIOS32(offset); 2000 ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val); 2001 OUTPLL(pScrn, index, val); 2002 offset += 4; 2003 break; 2004 } 2005 } 2006 } 2007 2008 Bool 2009 RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn) 2010 { 2011 RADEONInfoPtr info = RADEONPTR (pScrn); 2012 2013 if (!info->VBIOS) { 2014 return FALSE; 2015 } else { 2016 if (info->IsAtomBios) { 2017 return FALSE; 2018 } else { 2019 if (info->BiosTable.rr1_offset) { 2020 ErrorF("rr1 restore, 0x%x\n", info->BiosTable.rr1_offset); 2021 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr1_offset); 2022 } 2023 if (info->BiosTable.revision < 0x09) { 2024 if (info->BiosTable.pll_offset) { 2025 ErrorF("pll restore, 0x%x\n", info->BiosTable.pll_offset); 2026 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.pll_offset); 2027 } 2028 if (info->BiosTable.rr2_offset) { 2029 ErrorF("rr2 restore, 0x%x\n", info->BiosTable.rr2_offset); 2030 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr2_offset); 2031 } 2032 if (info->BiosTable.rr4_offset) { 2033 ErrorF("rr4 restore, 0x%x\n", info->BiosTable.rr4_offset); 2034 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr4_offset); 2035 } 2036 if (info->BiosTable.mem_reset_offset) { 2037 ErrorF("mem reset restore, 0x%x\n", info->BiosTable.mem_reset_offset); 2038 RADEONRestoreBIOSMemBlock(pScrn, info->BiosTable.mem_reset_offset); 2039 } 2040 if (info->BiosTable.rr3_offset) { 2041 ErrorF("rr3 restore, 0x%x\n", info->BiosTable.rr3_offset); 2042 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr3_offset); 2043 } 2044 if (info->BiosTable.dyn_clk_offset) { 2045 ErrorF("dyn_clk restore, 0x%x\n", info->BiosTable.dyn_clk_offset); 2046 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.dyn_clk_offset); 2047 } 2048 } 2049 } 2050 } 2051 return TRUE; 2052 } 2053
Indexes created Mon Jul 20 00:27:07 UTC 2026