1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ 2 /* 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2007 Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin (at) valinux.com> 29 * Gareth Hughes <gareth (at) valinux.com> 30 */ 31 32 #include "drmP.h" 33 #include "drm.h" 34 #include "radeon_drm.h" 35 #include "radeon_drv.h" 36 #include "r300_reg.h" 37 38 #if defined(__NetBSD__) && defined(_KERNEL_OPT) 39 #include "agp.h" 40 #endif 41 42 #define RADEON_FIFO_DEBUG 0 43 44 static int radeon_do_cleanup_cp(struct drm_device * dev); 45 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); 46 47 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) 48 { 49 u32 ret; 50 51 if (addr < 0x10000) 52 ret = DRM_READ32( dev_priv->mmio, addr ); 53 else { 54 DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, addr ); 55 ret = DRM_READ32( dev_priv->mmio, RADEON_MM_DATA ); 56 } 57 58 return ret; 59 } 60 61 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 62 { 63 u32 ret; 64 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 65 ret = RADEON_READ(R520_MC_IND_DATA); 66 RADEON_WRITE(R520_MC_IND_INDEX, 0); 67 return ret; 68 } 69 70 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 71 { 72 u32 ret; 73 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 74 ret = RADEON_READ(RS480_NB_MC_DATA); 75 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); 76 return ret; 77 } 78 79 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 80 { 81 u32 ret; 82 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 83 ret = RADEON_READ(RS690_MC_DATA); 84 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); 85 return ret; 86 } 87 88 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 89 { 90 u32 ret; 91 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 92 RS600_MC_IND_CITF_ARB0)); 93 ret = RADEON_READ(RS600_MC_DATA); 94 return ret; 95 } 96 97 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 98 { 99 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 100 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 101 return RS690_READ_MCIND(dev_priv, addr); 102 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 103 return RS600_READ_MCIND(dev_priv, addr); 104 else 105 return RS480_READ_MCIND(dev_priv, addr); 106 } 107 108 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 109 { 110 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 111 return RADEON_READ(R700_MC_VM_FB_LOCATION); 112 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 113 return RADEON_READ(R600_MC_VM_FB_LOCATION); 114 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 115 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 116 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 117 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 118 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 119 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 120 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); 121 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 122 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 123 else 124 return RADEON_READ(RADEON_MC_FB_LOCATION); 125 } 126 127 void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 128 { 129 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 130 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc); 131 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 132 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc); 133 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 134 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 135 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 136 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 137 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 138 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 139 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc); 140 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 141 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 142 else 143 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 144 } 145 146 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 147 { 148 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */ 149 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 150 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 151 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 152 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 153 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 154 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 155 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 156 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 157 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 158 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 159 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 160 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 161 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc); 162 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 163 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 164 else 165 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 166 } 167 168 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 169 { 170 u32 agp_base_hi = upper_32_bits(agp_base); 171 u32 agp_base_lo = agp_base & 0xffffffff; 172 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff; 173 174 // R6xx/R7xx must be aligned to a 4MB boundry 175 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 176 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); /* FIX ME */ 177 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 178 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base); /* FIX ME */ 179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 180 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 181 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 182 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 183 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 184 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 185 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 186 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 187 RS690_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo); 188 RS690_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi); 189 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 190 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 191 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 192 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 193 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 194 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 195 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); 196 } else { 197 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 198 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 199 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); 200 } 201 } 202 203 static int RADEON_READ_PLL(struct drm_device * dev, int addr) 204 { 205 drm_radeon_private_t *dev_priv = dev->dev_private; 206 207 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 208 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 209 } 210 211 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 212 { 213 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 214 return RADEON_READ(RADEON_PCIE_DATA); 215 } 216 217 #if RADEON_FIFO_DEBUG 218 static void radeon_status(drm_radeon_private_t * dev_priv) 219 { 220 printk("%s:\n", __FUNCTION__); 221 printk("RBBM_STATUS = 0x%08x\n", 222 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 223 printk("CP_RB_RTPR = 0x%08x\n", 224 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 225 printk("CP_RB_WTPR = 0x%08x\n", 226 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 227 printk("AIC_CNTL = 0x%08x\n", 228 (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 229 printk("AIC_STAT = 0x%08x\n", 230 (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 231 printk("AIC_PT_BASE = 0x%08x\n", 232 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 233 printk("TLB_ADDR = 0x%08x\n", 234 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 235 printk("TLB_DATA = 0x%08x\n", 236 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 237 } 238 #endif 239 240 /* ================================================================ 241 * Engine, FIFO control 242 */ 243 244 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 245 { 246 u32 tmp; 247 int i; 248 249 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 250 251 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { 252 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 253 tmp |= RADEON_RB3D_DC_FLUSH_ALL; 254 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 255 256 for (i = 0; i < dev_priv->usec_timeout; i++) { 257 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 258 & RADEON_RB3D_DC_BUSY)) { 259 return 0; 260 } 261 DRM_UDELAY(1); 262 } 263 } else { 264 /* don't flush or purge cache here or lockup */ 265 return 0; 266 } 267 268 #if RADEON_FIFO_DEBUG 269 DRM_ERROR("failed!\n"); 270 radeon_status(dev_priv); 271 #endif 272 return -EBUSY; 273 } 274 275 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 276 { 277 int i; 278 279 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 280 281 for (i = 0; i < dev_priv->usec_timeout; i++) { 282 int slots = (RADEON_READ(RADEON_RBBM_STATUS) 283 & RADEON_RBBM_FIFOCNT_MASK); 284 if (slots >= entries) 285 return 0; 286 DRM_UDELAY(1); 287 } 288 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 289 RADEON_READ(RADEON_RBBM_STATUS), 290 RADEON_READ(R300_VAP_CNTL_STATUS)); 291 292 #if RADEON_FIFO_DEBUG 293 DRM_ERROR("failed!\n"); 294 radeon_status(dev_priv); 295 #endif 296 return -EBUSY; 297 } 298 299 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 300 { 301 int i, ret; 302 303 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 304 305 ret = radeon_do_wait_for_fifo(dev_priv, 64); 306 if (ret) 307 return ret; 308 309 for (i = 0; i < dev_priv->usec_timeout; i++) { 310 if (!(RADEON_READ(RADEON_RBBM_STATUS) 311 & RADEON_RBBM_ACTIVE)) { 312 radeon_do_pixcache_flush(dev_priv); 313 return 0; 314 } 315 DRM_UDELAY(1); 316 } 317 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 318 RADEON_READ(RADEON_RBBM_STATUS), 319 RADEON_READ(R300_VAP_CNTL_STATUS)); 320 321 #if RADEON_FIFO_DEBUG 322 DRM_ERROR("failed!\n"); 323 radeon_status(dev_priv); 324 #endif 325 return -EBUSY; 326 } 327 328 static void radeon_init_pipes(drm_radeon_private_t * dev_priv) 329 { 330 uint32_t gb_tile_config, gb_pipe_sel = 0; 331 332 /* RS4xx/RS6xx/R4xx/R5xx */ 333 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 334 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 335 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 336 } else { 337 /* R3xx */ 338 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 339 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 340 dev_priv->num_gb_pipes = 2; 341 } else { 342 /* R3Vxx */ 343 dev_priv->num_gb_pipes = 1; 344 } 345 } 346 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); 347 348 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); 349 350 switch(dev_priv->num_gb_pipes) { 351 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 352 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 353 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 354 default: 355 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 356 } 357 358 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 359 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); 360 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); 361 } 362 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); 363 radeon_do_wait_for_idle(dev_priv); 364 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); 365 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | 366 R300_DC_AUTOFLUSH_ENABLE | 367 R300_DC_DC_DISABLE_IGNORE_PE)); 368 369 370 } 371 372 /* ================================================================ 373 * CP control, initialization 374 */ 375 376 377 /* Load the microcode for the CP */ 378 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 379 { 380 const char *chip_name; 381 u32 (*cp)[2]; 382 int i, error; 383 size_t cp_size; 384 DRM_DEBUG("\n"); 385 386 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 387 case CHIP_R100: 388 case CHIP_RV100: 389 case CHIP_RV200: 390 case CHIP_RS100: 391 case CHIP_RS200: 392 chip_name = "R100"; 393 break; 394 case CHIP_R200: 395 case CHIP_RV250: 396 case CHIP_RV280: 397 case CHIP_RS300: 398 chip_name = "R200"; 399 break; 400 case CHIP_R300: 401 case CHIP_R350: 402 case CHIP_RV350: 403 case CHIP_RV380: 404 case CHIP_RS400: 405 case CHIP_RS480: 406 chip_name = "R300"; 407 break; 408 case CHIP_R420: 409 case CHIP_R423: 410 case CHIP_RV410: 411 chip_name = "R420"; 412 break; 413 case CHIP_RS690: 414 case CHIP_RS740: 415 chip_name = "RS690"; 416 break; 417 case CHIP_RS600: 418 chip_name = "RS600"; 419 break; 420 case CHIP_RV515: 421 case CHIP_R520: 422 case CHIP_RV530: 423 case CHIP_R580: 424 case CHIP_RV560: 425 case CHIP_RV570: 426 chip_name = "R520"; 427 break; 428 default: 429 return; 430 } 431 432 DRM_INFO("Loading %s Microcode\n", chip_name); 433 434 if ((error = radeon_load_a_microcode("%s_cp.bin", chip_name, (void **)&cp, &cp_size)) != 0) 435 return; 436 437 radeon_do_wait_for_idle(dev_priv); 438 439 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 440 441 for (i = 0; i != 256; i++) { 442 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, be32toh(cp[i][0])); 443 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, be32toh(cp[i][1])); 444 } 445 446 radeon_free_a_microcode(cp, cp_size); 447 } 448 449 450 451 452 /* Flush any pending commands to the CP. This should only be used just 453 * prior to a wait for idle, as it informs the engine that the command 454 * stream is ending. 455 */ 456 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 457 { 458 DRM_DEBUG("\n"); 459 #if 0 460 u32 tmp; 461 462 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 463 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 464 #endif 465 } 466 467 /* Wait for the CP to go idle. 468 */ 469 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 470 { 471 RING_LOCALS; 472 DRM_DEBUG("\n"); 473 474 BEGIN_RING(6); 475 476 RADEON_PURGE_CACHE(); 477 RADEON_PURGE_ZCACHE(); 478 RADEON_WAIT_UNTIL_IDLE(); 479 480 ADVANCE_RING(); 481 COMMIT_RING(); 482 483 return radeon_do_wait_for_idle(dev_priv); 484 } 485 486 /* Start the Command Processor. 487 */ 488 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 489 { 490 RING_LOCALS; 491 DRM_DEBUG("\n"); 492 493 radeon_do_wait_for_idle(dev_priv); 494 495 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 496 497 dev_priv->cp_running = 1; 498 499 BEGIN_RING(8); 500 /* isync can only be written through cp on r5xx write it here */ 501 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 502 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | 503 RADEON_ISYNC_ANY3D_IDLE2D | 504 RADEON_ISYNC_WAIT_IDLEGUI | 505 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 506 RADEON_PURGE_CACHE(); 507 RADEON_PURGE_ZCACHE(); 508 RADEON_WAIT_UNTIL_IDLE(); 509 ADVANCE_RING(); 510 COMMIT_RING(); 511 512 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; 513 } 514 515 /* Reset the Command Processor. This will not flush any pending 516 * commands, so you must wait for the CP command stream to complete 517 * before calling this routine. 518 */ 519 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 520 { 521 u32 cur_read_ptr; 522 DRM_DEBUG("\n"); 523 524 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 525 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 526 SET_RING_HEAD(dev_priv, cur_read_ptr); 527 dev_priv->ring.tail = cur_read_ptr; 528 } 529 530 /* Stop the Command Processor. This will not flush any pending 531 * commands, so you must flush the command stream and wait for the CP 532 * to go idle before calling this routine. 533 */ 534 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 535 { 536 DRM_DEBUG("\n"); 537 538 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 539 540 dev_priv->cp_running = 0; 541 } 542 543 /* Reset the engine. This will stop the CP if it is running. 544 */ 545 static int radeon_do_engine_reset(struct drm_device * dev) 546 { 547 drm_radeon_private_t *dev_priv = dev->dev_private; 548 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; 549 DRM_DEBUG("\n"); 550 551 radeon_do_pixcache_flush(dev_priv); 552 553 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 554 /* may need something similar for newer chips */ 555 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 556 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 557 558 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 559 RADEON_FORCEON_MCLKA | 560 RADEON_FORCEON_MCLKB | 561 RADEON_FORCEON_YCLKA | 562 RADEON_FORCEON_YCLKB | 563 RADEON_FORCEON_MC | 564 RADEON_FORCEON_AIC)); 565 } 566 567 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 568 569 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 570 RADEON_SOFT_RESET_CP | 571 RADEON_SOFT_RESET_HI | 572 RADEON_SOFT_RESET_SE | 573 RADEON_SOFT_RESET_RE | 574 RADEON_SOFT_RESET_PP | 575 RADEON_SOFT_RESET_E2 | 576 RADEON_SOFT_RESET_RB)); 577 RADEON_READ(RADEON_RBBM_SOFT_RESET); 578 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 579 ~(RADEON_SOFT_RESET_CP | 580 RADEON_SOFT_RESET_HI | 581 RADEON_SOFT_RESET_SE | 582 RADEON_SOFT_RESET_RE | 583 RADEON_SOFT_RESET_PP | 584 RADEON_SOFT_RESET_E2 | 585 RADEON_SOFT_RESET_RB))); 586 RADEON_READ(RADEON_RBBM_SOFT_RESET); 587 588 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 589 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 590 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 591 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 592 } 593 594 /* setup the raster pipes */ 595 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 596 radeon_init_pipes(dev_priv); 597 598 /* Reset the CP ring */ 599 radeon_do_cp_reset(dev_priv); 600 601 /* The CP is no longer running after an engine reset */ 602 dev_priv->cp_running = 0; 603 604 /* Reset any pending vertex, indirect buffers */ 605 radeon_freelist_reset(dev); 606 607 return 0; 608 } 609 610 static void radeon_cp_init_ring_buffer(struct drm_device * dev, 611 drm_radeon_private_t * dev_priv) 612 { 613 u32 ring_start, cur_read_ptr; 614 u32 tmp; 615 616 /* Initialize the memory controller. With new memory map, the fb location 617 * is not changed, it should have been properly initialized already. Part 618 * of the problem is that the code below is bogus, assuming the GART is 619 * always appended to the fb which is not necessarily the case 620 */ 621 if (!dev_priv->new_memmap) 622 radeon_write_fb_location(dev_priv, 623 ((dev_priv->gart_vm_start - 1) & 0xffff0000) 624 | (dev_priv->fb_location >> 16)); 625 626 #if __OS_HAS_AGP 627 if (dev_priv->flags & RADEON_IS_AGP) { 628 radeon_write_agp_base(dev_priv, dev->agp->base); 629 630 radeon_write_agp_location(dev_priv, 631 (((dev_priv->gart_vm_start - 1 + 632 dev_priv->gart_size) & 0xffff0000) | 633 (dev_priv->gart_vm_start >> 16))); 634 635 ring_start = (dev_priv->cp_ring->offset 636 - dev->agp->base 637 + dev_priv->gart_vm_start); 638 } else 639 #endif 640 ring_start = (dev_priv->cp_ring->offset 641 - (unsigned long)dev->sg->virtual 642 + dev_priv->gart_vm_start); 643 644 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 645 646 /* Set the write pointer delay */ 647 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 648 649 /* Initialize the ring buffer's read and write pointers */ 650 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 651 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 652 SET_RING_HEAD(dev_priv, cur_read_ptr); 653 dev_priv->ring.tail = cur_read_ptr; 654 655 #if __OS_HAS_AGP 656 if (dev_priv->flags & RADEON_IS_AGP) { 657 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 658 dev_priv->ring_rptr->offset 659 - dev->agp->base + dev_priv->gart_vm_start); 660 } else 661 #endif 662 { 663 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 664 dev_priv->ring_rptr->offset 665 - ((unsigned long) dev->sg->virtual) 666 + dev_priv->gart_vm_start); 667 } 668 669 /* Set ring buffer size */ 670 #ifdef __BIG_ENDIAN 671 RADEON_WRITE(RADEON_CP_RB_CNTL, 672 RADEON_BUF_SWAP_32BIT | 673 (dev_priv->ring.fetch_size_l2ow << 18) | 674 (dev_priv->ring.rptr_update_l2qw << 8) | 675 dev_priv->ring.size_l2qw); 676 #else 677 RADEON_WRITE(RADEON_CP_RB_CNTL, 678 (dev_priv->ring.fetch_size_l2ow << 18) | 679 (dev_priv->ring.rptr_update_l2qw << 8) | 680 dev_priv->ring.size_l2qw); 681 #endif 682 683 /* Initialize the scratch register pointer. This will cause 684 * the scratch register values to be written out to memory 685 * whenever they are updated. 686 * 687 * We simply put this behind the ring read pointer, this works 688 * with PCI GART as well as (whatever kind of) AGP GART 689 */ 690 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 691 + RADEON_SCRATCH_REG_OFFSET); 692 693 dev_priv->scratch = ((__volatile__ u32 *) 694 dev_priv->ring_rptr->handle + 695 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 696 697 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 698 699 /* Turn on bus mastering */ 700 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 701 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 702 /* rs600/rs690/rs740 */ 703 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 704 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 705 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || 706 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 707 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 708 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 709 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 710 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 711 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 712 } /* PCIE cards appears to not need this */ 713 714 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 715 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 716 717 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 718 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 719 dev_priv->sarea_priv->last_dispatch); 720 721 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 722 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); 723 724 radeon_do_wait_for_idle(dev_priv); 725 726 /* Sync everything up */ 727 RADEON_WRITE(RADEON_ISYNC_CNTL, 728 (RADEON_ISYNC_ANY2D_IDLE3D | 729 RADEON_ISYNC_ANY3D_IDLE2D | 730 RADEON_ISYNC_WAIT_IDLEGUI | 731 RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 732 733 } 734 735 static void radeon_test_writeback(drm_radeon_private_t * dev_priv) 736 { 737 u32 tmp; 738 739 /* Writeback doesn't seem to work everywhere, test it here and possibly 740 * enable it if it appears to work 741 */ 742 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); 743 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 744 745 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 746 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == 747 0xdeadbeef) 748 break; 749 DRM_UDELAY(1); 750 } 751 752 if (tmp < dev_priv->usec_timeout) { 753 dev_priv->writeback_works = 1; 754 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 755 } else { 756 dev_priv->writeback_works = 0; 757 DRM_INFO("writeback test failed\n"); 758 } 759 if (radeon_no_wb == 1) { 760 dev_priv->writeback_works = 0; 761 DRM_INFO("writeback forced off\n"); 762 } 763 764 if (!dev_priv->writeback_works) { 765 /* Disable writeback to avoid unnecessary bus master transfers */ 766 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE); 767 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); 768 } 769 } 770 771 /* Enable or disable IGP GART on the chip */ 772 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 773 { 774 u32 temp; 775 776 if (on) { 777 DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 778 dev_priv->gart_vm_start, 779 (long)dev_priv->gart_info.bus_addr, 780 dev_priv->gart_size); 781 782 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 783 784 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 785 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 786 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 787 RS690_BLOCK_GFX_D3_EN)); 788 else 789 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 790 791 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 792 RS480_VA_SIZE_32MB)); 793 794 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); 795 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | 796 RS480_TLB_ENABLE | 797 RS480_GTW_LAC_EN | 798 RS480_1LEVEL_GART)); 799 800 temp = dev_priv->gart_info.bus_addr & 0xfffff000; 801 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; 802 IGP_WRITE_MCIND(RS480_GART_BASE, temp); 803 804 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); 805 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 806 RS480_REQ_TYPE_SNOOP_DIS)); 807 808 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); 809 810 dev_priv->gart_size = 32*1024*1024; 811 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 812 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 813 814 radeon_write_agp_location(dev_priv, temp); 815 816 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); 817 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 818 RS480_VA_SIZE_32MB)); 819 820 do { 821 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 822 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 823 break; 824 DRM_UDELAY(1); 825 } while(1); 826 827 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 828 RS480_GART_CACHE_INVALIDATE); 829 830 do { 831 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 832 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 833 break; 834 DRM_UDELAY(1); 835 } while(1); 836 837 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); 838 } else { 839 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 840 } 841 } 842 843 /* Enable or disable IGP GART on the chip */ 844 static void rs600_set_igpgart(drm_radeon_private_t * dev_priv, int on) 845 { 846 u32 temp; 847 int i; 848 849 if (on) { 850 DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 851 dev_priv->gart_vm_start, 852 (long)dev_priv->gart_info.bus_addr, 853 dev_priv->gart_size); 854 855 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | 856 RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); 857 858 for (i = 0; i < 19; i++) 859 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i, 860 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | 861 RS600_SYSTEM_ACCESS_MODE_IN_SYS | 862 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH | 863 RS600_EFFECTIVE_L1_CACHE_SIZE(3) | 864 RS600_ENABLE_FRAGMENT_PROCESSING | 865 RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); 866 867 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE | 868 RS600_PAGE_TABLE_TYPE_FLAT)); 869 870 /* disable all other contexts */ 871 for (i = 1; i < 8; i++) 872 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); 873 874 /* setup the page table aperture */ 875 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 876 dev_priv->gart_info.bus_addr); 877 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, 878 dev_priv->gart_vm_start); 879 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, 880 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 881 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 882 883 /* setup the system aperture */ 884 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, 885 dev_priv->gart_vm_start); 886 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, 887 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 888 889 /* enable page tables */ 890 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 891 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT)); 892 893 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 894 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES)); 895 896 /* invalidate the cache */ 897 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 898 899 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 900 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 901 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 902 903 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; 904 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 905 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 906 907 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 908 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 909 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 910 911 } else { 912 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0); 913 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 914 temp &= ~RS600_ENABLE_PAGE_TABLES; 915 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp); 916 } 917 } 918 919 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 920 { 921 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 922 if (on) { 923 924 DRM_DEBUG("programming pcie %08X %08lX %08X\n", 925 dev_priv->gart_vm_start, 926 (long)dev_priv->gart_info.bus_addr, 927 dev_priv->gart_size); 928 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, 929 dev_priv->gart_vm_start); 930 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, 931 dev_priv->gart_info.bus_addr); 932 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, 933 dev_priv->gart_vm_start); 934 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, 935 dev_priv->gart_vm_start + 936 dev_priv->gart_size - 1); 937 938 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ 939 940 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 941 RADEON_PCIE_TX_GART_EN); 942 } else { 943 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 944 tmp & ~RADEON_PCIE_TX_GART_EN); 945 } 946 } 947 948 /* Enable or disable PCI GART on the chip */ 949 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 950 { 951 u32 tmp; 952 953 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 954 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || 955 (dev_priv->flags & RADEON_IS_IGPGART)) { 956 radeon_set_igpgart(dev_priv, on); 957 return; 958 } 959 960 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 961 rs600_set_igpgart(dev_priv, on); 962 return; 963 } 964 965 if (dev_priv->flags & RADEON_IS_PCIE) { 966 radeon_set_pciegart(dev_priv, on); 967 return; 968 } 969 970 tmp = RADEON_READ(RADEON_AIC_CNTL); 971 972 if (on) { 973 RADEON_WRITE(RADEON_AIC_CNTL, 974 tmp | RADEON_PCIGART_TRANSLATE_EN); 975 976 /* set PCI GART page-table base address 977 */ 978 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); 979 980 /* set address range for PCI address translate 981 */ 982 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 983 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 984 + dev_priv->gart_size - 1); 985 986 /* Turn off AGP aperture -- is this required for PCI GART? 987 */ 988 radeon_write_agp_location(dev_priv, 0xffffffc0); 989 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 990 } else { 991 RADEON_WRITE(RADEON_AIC_CNTL, 992 tmp & ~RADEON_PCIGART_TRANSLATE_EN); 993 } 994 } 995 996 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) 997 { 998 drm_radeon_private_t *dev_priv = dev->dev_private; 999 int ret; 1000 1001 DRM_DEBUG("\n"); 1002 1003 /* if we require new memory map but we don't have it fail */ 1004 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1005 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1006 radeon_do_cleanup_cp(dev); 1007 return -EINVAL; 1008 } 1009 1010 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) 1011 { 1012 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1013 dev_priv->flags &= ~RADEON_IS_AGP; 1014 } 1015 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1016 && !init->is_pci) 1017 { 1018 DRM_DEBUG("Restoring AGP flag\n"); 1019 dev_priv->flags |= RADEON_IS_AGP; 1020 } 1021 1022 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { 1023 DRM_ERROR("PCI GART memory not allocated!\n"); 1024 radeon_do_cleanup_cp(dev); 1025 return -EINVAL; 1026 } 1027 1028 dev_priv->usec_timeout = init->usec_timeout; 1029 if (dev_priv->usec_timeout < 1 || 1030 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1031 DRM_DEBUG("TIMEOUT problem!\n"); 1032 radeon_do_cleanup_cp(dev); 1033 return -EINVAL; 1034 } 1035 1036 /* Enable vblank on CRTC1 for older X servers 1037 */ 1038 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1039 1040 dev_priv->do_boxes = 0; 1041 dev_priv->cp_mode = init->cp_mode; 1042 1043 /* We don't support anything other than bus-mastering ring mode, 1044 * but the ring can be in either AGP or PCI space for the ring 1045 * read pointer. 1046 */ 1047 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1048 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1049 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1050 radeon_do_cleanup_cp(dev); 1051 return -EINVAL; 1052 } 1053 1054 switch (init->fb_bpp) { 1055 case 16: 1056 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1057 break; 1058 case 32: 1059 default: 1060 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1061 break; 1062 } 1063 dev_priv->front_offset = init->front_offset; 1064 dev_priv->front_pitch = init->front_pitch; 1065 dev_priv->back_offset = init->back_offset; 1066 dev_priv->back_pitch = init->back_pitch; 1067 1068 switch (init->depth_bpp) { 1069 case 16: 1070 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 1071 break; 1072 case 32: 1073 default: 1074 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 1075 break; 1076 } 1077 dev_priv->depth_offset = init->depth_offset; 1078 dev_priv->depth_pitch = init->depth_pitch; 1079 1080 /* Hardware state for depth clears. Remove this if/when we no 1081 * longer clear the depth buffer with a 3D rectangle. Hard-code 1082 * all values to prevent unwanted 3D state from slipping through 1083 * and screwing with the clear operation. 1084 */ 1085 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 1086 (dev_priv->color_fmt << 10) | 1087 (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0)); 1088 1089 dev_priv->depth_clear.rb3d_zstencilcntl = 1090 (dev_priv->depth_fmt | 1091 RADEON_Z_TEST_ALWAYS | 1092 RADEON_STENCIL_TEST_ALWAYS | 1093 RADEON_STENCIL_S_FAIL_REPLACE | 1094 RADEON_STENCIL_ZPASS_REPLACE | 1095 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 1096 1097 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 1098 RADEON_BFACE_SOLID | 1099 RADEON_FFACE_SOLID | 1100 RADEON_FLAT_SHADE_VTX_LAST | 1101 RADEON_DIFFUSE_SHADE_FLAT | 1102 RADEON_ALPHA_SHADE_FLAT | 1103 RADEON_SPECULAR_SHADE_FLAT | 1104 RADEON_FOG_SHADE_FLAT | 1105 RADEON_VTX_PIX_CENTER_OGL | 1106 RADEON_ROUND_MODE_TRUNC | 1107 RADEON_ROUND_PREC_8TH_PIX); 1108 1109 1110 dev_priv->ring_offset = init->ring_offset; 1111 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1112 dev_priv->buffers_offset = init->buffers_offset; 1113 dev_priv->gart_textures_offset = init->gart_textures_offset; 1114 1115 dev_priv->sarea = drm_getsarea(dev); 1116 if (!dev_priv->sarea) { 1117 DRM_ERROR("could not find sarea!\n"); 1118 radeon_do_cleanup_cp(dev); 1119 return -EINVAL; 1120 } 1121 1122 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1123 if (!dev_priv->cp_ring) { 1124 DRM_ERROR("could not find cp ring region!\n"); 1125 radeon_do_cleanup_cp(dev); 1126 return -EINVAL; 1127 } 1128 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1129 if (!dev_priv->ring_rptr) { 1130 DRM_ERROR("could not find ring read pointer!\n"); 1131 radeon_do_cleanup_cp(dev); 1132 return -EINVAL; 1133 } 1134 dev->agp_buffer_token = init->buffers_offset; 1135 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1136 if (!dev->agp_buffer_map) { 1137 DRM_ERROR("could not find dma buffer region!\n"); 1138 radeon_do_cleanup_cp(dev); 1139 return -EINVAL; 1140 } 1141 1142 if (init->gart_textures_offset) { 1143 dev_priv->gart_textures = 1144 drm_core_findmap(dev, init->gart_textures_offset); 1145 if (!dev_priv->gart_textures) { 1146 DRM_ERROR("could not find GART texture region!\n"); 1147 radeon_do_cleanup_cp(dev); 1148 return -EINVAL; 1149 } 1150 } 1151 1152 dev_priv->sarea_priv = 1153 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1154 init->sarea_priv_offset); 1155 1156 #if __OS_HAS_AGP 1157 if (dev_priv->flags & RADEON_IS_AGP) { 1158 drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1159 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1160 drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1161 if (!dev_priv->cp_ring->handle || 1162 !dev_priv->ring_rptr->handle || 1163 !dev->agp_buffer_map->handle) { 1164 DRM_ERROR("could not find ioremap agp regions!\n"); 1165 radeon_do_cleanup_cp(dev); 1166 return -EINVAL; 1167 } 1168 } else 1169 #endif 1170 { 1171 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1172 dev_priv->ring_rptr->handle = 1173 (void *)dev_priv->ring_rptr->offset; 1174 dev->agp_buffer_map->handle = 1175 (void *)dev->agp_buffer_map->offset; 1176 1177 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1178 dev_priv->cp_ring->handle); 1179 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1180 dev_priv->ring_rptr->handle); 1181 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1182 dev->agp_buffer_map->handle); 1183 } 1184 1185 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; 1186 dev_priv->fb_size = 1187 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) 1188 - dev_priv->fb_location; 1189 1190 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1191 ((dev_priv->front_offset 1192 + dev_priv->fb_location) >> 10)); 1193 1194 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1195 ((dev_priv->back_offset 1196 + dev_priv->fb_location) >> 10)); 1197 1198 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1199 ((dev_priv->depth_offset 1200 + dev_priv->fb_location) >> 10)); 1201 1202 dev_priv->gart_size = init->gart_size; 1203 1204 /* New let's set the memory map ... */ 1205 if (dev_priv->new_memmap) { 1206 u32 base = 0; 1207 1208 DRM_INFO("Setting GART location based on new memory map\n"); 1209 1210 /* If using AGP, try to locate the AGP aperture at the same 1211 * location in the card and on the bus, though we have to 1212 * align it down. 1213 */ 1214 #if __OS_HAS_AGP 1215 if (dev_priv->flags & RADEON_IS_AGP) { 1216 base = dev->agp->base; 1217 /* Check if valid */ 1218 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1219 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1220 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1221 dev->agp->base); 1222 base = 0; 1223 } 1224 } 1225 #endif 1226 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1227 if (base == 0) { 1228 base = dev_priv->fb_location + dev_priv->fb_size; 1229 if (base < dev_priv->fb_location || 1230 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 1231 base = dev_priv->fb_location 1232 - dev_priv->gart_size; 1233 } 1234 dev_priv->gart_vm_start = base & 0xffc00000u; 1235 if (dev_priv->gart_vm_start != base) 1236 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1237 base, dev_priv->gart_vm_start); 1238 } else { 1239 DRM_INFO("Setting GART location based on old memory map\n"); 1240 dev_priv->gart_vm_start = dev_priv->fb_location + 1241 RADEON_READ(RADEON_CONFIG_APER_SIZE); 1242 } 1243 1244 #if __OS_HAS_AGP 1245 if (dev_priv->flags & RADEON_IS_AGP) 1246 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1247 - dev->agp->base 1248 + dev_priv->gart_vm_start); 1249 else 1250 #endif 1251 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1252 - (unsigned long)dev->sg->virtual 1253 + dev_priv->gart_vm_start); 1254 1255 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1256 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", 1257 (unsigned int) dev_priv->gart_vm_start); 1258 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1259 dev_priv->gart_buffers_offset); 1260 1261 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1262 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 1263 + init->ring_size / sizeof(u32)); 1264 dev_priv->ring.size = init->ring_size; 1265 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 1266 1267 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 1268 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); 1269 1270 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 1271 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); 1272 1273 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 1274 1275 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1276 1277 #if __OS_HAS_AGP 1278 if (dev_priv->flags & RADEON_IS_AGP) { 1279 /* Turn off PCI GART */ 1280 radeon_set_pcigart(dev_priv, 0); 1281 } else 1282 #endif 1283 { 1284 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 1285 /* if we have an offset set from userspace */ 1286 if (dev_priv->pcigart_offset_set) { 1287 dev_priv->gart_info.bus_addr = 1288 dev_priv->pcigart_offset + dev_priv->fb_location; 1289 dev_priv->gart_info.mapping.offset = 1290 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 1291 dev_priv->gart_info.mapping.size = 1292 dev_priv->gart_info.table_size; 1293 1294 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 1295 if (!dev_priv->gart_info.mapping.handle) { 1296 DRM_ERROR("ioremap failed.\n"); 1297 radeon_do_cleanup_cp(dev); 1298 return -EINVAL; 1299 } 1300 1301 dev_priv->gart_info.addr = 1302 dev_priv->gart_info.mapping.handle; 1303 1304 if (dev_priv->flags & RADEON_IS_PCIE) 1305 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; 1306 else 1307 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1308 dev_priv->gart_info.gart_table_location = 1309 DRM_ATI_GART_FB; 1310 1311 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 1312 dev_priv->gart_info.addr, 1313 dev_priv->pcigart_offset); 1314 1315 } else { 1316 if (dev_priv->flags & RADEON_IS_IGPGART) 1317 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; 1318 else 1319 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1320 dev_priv->gart_info.gart_table_location = 1321 DRM_ATI_GART_MAIN; 1322 dev_priv->gart_info.addr = NULL; 1323 dev_priv->gart_info.bus_addr = 0; 1324 if (dev_priv->flags & RADEON_IS_PCIE) { 1325 DRM_ERROR 1326 ("Cannot use PCI Express without GART in FB memory\n"); 1327 radeon_do_cleanup_cp(dev); 1328 return -EINVAL; 1329 } 1330 } 1331 1332 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1333 ret = r600_page_table_init(dev); 1334 else 1335 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); 1336 1337 if (!ret) { 1338 DRM_ERROR("failed to init PCI GART!\n"); 1339 radeon_do_cleanup_cp(dev); 1340 return -ENOMEM; 1341 } 1342 1343 /* Turn on PCI GART */ 1344 radeon_set_pcigart(dev_priv, 1); 1345 } 1346 1347 /* Start with assuming that writeback doesn't work */ 1348 dev_priv->writeback_works = 0; 1349 1350 radeon_cp_load_microcode(dev_priv); 1351 radeon_cp_init_ring_buffer(dev, dev_priv); 1352 1353 dev_priv->last_buf = 0; 1354 1355 radeon_do_engine_reset(dev); 1356 radeon_test_writeback(dev_priv); 1357 1358 return 0; 1359 } 1360 1361 static int radeon_do_cleanup_cp(struct drm_device * dev) 1362 { 1363 drm_radeon_private_t *dev_priv = dev->dev_private; 1364 DRM_DEBUG("\n"); 1365 1366 /* Make sure interrupts are disabled here because the uninstall ioctl 1367 * may not have been called from userspace and after dev_private 1368 * is freed, it's too late. 1369 */ 1370 if (dev->irq_enabled) 1371 drm_irq_uninstall(dev); 1372 1373 #if __OS_HAS_AGP 1374 if (dev_priv->flags & RADEON_IS_AGP) { 1375 if (dev_priv->cp_ring != NULL) { 1376 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1377 dev_priv->cp_ring = NULL; 1378 } 1379 if (dev_priv->ring_rptr != NULL) { 1380 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1381 dev_priv->ring_rptr = NULL; 1382 } 1383 if (dev->agp_buffer_map != NULL) { 1384 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1385 dev->agp_buffer_map = NULL; 1386 } 1387 } else 1388 #endif 1389 { 1390 1391 if (dev_priv->gart_info.bus_addr) { 1392 /* Turn off PCI GART */ 1393 radeon_set_pcigart(dev_priv, 0); 1394 1395 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1396 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1397 else { 1398 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1399 DRM_ERROR("failed to cleanup PCI GART!\n"); 1400 } 1401 } 1402 1403 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1404 { 1405 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1406 dev_priv->gart_info.addr = 0; 1407 } 1408 } 1409 1410 if (dev_priv->mmio) 1411 drm_rmmap(dev, dev_priv->mmio); 1412 if (dev_priv->fb_map) 1413 drm_rmmap(dev, dev_priv->fb_map); 1414 1415 /* only clear to the start of flags */ 1416 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1417 1418 return 0; 1419 } 1420 1421 /* This code will reinit the Radeon CP hardware after a resume from disc. 1422 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1423 * here we make sure that all Radeon hardware initialisation is re-done without 1424 * affecting running applications. 1425 * 1426 * Charl P. Botha <http://cpbotha.net> 1427 */ 1428 static int radeon_do_resume_cp(struct drm_device * dev) 1429 { 1430 drm_radeon_private_t *dev_priv = dev->dev_private; 1431 1432 if (!dev_priv) { 1433 DRM_ERROR("Called with no initialization\n"); 1434 return -EINVAL; 1435 } 1436 1437 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1438 1439 #if __OS_HAS_AGP 1440 if (dev_priv->flags & RADEON_IS_AGP) { 1441 /* Turn off PCI GART */ 1442 radeon_set_pcigart(dev_priv, 0); 1443 } else 1444 #endif 1445 { 1446 /* Turn on PCI GART */ 1447 radeon_set_pcigart(dev_priv, 1); 1448 } 1449 1450 radeon_cp_load_microcode(dev_priv); 1451 radeon_cp_init_ring_buffer(dev, dev_priv); 1452 1453 radeon_do_engine_reset(dev); 1454 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 1455 1456 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1457 1458 return 0; 1459 } 1460 1461 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 1462 { 1463 drm_radeon_private_t *dev_priv = dev->dev_private; 1464 drm_radeon_init_t *init = data; 1465 1466 LOCK_TEST_WITH_RETURN(dev, file_priv); 1467 1468 if (init->func == RADEON_INIT_R300_CP) 1469 r300_init_reg_flags(dev); 1470 1471 switch (init->func) { 1472 case RADEON_INIT_CP: 1473 case RADEON_INIT_R200_CP: 1474 case RADEON_INIT_R300_CP: 1475 return radeon_do_init_cp(dev, init); 1476 case RADEON_INIT_R600_CP: 1477 return r600_do_init_cp(dev, init); 1478 case RADEON_CLEANUP_CP: 1479 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1480 return r600_do_cleanup_cp(dev); 1481 else 1482 return radeon_do_cleanup_cp(dev); 1483 } 1484 1485 return -EINVAL; 1486 } 1487 1488 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) 1489 { 1490 drm_radeon_private_t *dev_priv = dev->dev_private; 1491 DRM_DEBUG("\n"); 1492 1493 LOCK_TEST_WITH_RETURN(dev, file_priv); 1494 1495 if (dev_priv->cp_running) { 1496 DRM_DEBUG("while CP running\n"); 1497 return 0; 1498 } 1499 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1500 DRM_DEBUG("called with bogus CP mode (%d)\n", 1501 dev_priv->cp_mode); 1502 return 0; 1503 } 1504 1505 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1506 r600_do_cp_start(dev_priv); 1507 else 1508 radeon_do_cp_start(dev_priv); 1509 1510 return 0; 1511 } 1512 1513 /* Stop the CP. The engine must have been idled before calling this 1514 * routine. 1515 */ 1516 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) 1517 { 1518 drm_radeon_private_t *dev_priv = dev->dev_private; 1519 drm_radeon_cp_stop_t *stop = data; 1520 int ret; 1521 DRM_DEBUG("\n"); 1522 1523 LOCK_TEST_WITH_RETURN(dev, file_priv); 1524 1525 if (!dev_priv->cp_running) 1526 return 0; 1527 1528 /* Flush any pending CP commands. This ensures any outstanding 1529 * commands are exectuted by the engine before we turn it off. 1530 */ 1531 if (stop->flush) { 1532 radeon_do_cp_flush(dev_priv); 1533 } 1534 1535 /* If we fail to make the engine go idle, we return an error 1536 * code so that the DRM ioctl wrapper can try again. 1537 */ 1538 if (stop->idle) { 1539 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1540 ret = r600_do_cp_idle(dev_priv); 1541 else 1542 ret = radeon_do_cp_idle(dev_priv); 1543 if (ret) 1544 return ret; 1545 } 1546 1547 /* Finally, we can turn off the CP. If the engine isn't idle, 1548 * we will get some dropped triangles as they won't be fully 1549 * rendered before the CP is shut down. 1550 */ 1551 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1552 r600_do_cp_stop(dev_priv); 1553 else 1554 radeon_do_cp_stop(dev_priv); 1555 1556 /* Reset the engine */ 1557 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) 1558 radeon_do_engine_reset(dev); 1559 else 1560 r600_do_engine_reset(dev); 1561 1562 return 0; 1563 } 1564 1565 void radeon_do_release(struct drm_device * dev) 1566 { 1567 drm_radeon_private_t *dev_priv = dev->dev_private; 1568 int i, ret; 1569 1570 if (dev_priv) { 1571 if (dev_priv->cp_running) { 1572 /* Stop the cp */ 1573 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1574 while ((ret = r600_do_cp_idle(dev_priv)) != 0) { 1575 DRM_DEBUG("r600_do_cp_idle %d\n", ret); 1576 #ifdef __linux__ 1577 schedule(); 1578 #else 1579 #if defined(__FreeBSD__) && __FreeBSD_version > 500000 1580 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel", 1581 1); 1582 #elif defined(__NetBSD__) 1583 mtsleep(&ret, 0, "rdnrel", 1, 1584 &dev->dev_lock); 1585 #else 1586 tsleep(&ret, PZERO, "rdnrel", 1); 1587 #endif 1588 #endif 1589 } 1590 r600_do_cp_stop(dev_priv); 1591 r600_do_engine_reset(dev); 1592 } else { 1593 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1594 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1595 #ifdef __linux__ 1596 schedule(); 1597 #else 1598 #if defined(__FreeBSD__) && __FreeBSD_version > 500000 1599 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel", 1600 1); 1601 #elif defined(__NetBSD__) 1602 mtsleep(&ret, 0, "rdnrel", 1, 1603 &dev->dev_lock); 1604 #else 1605 tsleep(&ret, PZERO, "rdnrel", 1); 1606 #endif 1607 #endif 1608 } 1609 radeon_do_cp_stop(dev_priv); 1610 radeon_do_engine_reset(dev); 1611 } 1612 } 1613 1614 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { 1615 /* Disable *all* interrupts */ 1616 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1617 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1618 1619 if (dev_priv->mmio) { /* remove all surfaces */ 1620 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1621 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); 1622 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 1623 16 * i, 0); 1624 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 1625 16 * i, 0); 1626 } 1627 } 1628 } 1629 1630 /* Free memory heap structures */ 1631 radeon_mem_takedown(&(dev_priv->gart_heap)); 1632 radeon_mem_takedown(&(dev_priv->fb_heap)); 1633 1634 /* deallocate kernel resources */ 1635 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1636 r600_do_cleanup_cp(dev); 1637 else 1638 radeon_do_cleanup_cp(dev); 1639 } 1640 } 1641 1642 /* Just reset the CP ring. Called as part of an X Server engine reset. 1643 */ 1644 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 1645 { 1646 drm_radeon_private_t *dev_priv = dev->dev_private; 1647 DRM_DEBUG("\n"); 1648 1649 LOCK_TEST_WITH_RETURN(dev, file_priv); 1650 1651 if (!dev_priv) { 1652 DRM_DEBUG("called before init done\n"); 1653 return -EINVAL; 1654 } 1655 1656 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1657 r600_do_cp_reset(dev_priv); 1658 else 1659 radeon_do_cp_reset(dev_priv); 1660 1661 /* The CP is no longer running after an engine reset */ 1662 dev_priv->cp_running = 0; 1663 1664 return 0; 1665 } 1666 1667 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) 1668 { 1669 drm_radeon_private_t *dev_priv = dev->dev_private; 1670 DRM_DEBUG("\n"); 1671 1672 LOCK_TEST_WITH_RETURN(dev, file_priv); 1673 1674 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1675 return r600_do_cp_idle(dev_priv); 1676 else 1677 return radeon_do_cp_idle(dev_priv); 1678 } 1679 1680 /* Added by Charl P. Botha to call radeon_do_resume_cp(). 1681 */ 1682 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) 1683 { 1684 drm_radeon_private_t *dev_priv = dev->dev_private; 1685 1686 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1687 return r600_do_resume_cp(dev); 1688 else 1689 return radeon_do_resume_cp(dev); 1690 } 1691 1692 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 1693 { 1694 drm_radeon_private_t *dev_priv = dev->dev_private; 1695 DRM_DEBUG("\n"); 1696 1697 LOCK_TEST_WITH_RETURN(dev, file_priv); 1698 1699 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1700 return r600_do_engine_reset(dev); 1701 else 1702 return radeon_do_engine_reset(dev); 1703 } 1704 1705 /* ================================================================ 1706 * Fullscreen mode 1707 */ 1708 1709 /* KW: Deprecated to say the least: 1710 */ 1711 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) 1712 { 1713 return 0; 1714 } 1715 1716 /* ================================================================ 1717 * Freelist management 1718 */ 1719 1720 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1721 * bufs until freelist code is used. Note this hides a problem with 1722 * the scratch register * (used to keep track of last buffer 1723 * completed) being written to before * the last buffer has actually 1724 * completed rendering. 1725 * 1726 * KW: It's also a good way to find free buffers quickly. 1727 * 1728 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1729 * sleep. However, bugs in older versions of radeon_accel.c mean that 1730 * we essentially have to do this, else old clients will break. 1731 * 1732 * However, it does leave open a potential deadlock where all the 1733 * buffers are held by other clients, which can't release them because 1734 * they can't get the lock. 1735 */ 1736 1737 struct drm_buf *radeon_freelist_get(struct drm_device * dev) 1738 { 1739 struct drm_device_dma *dma = dev->dma; 1740 drm_radeon_private_t *dev_priv = dev->dev_private; 1741 drm_radeon_buf_priv_t *buf_priv; 1742 struct drm_buf *buf; 1743 int i, t; 1744 int start; 1745 1746 if (++dev_priv->last_buf >= dma->buf_count) 1747 dev_priv->last_buf = 0; 1748 1749 start = dev_priv->last_buf; 1750 1751 for (t = 0; t < dev_priv->usec_timeout; t++) { 1752 u32 done_age; 1753 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1754 done_age = GET_R600_SCRATCH(1); 1755 else 1756 done_age = GET_SCRATCH(1); 1757 DRM_DEBUG("done_age = %d\n", done_age); 1758 for (i = start; i < dma->buf_count; i++) { 1759 buf = dma->buflist[i]; 1760 buf_priv = buf->dev_private; 1761 if (buf->file_priv == NULL || (buf->pending && 1762 buf_priv->age <= 1763 done_age)) { 1764 dev_priv->stats.requested_bufs++; 1765 buf->pending = 0; 1766 return buf; 1767 } 1768 start = 0; 1769 } 1770 1771 if (t) { 1772 DRM_UDELAY(1); 1773 dev_priv->stats.freelist_loops++; 1774 } 1775 } 1776 1777 DRM_DEBUG("returning NULL!\n"); 1778 return NULL; 1779 } 1780 1781 #if 0 1782 struct drm_buf *radeon_freelist_get(struct drm_device * dev) 1783 { 1784 struct drm_device_dma *dma = dev->dma; 1785 drm_radeon_private_t *dev_priv = dev->dev_private; 1786 drm_radeon_buf_priv_t *buf_priv; 1787 struct drm_buf *buf; 1788 int i, t; 1789 int start; 1790 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 1791 1792 if (++dev_priv->last_buf >= dma->buf_count) 1793 dev_priv->last_buf = 0; 1794 1795 start = dev_priv->last_buf; 1796 dev_priv->stats.freelist_loops++; 1797 1798 for (t = 0; t < 2; t++) { 1799 for (i = start; i < dma->buf_count; i++) { 1800 buf = dma->buflist[i]; 1801 buf_priv = buf->dev_private; 1802 if (buf->file_priv == 0 || (buf->pending && 1803 buf_priv->age <= 1804 done_age)) { 1805 dev_priv->stats.requested_bufs++; 1806 buf->pending = 0; 1807 return buf; 1808 } 1809 } 1810 start = 0; 1811 } 1812 1813 return NULL; 1814 } 1815 #endif 1816 1817 void radeon_freelist_reset(struct drm_device * dev) 1818 { 1819 struct drm_device_dma *dma = dev->dma; 1820 drm_radeon_private_t *dev_priv = dev->dev_private; 1821 int i; 1822 1823 dev_priv->last_buf = 0; 1824 for (i = 0; i < dma->buf_count; i++) { 1825 struct drm_buf *buf = dma->buflist[i]; 1826 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1827 buf_priv->age = 0; 1828 } 1829 } 1830 1831 /* ================================================================ 1832 * CP command submission 1833 */ 1834 1835 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 1836 { 1837 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 1838 int i; 1839 u32 last_head; 1840 1841 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1842 last_head = R600_GET_RING_HEAD(dev_priv); 1843 else 1844 last_head = GET_RING_HEAD(dev_priv); 1845 1846 for (i = 0; i < dev_priv->usec_timeout; i++) { 1847 u32 head; 1848 1849 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1850 head = R600_GET_RING_HEAD(dev_priv); 1851 else 1852 head = GET_RING_HEAD(dev_priv); 1853 1854 ring->space = (head - ring->tail) * sizeof(u32); 1855 if (ring->space <= 0) 1856 ring->space += ring->size; 1857 if (ring->space > n) 1858 return 0; 1859 1860 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 1861 1862 if (head != last_head) 1863 i = 0; 1864 last_head = head; 1865 1866 DRM_UDELAY(1); 1867 } 1868 1869 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 1870 #if RADEON_FIFO_DEBUG 1871 radeon_status(dev_priv); 1872 DRM_ERROR("failed!\n"); 1873 #endif 1874 return -EBUSY; 1875 } 1876 1877 static int radeon_cp_get_buffers(struct drm_device *dev, 1878 struct drm_file *file_priv, 1879 struct drm_dma * d) 1880 { 1881 int i; 1882 struct drm_buf *buf; 1883 1884 for (i = d->granted_count; i < d->request_count; i++) { 1885 buf = radeon_freelist_get(dev); 1886 if (!buf) 1887 return -EBUSY; /* NOTE: broken client */ 1888 1889 buf->file_priv = file_priv; 1890 1891 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 1892 sizeof(buf->idx))) 1893 return -EFAULT; 1894 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 1895 sizeof(buf->total))) 1896 return -EFAULT; 1897 1898 d->granted_count++; 1899 } 1900 return 0; 1901 } 1902 1903 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1904 { 1905 struct drm_device_dma *dma = dev->dma; 1906 int ret = 0; 1907 struct drm_dma *d = data; 1908 1909 LOCK_TEST_WITH_RETURN(dev, file_priv); 1910 1911 /* Please don't send us buffers. 1912 */ 1913 if (d->send_count != 0) { 1914 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1915 DRM_CURRENTPID, d->send_count); 1916 return -EINVAL; 1917 } 1918 1919 /* We'll send you buffers. 1920 */ 1921 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1922 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1923 DRM_CURRENTPID, d->request_count, dma->buf_count); 1924 return -EINVAL; 1925 } 1926 1927 d->granted_count = 0; 1928 1929 if (d->request_count) { 1930 ret = radeon_cp_get_buffers(dev, file_priv, d); 1931 } 1932 1933 return ret; 1934 } 1935 1936 void radeon_commit_ring(drm_radeon_private_t *dev_priv) 1937 { 1938 int i; 1939 u32 *ring; 1940 int tail_aligned; 1941 1942 /* check if the ring is padded out to 16-dword alignment */ 1943 1944 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1); 1945 if (tail_aligned) { 1946 int num_p2 = RADEON_RING_ALIGN - tail_aligned; 1947 1948 ring = dev_priv->ring.start; 1949 /* pad with some CP_PACKET2 */ 1950 for (i = 0; i < num_p2; i++) 1951 ring[dev_priv->ring.tail + i] = CP_PACKET2(); 1952 1953 dev_priv->ring.tail += i; 1954 1955 dev_priv->ring.space -= num_p2 * sizeof(u32); 1956 } 1957 1958 dev_priv->ring.tail &= dev_priv->ring.tail_mask; 1959 1960 DRM_MEMORYBARRIER(); 1961 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1962 R600_GET_RING_HEAD( dev_priv ); 1963 else 1964 GET_RING_HEAD( dev_priv ); 1965 1966 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1967 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); 1968 /* read from PCI bus to ensure correct posting */ 1969 RADEON_READ(R600_CP_RB_RPTR); 1970 } else { 1971 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); 1972 /* read from PCI bus to ensure correct posting */ 1973 RADEON_READ(RADEON_CP_RB_RPTR); 1974 } 1975 } 1976 1977 int radeon_driver_load(struct drm_device *dev, unsigned long flags) 1978 { 1979 drm_radeon_private_t *dev_priv; 1980 int ret = 0; 1981 1982 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 1983 if (dev_priv == NULL) 1984 return -ENOMEM; 1985 1986 memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 1987 dev->dev_private = (void *)dev_priv; 1988 dev_priv->flags = flags; 1989 1990 DRM_SPININIT(&dev_priv->cs.cs_mutex, "cs_mtx"); 1991 1992 switch (flags & RADEON_FAMILY_MASK) { 1993 case CHIP_R100: 1994 case CHIP_RV200: 1995 case CHIP_R200: 1996 case CHIP_R300: 1997 case CHIP_R350: 1998 case CHIP_R420: 1999 case CHIP_R423: 2000 case CHIP_RV410: 2001 case CHIP_RV515: 2002 case CHIP_R520: 2003 case CHIP_RV570: 2004 case CHIP_R580: 2005 dev_priv->flags |= RADEON_HAS_HIERZ; 2006 break; 2007 default: 2008 /* all other chips have no hierarchical z buffer */ 2009 break; 2010 } 2011 2012 dev_priv->chip_family = flags & RADEON_FAMILY_MASK; 2013 #if !defined(__NetBSD__) || NAGP > 0 2014 if (drm_device_is_agp(dev)) 2015 dev_priv->flags |= RADEON_IS_AGP; 2016 else if (drm_device_is_pcie(dev)) 2017 dev_priv->flags |= RADEON_IS_PCIE; 2018 else 2019 #endif 2020 dev_priv->flags |= RADEON_IS_PCI; 2021 2022 ret = drm_vblank_init(dev, 2); 2023 if (ret) { 2024 radeon_driver_unload(dev); 2025 return ret; 2026 } 2027 2028 DRM_DEBUG("%s card detected\n", 2029 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 2030 return ret; 2031 } 2032 2033 /* Create mappings for registers and framebuffer so userland doesn't necessarily 2034 * have to find them. 2035 */ 2036 int radeon_driver_firstopen(struct drm_device *dev) 2037 { 2038 int ret; 2039 drm_radeon_private_t *dev_priv = dev->dev_private; 2040 2041 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 2042 2043 ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 2044 drm_get_resource_len(dev, 2), _DRM_REGISTERS, 2045 _DRM_READ_ONLY, &dev_priv->mmio); 2046 if (ret != 0) 2047 return ret; 2048 2049 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 2050 ret = drm_addmap(dev, dev_priv->fb_aper_offset, 2051 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 2052 _DRM_WRITE_COMBINING, &dev_priv->fb_map); 2053 if (ret != 0) 2054 return ret; 2055 2056 return 0; 2057 } 2058 2059 int radeon_driver_unload(struct drm_device *dev) 2060 { 2061 drm_radeon_private_t *dev_priv = dev->dev_private; 2062 2063 DRM_DEBUG("\n"); 2064 2065 DRM_SPINUNINIT(&dev_priv->cs.cs_mutex); 2066 2067 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2068 2069 dev->dev_private = NULL; 2070 return 0; 2071 } 2072
Indexes created Sat Sep 20 22:09:52 GMT 2025