1 /* $NetBSD: radeon_dp_auxch.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_dp_auxch.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $"); 29 30 #include <drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "nid.h" 33 34 #define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \ 35 AUX_SW_RX_HPD_DISCON | \ 36 AUX_SW_RX_PARTIAL_BYTE | \ 37 AUX_SW_NON_AUX_MODE | \ 38 AUX_SW_RX_SYNC_INVALID_L | \ 39 AUX_SW_RX_SYNC_INVALID_H | \ 40 AUX_SW_RX_INVALID_START | \ 41 AUX_SW_RX_RECV_NO_DET | \ 42 AUX_SW_RX_RECV_INVALID_H | \ 43 AUX_SW_RX_RECV_INVALID_V) 44 45 #define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f) 46 47 #define BARE_ADDRESS_SIZE 3 48 49 static const u32 aux_offset[] = 50 { 51 0x6200 - 0x6200, 52 0x6250 - 0x6200, 53 0x62a0 - 0x6200, 54 0x6300 - 0x6200, 55 0x6350 - 0x6200, 56 0x63a0 - 0x6200, 57 }; 58 59 ssize_t 60 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 61 { 62 struct radeon_i2c_chan *chan = 63 container_of(aux, struct radeon_i2c_chan, aux); 64 struct drm_device *dev = chan->dev; 65 struct radeon_device *rdev = dev->dev_private; 66 int ret = 0, i; 67 uint32_t tmp, ack = 0; 68 int instance = chan->rec.i2c_id & 0xf; 69 u8 byte; 70 u8 *buf = msg->buffer; 71 int retry_count = 0; 72 int bytes; 73 int msize; 74 bool is_write = false; 75 76 if (WARN_ON(msg->size > 16)) 77 return -E2BIG; 78 79 switch (msg->request & ~DP_AUX_I2C_MOT) { 80 case DP_AUX_NATIVE_WRITE: 81 case DP_AUX_I2C_WRITE: 82 is_write = true; 83 break; 84 case DP_AUX_NATIVE_READ: 85 case DP_AUX_I2C_READ: 86 break; 87 default: 88 return -EINVAL; 89 } 90 91 /* work out two sizes required */ 92 msize = 0; 93 bytes = BARE_ADDRESS_SIZE; 94 if (msg->size) { 95 msize = msg->size - 1; 96 bytes++; 97 if (is_write) 98 bytes += msg->size; 99 } 100 101 mutex_lock(&chan->mutex); 102 103 /* switch the pad to aux mode */ 104 tmp = RREG32(chan->rec.mask_clk_reg); 105 tmp |= (1 << 16); 106 WREG32(chan->rec.mask_clk_reg, tmp); 107 108 /* setup AUX control register with correct HPD pin */ 109 tmp = RREG32(AUX_CONTROL + aux_offset[instance]); 110 111 tmp &= AUX_HPD_SEL(0x7); 112 tmp |= AUX_HPD_SEL(chan->rec.hpd); 113 tmp |= AUX_EN | AUX_LS_READ_EN; 114 115 WREG32(AUX_CONTROL + aux_offset[instance], tmp); 116 117 /* atombios appears to write this twice lets copy it */ 118 WREG32(AUX_SW_CONTROL + aux_offset[instance], 119 AUX_SW_WR_BYTES(bytes)); 120 WREG32(AUX_SW_CONTROL + aux_offset[instance], 121 AUX_SW_WR_BYTES(bytes)); 122 123 /* write the data header into the registers */ 124 /* request, address, msg size */ 125 byte = (msg->request << 4) | ((msg->address >> 16) & 0xf); 126 WREG32(AUX_SW_DATA + aux_offset[instance], 127 AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); 128 129 byte = (msg->address >> 8) & 0xff; 130 WREG32(AUX_SW_DATA + aux_offset[instance], 131 AUX_SW_DATA_MASK(byte)); 132 133 byte = msg->address & 0xff; 134 WREG32(AUX_SW_DATA + aux_offset[instance], 135 AUX_SW_DATA_MASK(byte)); 136 137 byte = msize; 138 WREG32(AUX_SW_DATA + aux_offset[instance], 139 AUX_SW_DATA_MASK(byte)); 140 141 /* if we are writing - write the msg buffer */ 142 if (is_write) { 143 for (i = 0; i < msg->size; i++) { 144 WREG32(AUX_SW_DATA + aux_offset[instance], 145 AUX_SW_DATA_MASK(buf[i])); 146 } 147 } 148 149 /* clear the ACK */ 150 WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); 151 152 /* write the size and GO bits */ 153 WREG32(AUX_SW_CONTROL + aux_offset[instance], 154 AUX_SW_WR_BYTES(bytes) | AUX_SW_GO); 155 156 /* poll the status registers - TODO irq support */ 157 do { 158 tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); 159 if (tmp & AUX_SW_DONE) { 160 break; 161 } 162 usleep_range(100, 200); 163 } while (retry_count++ < 1000); 164 165 if (retry_count >= 1000) { 166 DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); 167 ret = -EIO; 168 goto done; 169 } 170 171 if (tmp & AUX_SW_RX_TIMEOUT) { 172 ret = -ETIMEDOUT; 173 goto done; 174 } 175 if (tmp & AUX_RX_ERROR_FLAGS) { 176 DRM_DEBUG_KMS_RATELIMITED("dp_aux_ch flags not zero: %08x\n", 177 tmp); 178 ret = -EIO; 179 goto done; 180 } 181 182 bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); 183 if (bytes) { 184 WREG32(AUX_SW_DATA + aux_offset[instance], 185 AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE); 186 187 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); 188 ack = (tmp >> 8) & 0xff; 189 190 for (i = 0; i < bytes - 1; i++) { 191 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); 192 if (buf) 193 buf[i] = (tmp >> 8) & 0xff; 194 } 195 if (buf) 196 ret = bytes - 1; 197 } 198 199 WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); 200 201 if (is_write) 202 ret = msg->size; 203 done: 204 mutex_unlock(&chan->mutex); 205 206 if (ret >= 0) 207 msg->reply = ack >> 4; 208 return ret; 209 } 210
Indexes created Mon Sep 29 03:10:08 GMT 2025