1 /* $NetBSD: radeon_combios.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 5 * Copyright 2007-8 Advanced Micro Devices, Inc. 6 * Copyright 2008 Red Hat Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_combios.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $"); 32 33 #include <linux/pci.h> 34 35 #include <drm/drm_device.h> 36 #include <drm/radeon_drm.h> 37 38 #include "radeon.h" 39 #include "atom.h" 40 41 #ifdef CONFIG_PPC_PMAC 42 /* not sure which of these are needed */ 43 #include <asm/machdep.h> 44 #include <asm/pmac_feature.h> 45 #include <asm/prom.h> 46 #endif /* CONFIG_PPC_PMAC */ 47 48 /* from radeon_legacy_encoder.c */ 49 extern void 50 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 51 uint32_t supported_device); 52 53 /* old legacy ATI BIOS routines */ 54 55 /* COMBIOS table offsets */ 56 enum radeon_combios_table_offset { 57 /* absolute offset tables */ 58 COMBIOS_ASIC_INIT_1_TABLE, 59 COMBIOS_BIOS_SUPPORT_TABLE, 60 COMBIOS_DAC_PROGRAMMING_TABLE, 61 COMBIOS_MAX_COLOR_DEPTH_TABLE, 62 COMBIOS_CRTC_INFO_TABLE, 63 COMBIOS_PLL_INFO_TABLE, 64 COMBIOS_TV_INFO_TABLE, 65 COMBIOS_DFP_INFO_TABLE, 66 COMBIOS_HW_CONFIG_INFO_TABLE, 67 COMBIOS_MULTIMEDIA_INFO_TABLE, 68 COMBIOS_TV_STD_PATCH_TABLE, 69 COMBIOS_LCD_INFO_TABLE, 70 COMBIOS_MOBILE_INFO_TABLE, 71 COMBIOS_PLL_INIT_TABLE, 72 COMBIOS_MEM_CONFIG_TABLE, 73 COMBIOS_SAVE_MASK_TABLE, 74 COMBIOS_HARDCODED_EDID_TABLE, 75 COMBIOS_ASIC_INIT_2_TABLE, 76 COMBIOS_CONNECTOR_INFO_TABLE, 77 COMBIOS_DYN_CLK_1_TABLE, 78 COMBIOS_RESERVED_MEM_TABLE, 79 COMBIOS_EXT_TMDS_INFO_TABLE, 80 COMBIOS_MEM_CLK_INFO_TABLE, 81 COMBIOS_EXT_DAC_INFO_TABLE, 82 COMBIOS_MISC_INFO_TABLE, 83 COMBIOS_CRT_INFO_TABLE, 84 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 85 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 86 COMBIOS_FAN_SPEED_INFO_TABLE, 87 COMBIOS_OVERDRIVE_INFO_TABLE, 88 COMBIOS_OEM_INFO_TABLE, 89 COMBIOS_DYN_CLK_2_TABLE, 90 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 91 COMBIOS_I2C_INFO_TABLE, 92 /* relative offset tables */ 93 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 94 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 95 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 96 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 97 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 98 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 99 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 100 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 101 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 102 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 103 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 104 }; 105 106 enum radeon_combios_ddc { 107 DDC_NONE_DETECTED, 108 DDC_MONID, 109 DDC_DVI, 110 DDC_VGA, 111 DDC_CRT2, 112 DDC_LCD, 113 DDC_GPIO, 114 }; 115 116 enum radeon_combios_connector { 117 CONNECTOR_NONE_LEGACY, 118 CONNECTOR_PROPRIETARY_LEGACY, 119 CONNECTOR_CRT_LEGACY, 120 CONNECTOR_DVI_I_LEGACY, 121 CONNECTOR_DVI_D_LEGACY, 122 CONNECTOR_CTV_LEGACY, 123 CONNECTOR_STV_LEGACY, 124 CONNECTOR_UNSUPPORTED_LEGACY 125 }; 126 127 static const int legacy_connector_convert[] = { 128 DRM_MODE_CONNECTOR_Unknown, 129 DRM_MODE_CONNECTOR_DVID, 130 DRM_MODE_CONNECTOR_VGA, 131 DRM_MODE_CONNECTOR_DVII, 132 DRM_MODE_CONNECTOR_DVID, 133 DRM_MODE_CONNECTOR_Composite, 134 DRM_MODE_CONNECTOR_SVIDEO, 135 DRM_MODE_CONNECTOR_Unknown, 136 }; 137 138 static uint16_t combios_get_table_offset(struct drm_device *dev, 139 enum radeon_combios_table_offset table) 140 { 141 struct radeon_device *rdev = dev->dev_private; 142 int rev, size; 143 uint16_t offset = 0, check_offset; 144 145 if (!rdev->bios) 146 return 0; 147 148 switch (table) { 149 /* absolute offset tables */ 150 case COMBIOS_ASIC_INIT_1_TABLE: 151 check_offset = 0xc; 152 break; 153 case COMBIOS_BIOS_SUPPORT_TABLE: 154 check_offset = 0x14; 155 break; 156 case COMBIOS_DAC_PROGRAMMING_TABLE: 157 check_offset = 0x2a; 158 break; 159 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 160 check_offset = 0x2c; 161 break; 162 case COMBIOS_CRTC_INFO_TABLE: 163 check_offset = 0x2e; 164 break; 165 case COMBIOS_PLL_INFO_TABLE: 166 check_offset = 0x30; 167 break; 168 case COMBIOS_TV_INFO_TABLE: 169 check_offset = 0x32; 170 break; 171 case COMBIOS_DFP_INFO_TABLE: 172 check_offset = 0x34; 173 break; 174 case COMBIOS_HW_CONFIG_INFO_TABLE: 175 check_offset = 0x36; 176 break; 177 case COMBIOS_MULTIMEDIA_INFO_TABLE: 178 check_offset = 0x38; 179 break; 180 case COMBIOS_TV_STD_PATCH_TABLE: 181 check_offset = 0x3e; 182 break; 183 case COMBIOS_LCD_INFO_TABLE: 184 check_offset = 0x40; 185 break; 186 case COMBIOS_MOBILE_INFO_TABLE: 187 check_offset = 0x42; 188 break; 189 case COMBIOS_PLL_INIT_TABLE: 190 check_offset = 0x46; 191 break; 192 case COMBIOS_MEM_CONFIG_TABLE: 193 check_offset = 0x48; 194 break; 195 case COMBIOS_SAVE_MASK_TABLE: 196 check_offset = 0x4a; 197 break; 198 case COMBIOS_HARDCODED_EDID_TABLE: 199 check_offset = 0x4c; 200 break; 201 case COMBIOS_ASIC_INIT_2_TABLE: 202 check_offset = 0x4e; 203 break; 204 case COMBIOS_CONNECTOR_INFO_TABLE: 205 check_offset = 0x50; 206 break; 207 case COMBIOS_DYN_CLK_1_TABLE: 208 check_offset = 0x52; 209 break; 210 case COMBIOS_RESERVED_MEM_TABLE: 211 check_offset = 0x54; 212 break; 213 case COMBIOS_EXT_TMDS_INFO_TABLE: 214 check_offset = 0x58; 215 break; 216 case COMBIOS_MEM_CLK_INFO_TABLE: 217 check_offset = 0x5a; 218 break; 219 case COMBIOS_EXT_DAC_INFO_TABLE: 220 check_offset = 0x5c; 221 break; 222 case COMBIOS_MISC_INFO_TABLE: 223 check_offset = 0x5e; 224 break; 225 case COMBIOS_CRT_INFO_TABLE: 226 check_offset = 0x60; 227 break; 228 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 229 check_offset = 0x62; 230 break; 231 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 232 check_offset = 0x64; 233 break; 234 case COMBIOS_FAN_SPEED_INFO_TABLE: 235 check_offset = 0x66; 236 break; 237 case COMBIOS_OVERDRIVE_INFO_TABLE: 238 check_offset = 0x68; 239 break; 240 case COMBIOS_OEM_INFO_TABLE: 241 check_offset = 0x6a; 242 break; 243 case COMBIOS_DYN_CLK_2_TABLE: 244 check_offset = 0x6c; 245 break; 246 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 247 check_offset = 0x6e; 248 break; 249 case COMBIOS_I2C_INFO_TABLE: 250 check_offset = 0x70; 251 break; 252 /* relative offset tables */ 253 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 254 check_offset = 255 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 256 if (check_offset) { 257 rev = RBIOS8(check_offset); 258 if (rev > 0) { 259 check_offset = RBIOS16(check_offset + 0x3); 260 if (check_offset) 261 offset = check_offset; 262 } 263 } 264 break; 265 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 266 check_offset = 267 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 268 if (check_offset) { 269 rev = RBIOS8(check_offset); 270 if (rev > 0) { 271 check_offset = RBIOS16(check_offset + 0x5); 272 if (check_offset) 273 offset = check_offset; 274 } 275 } 276 break; 277 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 278 check_offset = 279 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 280 if (check_offset) { 281 rev = RBIOS8(check_offset); 282 if (rev > 0) { 283 check_offset = RBIOS16(check_offset + 0x7); 284 if (check_offset) 285 offset = check_offset; 286 } 287 } 288 break; 289 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 290 check_offset = 291 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 292 if (check_offset) { 293 rev = RBIOS8(check_offset); 294 if (rev == 2) { 295 check_offset = RBIOS16(check_offset + 0x9); 296 if (check_offset) 297 offset = check_offset; 298 } 299 } 300 break; 301 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 302 check_offset = 303 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 304 if (check_offset) { 305 while (RBIOS8(check_offset++)); 306 check_offset += 2; 307 if (check_offset) 308 offset = check_offset; 309 } 310 break; 311 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 312 check_offset = 313 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 314 if (check_offset) { 315 check_offset = RBIOS16(check_offset + 0x11); 316 if (check_offset) 317 offset = check_offset; 318 } 319 break; 320 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 321 check_offset = 322 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 323 if (check_offset) { 324 check_offset = RBIOS16(check_offset + 0x13); 325 if (check_offset) 326 offset = check_offset; 327 } 328 break; 329 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 330 check_offset = 331 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 332 if (check_offset) { 333 check_offset = RBIOS16(check_offset + 0x15); 334 if (check_offset) 335 offset = check_offset; 336 } 337 break; 338 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 339 check_offset = 340 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 341 if (check_offset) { 342 check_offset = RBIOS16(check_offset + 0x17); 343 if (check_offset) 344 offset = check_offset; 345 } 346 break; 347 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 348 check_offset = 349 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 350 if (check_offset) { 351 check_offset = RBIOS16(check_offset + 0x2); 352 if (check_offset) 353 offset = check_offset; 354 } 355 break; 356 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 357 check_offset = 358 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 359 if (check_offset) { 360 check_offset = RBIOS16(check_offset + 0x4); 361 if (check_offset) 362 offset = check_offset; 363 } 364 break; 365 default: 366 check_offset = 0; 367 break; 368 } 369 370 size = RBIOS8(rdev->bios_header_start + 0x6); 371 /* check absolute offset tables */ 372 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 373 offset = RBIOS16(rdev->bios_header_start + check_offset); 374 375 return offset; 376 } 377 378 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 379 { 380 int edid_info, size; 381 struct edid *edid; 382 unsigned char *raw; 383 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 384 if (!edid_info) 385 return false; 386 387 raw = rdev->bios + edid_info; 388 size = EDID_LENGTH * (raw[0x7e] + 1); 389 edid = kmalloc(size, GFP_KERNEL); 390 if (edid == NULL) 391 return false; 392 393 memcpy((unsigned char *)edid, raw, size); 394 395 if (!drm_edid_is_valid(edid)) { 396 kfree(edid); 397 return false; 398 } 399 400 rdev->mode_info.bios_hardcoded_edid = edid; 401 rdev->mode_info.bios_hardcoded_edid_size = size; 402 return true; 403 } 404 405 /* this is used for atom LCDs as well */ 406 struct edid * 407 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 408 { 409 struct edid *edid; 410 411 if (rdev->mode_info.bios_hardcoded_edid) { 412 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 413 if (edid) { 414 memcpy((unsigned char *)edid, 415 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 416 rdev->mode_info.bios_hardcoded_edid_size); 417 return edid; 418 } 419 } 420 return NULL; 421 } 422 423 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 424 enum radeon_combios_ddc ddc, 425 u32 clk_mask, 426 u32 data_mask) 427 { 428 struct radeon_i2c_bus_rec i2c; 429 int ddc_line = 0; 430 431 /* ddc id = mask reg 432 * DDC_NONE_DETECTED = none 433 * DDC_DVI = RADEON_GPIO_DVI_DDC 434 * DDC_VGA = RADEON_GPIO_VGA_DDC 435 * DDC_LCD = RADEON_GPIOPAD_MASK 436 * DDC_GPIO = RADEON_MDGPIO_MASK 437 * r1xx 438 * DDC_MONID = RADEON_GPIO_MONID 439 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 440 * r200 441 * DDC_MONID = RADEON_GPIO_MONID 442 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 443 * r300/r350 444 * DDC_MONID = RADEON_GPIO_DVI_DDC 445 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 446 * rv2xx/rv3xx 447 * DDC_MONID = RADEON_GPIO_MONID 448 * DDC_CRT2 = RADEON_GPIO_MONID 449 * rs3xx/rs4xx 450 * DDC_MONID = RADEON_GPIOPAD_MASK 451 * DDC_CRT2 = RADEON_GPIO_MONID 452 */ 453 switch (ddc) { 454 case DDC_NONE_DETECTED: 455 default: 456 ddc_line = 0; 457 break; 458 case DDC_DVI: 459 ddc_line = RADEON_GPIO_DVI_DDC; 460 break; 461 case DDC_VGA: 462 ddc_line = RADEON_GPIO_VGA_DDC; 463 break; 464 case DDC_LCD: 465 ddc_line = RADEON_GPIOPAD_MASK; 466 break; 467 case DDC_GPIO: 468 ddc_line = RADEON_MDGPIO_MASK; 469 break; 470 case DDC_MONID: 471 if (rdev->family == CHIP_RS300 || 472 rdev->family == CHIP_RS400 || 473 rdev->family == CHIP_RS480) 474 ddc_line = RADEON_GPIOPAD_MASK; 475 else if (rdev->family == CHIP_R300 || 476 rdev->family == CHIP_R350) { 477 ddc_line = RADEON_GPIO_DVI_DDC; 478 ddc = DDC_DVI; 479 } else 480 ddc_line = RADEON_GPIO_MONID; 481 break; 482 case DDC_CRT2: 483 if (rdev->family == CHIP_R200 || 484 rdev->family == CHIP_R300 || 485 rdev->family == CHIP_R350) { 486 ddc_line = RADEON_GPIO_DVI_DDC; 487 ddc = DDC_DVI; 488 } else if (rdev->family == CHIP_RS300 || 489 rdev->family == CHIP_RS400 || 490 rdev->family == CHIP_RS480) 491 ddc_line = RADEON_GPIO_MONID; 492 else if (rdev->family >= CHIP_RV350) { 493 ddc_line = RADEON_GPIO_MONID; 494 ddc = DDC_MONID; 495 } else 496 ddc_line = RADEON_GPIO_CRT2_DDC; 497 break; 498 } 499 500 if (ddc_line == RADEON_GPIOPAD_MASK) { 501 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 502 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 503 i2c.a_clk_reg = RADEON_GPIOPAD_A; 504 i2c.a_data_reg = RADEON_GPIOPAD_A; 505 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 506 i2c.en_data_reg = RADEON_GPIOPAD_EN; 507 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 508 i2c.y_data_reg = RADEON_GPIOPAD_Y; 509 } else if (ddc_line == RADEON_MDGPIO_MASK) { 510 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 511 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 512 i2c.a_clk_reg = RADEON_MDGPIO_A; 513 i2c.a_data_reg = RADEON_MDGPIO_A; 514 i2c.en_clk_reg = RADEON_MDGPIO_EN; 515 i2c.en_data_reg = RADEON_MDGPIO_EN; 516 i2c.y_clk_reg = RADEON_MDGPIO_Y; 517 i2c.y_data_reg = RADEON_MDGPIO_Y; 518 } else { 519 i2c.mask_clk_reg = ddc_line; 520 i2c.mask_data_reg = ddc_line; 521 i2c.a_clk_reg = ddc_line; 522 i2c.a_data_reg = ddc_line; 523 i2c.en_clk_reg = ddc_line; 524 i2c.en_data_reg = ddc_line; 525 i2c.y_clk_reg = ddc_line; 526 i2c.y_data_reg = ddc_line; 527 } 528 529 if (clk_mask && data_mask) { 530 /* system specific masks */ 531 i2c.mask_clk_mask = clk_mask; 532 i2c.mask_data_mask = data_mask; 533 i2c.a_clk_mask = clk_mask; 534 i2c.a_data_mask = data_mask; 535 i2c.en_clk_mask = clk_mask; 536 i2c.en_data_mask = data_mask; 537 i2c.y_clk_mask = clk_mask; 538 i2c.y_data_mask = data_mask; 539 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 540 (ddc_line == RADEON_MDGPIO_MASK)) { 541 /* default gpiopad masks */ 542 i2c.mask_clk_mask = (0x20 << 8); 543 i2c.mask_data_mask = 0x80; 544 i2c.a_clk_mask = (0x20 << 8); 545 i2c.a_data_mask = 0x80; 546 i2c.en_clk_mask = (0x20 << 8); 547 i2c.en_data_mask = 0x80; 548 i2c.y_clk_mask = (0x20 << 8); 549 i2c.y_data_mask = 0x80; 550 } else { 551 /* default masks for ddc pads */ 552 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 553 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 554 i2c.a_clk_mask = RADEON_GPIO_A_1; 555 i2c.a_data_mask = RADEON_GPIO_A_0; 556 i2c.en_clk_mask = RADEON_GPIO_EN_1; 557 i2c.en_data_mask = RADEON_GPIO_EN_0; 558 i2c.y_clk_mask = RADEON_GPIO_Y_1; 559 i2c.y_data_mask = RADEON_GPIO_Y_0; 560 } 561 562 switch (rdev->family) { 563 case CHIP_R100: 564 case CHIP_RV100: 565 case CHIP_RS100: 566 case CHIP_RV200: 567 case CHIP_RS200: 568 case CHIP_RS300: 569 switch (ddc_line) { 570 case RADEON_GPIO_DVI_DDC: 571 i2c.hw_capable = true; 572 break; 573 default: 574 i2c.hw_capable = false; 575 break; 576 } 577 break; 578 case CHIP_R200: 579 switch (ddc_line) { 580 case RADEON_GPIO_DVI_DDC: 581 case RADEON_GPIO_MONID: 582 i2c.hw_capable = true; 583 break; 584 default: 585 i2c.hw_capable = false; 586 break; 587 } 588 break; 589 case CHIP_RV250: 590 case CHIP_RV280: 591 switch (ddc_line) { 592 case RADEON_GPIO_VGA_DDC: 593 case RADEON_GPIO_DVI_DDC: 594 case RADEON_GPIO_CRT2_DDC: 595 i2c.hw_capable = true; 596 break; 597 default: 598 i2c.hw_capable = false; 599 break; 600 } 601 break; 602 case CHIP_R300: 603 case CHIP_R350: 604 switch (ddc_line) { 605 case RADEON_GPIO_VGA_DDC: 606 case RADEON_GPIO_DVI_DDC: 607 i2c.hw_capable = true; 608 break; 609 default: 610 i2c.hw_capable = false; 611 break; 612 } 613 break; 614 case CHIP_RV350: 615 case CHIP_RV380: 616 case CHIP_RS400: 617 case CHIP_RS480: 618 switch (ddc_line) { 619 case RADEON_GPIO_VGA_DDC: 620 case RADEON_GPIO_DVI_DDC: 621 i2c.hw_capable = true; 622 break; 623 case RADEON_GPIO_MONID: 624 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 625 * reliably on some pre-r4xx hardware; not sure why. 626 */ 627 i2c.hw_capable = false; 628 break; 629 default: 630 i2c.hw_capable = false; 631 break; 632 } 633 break; 634 default: 635 i2c.hw_capable = false; 636 break; 637 } 638 i2c.mm_i2c = false; 639 640 i2c.i2c_id = ddc; 641 i2c.hpd = RADEON_HPD_NONE; 642 643 if (ddc_line) 644 i2c.valid = true; 645 else 646 i2c.valid = false; 647 648 return i2c; 649 } 650 651 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 652 { 653 struct drm_device *dev = rdev->ddev; 654 struct radeon_i2c_bus_rec i2c; 655 u16 offset; 656 u8 id, blocks, clk, data; 657 int i; 658 659 i2c.valid = false; 660 661 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 662 if (offset) { 663 blocks = RBIOS8(offset + 2); 664 for (i = 0; i < blocks; i++) { 665 id = RBIOS8(offset + 3 + (i * 5) + 0); 666 if (id == 136) { 667 clk = RBIOS8(offset + 3 + (i * 5) + 3); 668 data = RBIOS8(offset + 3 + (i * 5) + 4); 669 /* gpiopad */ 670 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 671 (1 << clk), (1 << data)); 672 break; 673 } 674 } 675 } 676 return i2c; 677 } 678 679 void radeon_combios_i2c_init(struct radeon_device *rdev) 680 { 681 struct drm_device *dev = rdev->ddev; 682 struct radeon_i2c_bus_rec i2c; 683 684 /* actual hw pads 685 * r1xx/rs2xx/rs3xx 686 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 687 * r200 688 * 0x60, 0x64, 0x68, mm 689 * r300/r350 690 * 0x60, 0x64, mm 691 * rv2xx/rv3xx/rs4xx 692 * 0x60, 0x64, 0x68, gpiopads, mm 693 */ 694 695 /* 0x60 */ 696 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 697 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 698 /* 0x64 */ 699 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 700 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 701 702 /* mm i2c */ 703 i2c.valid = true; 704 i2c.hw_capable = true; 705 i2c.mm_i2c = true; 706 i2c.i2c_id = 0xa0; 707 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 708 709 if (rdev->family == CHIP_R300 || 710 rdev->family == CHIP_R350) { 711 /* only 2 sw i2c pads */ 712 } else if (rdev->family == CHIP_RS300 || 713 rdev->family == CHIP_RS400 || 714 rdev->family == CHIP_RS480) { 715 /* 0x68 */ 716 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 717 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 718 719 /* gpiopad */ 720 i2c = radeon_combios_get_i2c_info_from_table(rdev); 721 if (i2c.valid) 722 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 723 } else if ((rdev->family == CHIP_R200) || 724 (rdev->family >= CHIP_R300)) { 725 /* 0x68 */ 726 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 727 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 728 } else { 729 /* 0x68 */ 730 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 731 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 732 /* 0x6c */ 733 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 735 } 736 } 737 738 bool radeon_combios_get_clock_info(struct drm_device *dev) 739 { 740 struct radeon_device *rdev = dev->dev_private; 741 uint16_t pll_info; 742 struct radeon_pll *p1pll = &rdev->clock.p1pll; 743 struct radeon_pll *p2pll = &rdev->clock.p2pll; 744 struct radeon_pll *spll = &rdev->clock.spll; 745 struct radeon_pll *mpll = &rdev->clock.mpll; 746 int8_t rev; 747 uint16_t sclk, mclk; 748 749 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 750 if (pll_info) { 751 rev = RBIOS8(pll_info); 752 753 /* pixel clocks */ 754 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 755 p1pll->reference_div = RBIOS16(pll_info + 0x10); 756 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 757 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 758 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 759 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 760 761 if (rev > 9) { 762 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 763 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 764 } else { 765 p1pll->pll_in_min = 40; 766 p1pll->pll_in_max = 500; 767 } 768 *p2pll = *p1pll; 769 770 /* system clock */ 771 spll->reference_freq = RBIOS16(pll_info + 0x1a); 772 spll->reference_div = RBIOS16(pll_info + 0x1c); 773 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 774 spll->pll_out_max = RBIOS32(pll_info + 0x22); 775 776 if (rev > 10) { 777 spll->pll_in_min = RBIOS32(pll_info + 0x48); 778 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 779 } else { 780 /* ??? */ 781 spll->pll_in_min = 40; 782 spll->pll_in_max = 500; 783 } 784 785 /* memory clock */ 786 mpll->reference_freq = RBIOS16(pll_info + 0x26); 787 mpll->reference_div = RBIOS16(pll_info + 0x28); 788 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 789 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 790 791 if (rev > 10) { 792 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 793 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 794 } else { 795 /* ??? */ 796 mpll->pll_in_min = 40; 797 mpll->pll_in_max = 500; 798 } 799 800 /* default sclk/mclk */ 801 sclk = RBIOS16(pll_info + 0xa); 802 mclk = RBIOS16(pll_info + 0x8); 803 if (sclk == 0) 804 sclk = 200 * 100; 805 if (mclk == 0) 806 mclk = 200 * 100; 807 808 rdev->clock.default_sclk = sclk; 809 rdev->clock.default_mclk = mclk; 810 811 if (RBIOS32(pll_info + 0x16)) 812 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 813 else 814 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 815 816 return true; 817 } 818 return false; 819 } 820 821 bool radeon_combios_sideport_present(struct radeon_device *rdev) 822 { 823 struct drm_device *dev = rdev->ddev; 824 u16 igp_info; 825 826 /* sideport is AMD only */ 827 if (rdev->family == CHIP_RS400) 828 return false; 829 830 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 831 832 if (igp_info) { 833 if (RBIOS16(igp_info + 0x4)) 834 return true; 835 } 836 return false; 837 } 838 839 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 840 0x00000808, /* r100 */ 841 0x00000808, /* rv100 */ 842 0x00000808, /* rs100 */ 843 0x00000808, /* rv200 */ 844 0x00000808, /* rs200 */ 845 0x00000808, /* r200 */ 846 0x00000808, /* rv250 */ 847 0x00000000, /* rs300 */ 848 0x00000808, /* rv280 */ 849 0x00000808, /* r300 */ 850 0x00000808, /* r350 */ 851 0x00000808, /* rv350 */ 852 0x00000808, /* rv380 */ 853 0x00000808, /* r420 */ 854 0x00000808, /* r423 */ 855 0x00000808, /* rv410 */ 856 0x00000000, /* rs400 */ 857 0x00000000, /* rs480 */ 858 }; 859 860 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 861 struct radeon_encoder_primary_dac *p_dac) 862 { 863 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 864 return; 865 } 866 867 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 868 radeon_encoder 869 *encoder) 870 { 871 struct drm_device *dev = encoder->base.dev; 872 struct radeon_device *rdev = dev->dev_private; 873 uint16_t dac_info; 874 uint8_t rev, bg, dac; 875 struct radeon_encoder_primary_dac *p_dac = NULL; 876 int found = 0; 877 878 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 879 GFP_KERNEL); 880 881 if (!p_dac) 882 return NULL; 883 884 /* check CRT table */ 885 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 886 if (dac_info) { 887 rev = RBIOS8(dac_info) & 0x3; 888 if (rev < 2) { 889 bg = RBIOS8(dac_info + 0x2) & 0xf; 890 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 891 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 892 } else { 893 bg = RBIOS8(dac_info + 0x2) & 0xf; 894 dac = RBIOS8(dac_info + 0x3) & 0xf; 895 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 896 } 897 /* if the values are zeros, use the table */ 898 if ((dac == 0) || (bg == 0)) 899 found = 0; 900 else 901 found = 1; 902 } 903 904 /* quirks */ 905 /* Radeon 7000 (RV100) */ 906 if (((dev->pdev->device == 0x5159) && 907 (dev->pdev->subsystem_vendor == 0x174B) && 908 (dev->pdev->subsystem_device == 0x7c28)) || 909 /* Radeon 9100 (R200) */ 910 ((dev->pdev->device == 0x514D) && 911 (dev->pdev->subsystem_vendor == 0x174B) && 912 (dev->pdev->subsystem_device == 0x7149))) { 913 /* vbios value is bad, use the default */ 914 found = 0; 915 } 916 917 if (!found) /* fallback to defaults */ 918 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 919 920 return p_dac; 921 } 922 923 enum radeon_tv_std 924 radeon_combios_get_tv_info(struct radeon_device *rdev) 925 { 926 struct drm_device *dev = rdev->ddev; 927 uint16_t tv_info; 928 enum radeon_tv_std tv_std = TV_STD_NTSC; 929 930 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 931 if (tv_info) { 932 if (RBIOS8(tv_info + 6) == 'T') { 933 switch (RBIOS8(tv_info + 7) & 0xf) { 934 case 1: 935 tv_std = TV_STD_NTSC; 936 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 937 break; 938 case 2: 939 tv_std = TV_STD_PAL; 940 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 941 break; 942 case 3: 943 tv_std = TV_STD_PAL_M; 944 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 945 break; 946 case 4: 947 tv_std = TV_STD_PAL_60; 948 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 949 break; 950 case 5: 951 tv_std = TV_STD_NTSC_J; 952 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 953 break; 954 case 6: 955 tv_std = TV_STD_SCART_PAL; 956 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 957 break; 958 default: 959 tv_std = TV_STD_NTSC; 960 DRM_DEBUG_KMS 961 ("Unknown TV standard; defaulting to NTSC\n"); 962 break; 963 } 964 965 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 966 case 0: 967 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 968 break; 969 case 1: 970 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 971 break; 972 case 2: 973 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 974 break; 975 case 3: 976 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 977 break; 978 default: 979 break; 980 } 981 } 982 } 983 return tv_std; 984 } 985 986 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 987 0x00000000, /* r100 */ 988 0x00280000, /* rv100 */ 989 0x00000000, /* rs100 */ 990 0x00880000, /* rv200 */ 991 0x00000000, /* rs200 */ 992 0x00000000, /* r200 */ 993 0x00770000, /* rv250 */ 994 0x00290000, /* rs300 */ 995 0x00560000, /* rv280 */ 996 0x00780000, /* r300 */ 997 0x00770000, /* r350 */ 998 0x00780000, /* rv350 */ 999 0x00780000, /* rv380 */ 1000 0x01080000, /* r420 */ 1001 0x01080000, /* r423 */ 1002 0x01080000, /* rv410 */ 1003 0x00780000, /* rs400 */ 1004 0x00780000, /* rs480 */ 1005 }; 1006 1007 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1008 struct radeon_encoder_tv_dac *tv_dac) 1009 { 1010 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1011 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1012 tv_dac->ps2_tvdac_adj = 0x00880000; 1013 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1014 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1015 return; 1016 } 1017 1018 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1019 radeon_encoder 1020 *encoder) 1021 { 1022 struct drm_device *dev = encoder->base.dev; 1023 struct radeon_device *rdev = dev->dev_private; 1024 uint16_t dac_info; 1025 uint8_t rev, bg, dac; 1026 struct radeon_encoder_tv_dac *tv_dac = NULL; 1027 int found = 0; 1028 1029 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1030 if (!tv_dac) 1031 return NULL; 1032 1033 /* first check TV table */ 1034 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1035 if (dac_info) { 1036 rev = RBIOS8(dac_info + 0x3); 1037 if (rev > 4) { 1038 bg = RBIOS8(dac_info + 0xc) & 0xf; 1039 dac = RBIOS8(dac_info + 0xd) & 0xf; 1040 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1041 1042 bg = RBIOS8(dac_info + 0xe) & 0xf; 1043 dac = RBIOS8(dac_info + 0xf) & 0xf; 1044 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1045 1046 bg = RBIOS8(dac_info + 0x10) & 0xf; 1047 dac = RBIOS8(dac_info + 0x11) & 0xf; 1048 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1049 /* if the values are all zeros, use the table */ 1050 if (tv_dac->ps2_tvdac_adj) 1051 found = 1; 1052 } else if (rev > 1) { 1053 bg = RBIOS8(dac_info + 0xc) & 0xf; 1054 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1055 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1056 1057 bg = RBIOS8(dac_info + 0xd) & 0xf; 1058 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1059 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1060 1061 bg = RBIOS8(dac_info + 0xe) & 0xf; 1062 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1063 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1064 /* if the values are all zeros, use the table */ 1065 if (tv_dac->ps2_tvdac_adj) 1066 found = 1; 1067 } 1068 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1069 } 1070 if (!found) { 1071 /* then check CRT table */ 1072 dac_info = 1073 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1074 if (dac_info) { 1075 rev = RBIOS8(dac_info) & 0x3; 1076 if (rev < 2) { 1077 bg = RBIOS8(dac_info + 0x3) & 0xf; 1078 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1079 tv_dac->ps2_tvdac_adj = 1080 (bg << 16) | (dac << 20); 1081 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1082 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1083 /* if the values are all zeros, use the table */ 1084 if (tv_dac->ps2_tvdac_adj) 1085 found = 1; 1086 } else { 1087 bg = RBIOS8(dac_info + 0x4) & 0xf; 1088 dac = RBIOS8(dac_info + 0x5) & 0xf; 1089 tv_dac->ps2_tvdac_adj = 1090 (bg << 16) | (dac << 20); 1091 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1092 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1093 /* if the values are all zeros, use the table */ 1094 if (tv_dac->ps2_tvdac_adj) 1095 found = 1; 1096 } 1097 } else { 1098 DRM_INFO("No TV DAC info found in BIOS\n"); 1099 } 1100 } 1101 1102 if (!found) /* fallback to defaults */ 1103 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1104 1105 return tv_dac; 1106 } 1107 1108 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1109 radeon_device 1110 *rdev) 1111 { 1112 struct radeon_encoder_lvds *lvds = NULL; 1113 uint32_t fp_vert_stretch, fp_horz_stretch; 1114 uint32_t ppll_div_sel, ppll_val; 1115 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1116 1117 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1118 1119 if (!lvds) 1120 return NULL; 1121 1122 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1123 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1124 1125 /* These should be fail-safe defaults, fingers crossed */ 1126 lvds->panel_pwr_delay = 200; 1127 lvds->panel_vcc_delay = 2000; 1128 1129 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1130 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1131 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1132 1133 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1134 lvds->native_mode.vdisplay = 1135 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1136 RADEON_VERT_PANEL_SHIFT) + 1; 1137 else 1138 lvds->native_mode.vdisplay = 1139 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1140 1141 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1142 lvds->native_mode.hdisplay = 1143 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1144 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1145 else 1146 lvds->native_mode.hdisplay = 1147 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1148 1149 if ((lvds->native_mode.hdisplay < 640) || 1150 (lvds->native_mode.vdisplay < 480)) { 1151 lvds->native_mode.hdisplay = 640; 1152 lvds->native_mode.vdisplay = 480; 1153 } 1154 1155 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1156 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1157 if ((ppll_val & 0x000707ff) == 0x1bb) 1158 lvds->use_bios_dividers = false; 1159 else { 1160 lvds->panel_ref_divider = 1161 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1162 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1163 lvds->panel_fb_divider = ppll_val & 0x7ff; 1164 1165 if ((lvds->panel_ref_divider != 0) && 1166 (lvds->panel_fb_divider > 3)) 1167 lvds->use_bios_dividers = true; 1168 } 1169 lvds->panel_vcc_delay = 200; 1170 1171 DRM_INFO("Panel info derived from registers\n"); 1172 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1173 lvds->native_mode.vdisplay); 1174 1175 return lvds; 1176 } 1177 1178 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1179 *encoder) 1180 { 1181 struct drm_device *dev = encoder->base.dev; 1182 struct radeon_device *rdev = dev->dev_private; 1183 uint16_t lcd_info; 1184 uint32_t panel_setup; 1185 char stmp[30]; 1186 int tmp, i; 1187 struct radeon_encoder_lvds *lvds = NULL; 1188 1189 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1190 1191 if (lcd_info) { 1192 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1193 1194 if (!lvds) 1195 return NULL; 1196 1197 for (i = 0; i < 24; i++) 1198 stmp[i] = RBIOS8(lcd_info + i + 1); 1199 stmp[24] = 0; 1200 1201 DRM_INFO("Panel ID String: %s\n", stmp); 1202 1203 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1204 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1205 1206 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1207 lvds->native_mode.vdisplay); 1208 1209 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1210 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1211 1212 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1213 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1214 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1215 1216 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1217 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1218 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1219 if ((lvds->panel_ref_divider != 0) && 1220 (lvds->panel_fb_divider > 3)) 1221 lvds->use_bios_dividers = true; 1222 1223 panel_setup = RBIOS32(lcd_info + 0x39); 1224 lvds->lvds_gen_cntl = 0xff00; 1225 if (panel_setup & 0x1) 1226 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1227 1228 if ((panel_setup >> 4) & 0x1) 1229 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1230 1231 switch ((panel_setup >> 8) & 0x7) { 1232 case 0: 1233 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1234 break; 1235 case 1: 1236 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1237 break; 1238 case 2: 1239 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1240 break; 1241 default: 1242 break; 1243 } 1244 1245 if ((panel_setup >> 16) & 0x1) 1246 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1247 1248 if ((panel_setup >> 17) & 0x1) 1249 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1250 1251 if ((panel_setup >> 18) & 0x1) 1252 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1253 1254 if ((panel_setup >> 23) & 0x1) 1255 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1256 1257 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1258 1259 for (i = 0; i < 32; i++) { 1260 tmp = RBIOS16(lcd_info + 64 + i * 2); 1261 if (tmp == 0) 1262 break; 1263 1264 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1265 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1266 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1267 1268 if (hss > lvds->native_mode.hdisplay) 1269 hss = (10 - 1) * 8; 1270 1271 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1272 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1273 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1274 hss; 1275 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1276 (RBIOS8(tmp + 23) * 8); 1277 1278 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1279 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1280 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1281 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1282 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1283 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1284 1285 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1286 lvds->native_mode.flags = 0; 1287 /* set crtc values */ 1288 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1289 1290 } 1291 } 1292 } else { 1293 DRM_INFO("No panel info found in BIOS\n"); 1294 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1295 } 1296 1297 if (lvds) 1298 encoder->native_mode = lvds->native_mode; 1299 return lvds; 1300 } 1301 1302 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1303 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1304 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1305 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1306 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1307 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1308 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1309 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1310 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1311 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1312 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1313 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1314 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1315 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1316 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1317 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1318 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1319 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1320 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1321 }; 1322 1323 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1324 struct radeon_encoder_int_tmds *tmds) 1325 { 1326 struct drm_device *dev = encoder->base.dev; 1327 struct radeon_device *rdev = dev->dev_private; 1328 int i; 1329 1330 for (i = 0; i < 4; i++) { 1331 tmds->tmds_pll[i].value = 1332 default_tmds_pll[rdev->family][i].value; 1333 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1334 } 1335 1336 return true; 1337 } 1338 1339 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1340 struct radeon_encoder_int_tmds *tmds) 1341 { 1342 struct drm_device *dev = encoder->base.dev; 1343 struct radeon_device *rdev = dev->dev_private; 1344 uint16_t tmds_info; 1345 int i, n; 1346 uint8_t ver; 1347 1348 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1349 1350 if (tmds_info) { 1351 ver = RBIOS8(tmds_info); 1352 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1353 if (ver == 3) { 1354 n = RBIOS8(tmds_info + 5) + 1; 1355 if (n > 4) 1356 n = 4; 1357 for (i = 0; i < n; i++) { 1358 tmds->tmds_pll[i].value = 1359 RBIOS32(tmds_info + i * 10 + 0x08); 1360 tmds->tmds_pll[i].freq = 1361 RBIOS16(tmds_info + i * 10 + 0x10); 1362 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1363 tmds->tmds_pll[i].freq, 1364 tmds->tmds_pll[i].value); 1365 } 1366 } else if (ver == 4) { 1367 int stride = 0; 1368 n = RBIOS8(tmds_info + 5) + 1; 1369 if (n > 4) 1370 n = 4; 1371 for (i = 0; i < n; i++) { 1372 tmds->tmds_pll[i].value = 1373 RBIOS32(tmds_info + stride + 0x08); 1374 tmds->tmds_pll[i].freq = 1375 RBIOS16(tmds_info + stride + 0x10); 1376 if (i == 0) 1377 stride += 10; 1378 else 1379 stride += 6; 1380 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1381 tmds->tmds_pll[i].freq, 1382 tmds->tmds_pll[i].value); 1383 } 1384 } 1385 } else { 1386 DRM_INFO("No TMDS info found in BIOS\n"); 1387 return false; 1388 } 1389 return true; 1390 } 1391 1392 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1393 struct radeon_encoder_ext_tmds *tmds) 1394 { 1395 struct drm_device *dev = encoder->base.dev; 1396 struct radeon_device *rdev = dev->dev_private; 1397 struct radeon_i2c_bus_rec i2c_bus; 1398 1399 /* default for macs */ 1400 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1401 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1402 1403 /* XXX some macs have duallink chips */ 1404 switch (rdev->mode_info.connector_table) { 1405 case CT_POWERBOOK_EXTERNAL: 1406 case CT_MINI_EXTERNAL: 1407 default: 1408 tmds->dvo_chip = DVO_SIL164; 1409 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1410 break; 1411 } 1412 1413 return true; 1414 } 1415 1416 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1417 struct radeon_encoder_ext_tmds *tmds) 1418 { 1419 struct drm_device *dev = encoder->base.dev; 1420 struct radeon_device *rdev = dev->dev_private; 1421 uint16_t offset; 1422 uint8_t ver; 1423 enum radeon_combios_ddc gpio; 1424 struct radeon_i2c_bus_rec i2c_bus; 1425 1426 tmds->i2c_bus = NULL; 1427 if (rdev->flags & RADEON_IS_IGP) { 1428 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1429 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1430 tmds->dvo_chip = DVO_SIL164; 1431 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1432 } else { 1433 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1434 if (offset) { 1435 ver = RBIOS8(offset); 1436 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1437 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1438 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1439 gpio = RBIOS8(offset + 4 + 3); 1440 if (gpio == DDC_LCD) { 1441 /* MM i2c */ 1442 i2c_bus.valid = true; 1443 i2c_bus.hw_capable = true; 1444 i2c_bus.mm_i2c = true; 1445 i2c_bus.i2c_id = 0xa0; 1446 } else 1447 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1448 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1449 } 1450 } 1451 1452 if (!tmds->i2c_bus) { 1453 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1454 return false; 1455 } 1456 1457 return true; 1458 } 1459 1460 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1461 { 1462 struct radeon_device *rdev = dev->dev_private; 1463 struct radeon_i2c_bus_rec ddc_i2c; 1464 struct radeon_hpd hpd; 1465 1466 rdev->mode_info.connector_table = radeon_connector_table; 1467 if (rdev->mode_info.connector_table == CT_NONE) { 1468 #ifdef CONFIG_PPC_PMAC 1469 if (of_machine_is_compatible("PowerBook3,3")) { 1470 /* powerbook with VGA */ 1471 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1472 } else if (of_machine_is_compatible("PowerBook3,4") || 1473 of_machine_is_compatible("PowerBook3,5")) { 1474 /* powerbook with internal tmds */ 1475 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1476 } else if (of_machine_is_compatible("PowerBook5,1") || 1477 of_machine_is_compatible("PowerBook5,2") || 1478 of_machine_is_compatible("PowerBook5,3") || 1479 of_machine_is_compatible("PowerBook5,4") || 1480 of_machine_is_compatible("PowerBook5,5")) { 1481 /* powerbook with external single link tmds (sil164) */ 1482 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1483 } else if (of_machine_is_compatible("PowerBook5,6")) { 1484 /* powerbook with external dual or single link tmds */ 1485 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1486 } else if (of_machine_is_compatible("PowerBook5,7") || 1487 of_machine_is_compatible("PowerBook5,8") || 1488 of_machine_is_compatible("PowerBook5,9")) { 1489 /* PowerBook6,2 ? */ 1490 /* powerbook with external dual link tmds (sil1178?) */ 1491 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1492 } else if (of_machine_is_compatible("PowerBook4,1") || 1493 of_machine_is_compatible("PowerBook4,2") || 1494 of_machine_is_compatible("PowerBook4,3") || 1495 of_machine_is_compatible("PowerBook6,3") || 1496 of_machine_is_compatible("PowerBook6,5") || 1497 of_machine_is_compatible("PowerBook6,7")) { 1498 /* ibook */ 1499 rdev->mode_info.connector_table = CT_IBOOK; 1500 } else if (of_machine_is_compatible("PowerMac3,5")) { 1501 /* PowerMac G4 Silver radeon 7500 */ 1502 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1503 } else if (of_machine_is_compatible("PowerMac4,4")) { 1504 /* emac */ 1505 rdev->mode_info.connector_table = CT_EMAC; 1506 } else if (of_machine_is_compatible("PowerMac10,1")) { 1507 /* mini with internal tmds */ 1508 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1509 } else if (of_machine_is_compatible("PowerMac10,2")) { 1510 /* mini with external tmds */ 1511 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1512 } else if (of_machine_is_compatible("PowerMac12,1")) { 1513 /* PowerMac8,1 ? */ 1514 /* imac g5 isight */ 1515 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1516 } else if ((rdev->pdev->device == 0x4a48) && 1517 (rdev->pdev->subsystem_vendor == 0x1002) && 1518 (rdev->pdev->subsystem_device == 0x4a48)) { 1519 /* Mac X800 */ 1520 rdev->mode_info.connector_table = CT_MAC_X800; 1521 } else if ((of_machine_is_compatible("PowerMac7,2") || 1522 of_machine_is_compatible("PowerMac7,3")) && 1523 (rdev->pdev->device == 0x4150) && 1524 (rdev->pdev->subsystem_vendor == 0x1002) && 1525 (rdev->pdev->subsystem_device == 0x4150)) { 1526 /* Mac G5 tower 9600 */ 1527 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1528 } else if ((rdev->pdev->device == 0x4c66) && 1529 (rdev->pdev->subsystem_vendor == 0x1002) && 1530 (rdev->pdev->subsystem_device == 0x4c66)) { 1531 /* SAM440ep RV250 embedded board */ 1532 rdev->mode_info.connector_table = CT_SAM440EP; 1533 } else 1534 #endif /* CONFIG_PPC_PMAC */ 1535 #ifdef CONFIG_PPC64 1536 if (ASIC_IS_RN50(rdev)) 1537 rdev->mode_info.connector_table = CT_RN50_POWER; 1538 else 1539 #endif 1540 rdev->mode_info.connector_table = CT_GENERIC; 1541 } 1542 1543 switch (rdev->mode_info.connector_table) { 1544 case CT_GENERIC: 1545 DRM_INFO("Connector Table: %d (generic)\n", 1546 rdev->mode_info.connector_table); 1547 /* these are the most common settings */ 1548 if (rdev->flags & RADEON_SINGLE_CRTC) { 1549 /* VGA - primary dac */ 1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1551 hpd.hpd = RADEON_HPD_NONE; 1552 radeon_add_legacy_encoder(dev, 1553 radeon_get_encoder_enum(dev, 1554 ATOM_DEVICE_CRT1_SUPPORT, 1555 1), 1556 ATOM_DEVICE_CRT1_SUPPORT); 1557 radeon_add_legacy_connector(dev, 0, 1558 ATOM_DEVICE_CRT1_SUPPORT, 1559 DRM_MODE_CONNECTOR_VGA, 1560 &ddc_i2c, 1561 CONNECTOR_OBJECT_ID_VGA, 1562 &hpd); 1563 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1564 /* LVDS */ 1565 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1566 hpd.hpd = RADEON_HPD_NONE; 1567 radeon_add_legacy_encoder(dev, 1568 radeon_get_encoder_enum(dev, 1569 ATOM_DEVICE_LCD1_SUPPORT, 1570 0), 1571 ATOM_DEVICE_LCD1_SUPPORT); 1572 radeon_add_legacy_connector(dev, 0, 1573 ATOM_DEVICE_LCD1_SUPPORT, 1574 DRM_MODE_CONNECTOR_LVDS, 1575 &ddc_i2c, 1576 CONNECTOR_OBJECT_ID_LVDS, 1577 &hpd); 1578 1579 /* VGA - primary dac */ 1580 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1581 hpd.hpd = RADEON_HPD_NONE; 1582 radeon_add_legacy_encoder(dev, 1583 radeon_get_encoder_enum(dev, 1584 ATOM_DEVICE_CRT1_SUPPORT, 1585 1), 1586 ATOM_DEVICE_CRT1_SUPPORT); 1587 radeon_add_legacy_connector(dev, 1, 1588 ATOM_DEVICE_CRT1_SUPPORT, 1589 DRM_MODE_CONNECTOR_VGA, 1590 &ddc_i2c, 1591 CONNECTOR_OBJECT_ID_VGA, 1592 &hpd); 1593 } else { 1594 /* DVI-I - tv dac, int tmds */ 1595 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1596 hpd.hpd = RADEON_HPD_1; 1597 radeon_add_legacy_encoder(dev, 1598 radeon_get_encoder_enum(dev, 1599 ATOM_DEVICE_DFP1_SUPPORT, 1600 0), 1601 ATOM_DEVICE_DFP1_SUPPORT); 1602 radeon_add_legacy_encoder(dev, 1603 radeon_get_encoder_enum(dev, 1604 ATOM_DEVICE_CRT2_SUPPORT, 1605 2), 1606 ATOM_DEVICE_CRT2_SUPPORT); 1607 radeon_add_legacy_connector(dev, 0, 1608 ATOM_DEVICE_DFP1_SUPPORT | 1609 ATOM_DEVICE_CRT2_SUPPORT, 1610 DRM_MODE_CONNECTOR_DVII, 1611 &ddc_i2c, 1612 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1613 &hpd); 1614 1615 /* VGA - primary dac */ 1616 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1617 hpd.hpd = RADEON_HPD_NONE; 1618 radeon_add_legacy_encoder(dev, 1619 radeon_get_encoder_enum(dev, 1620 ATOM_DEVICE_CRT1_SUPPORT, 1621 1), 1622 ATOM_DEVICE_CRT1_SUPPORT); 1623 radeon_add_legacy_connector(dev, 1, 1624 ATOM_DEVICE_CRT1_SUPPORT, 1625 DRM_MODE_CONNECTOR_VGA, 1626 &ddc_i2c, 1627 CONNECTOR_OBJECT_ID_VGA, 1628 &hpd); 1629 } 1630 1631 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1632 /* TV - tv dac */ 1633 ddc_i2c.valid = false; 1634 hpd.hpd = RADEON_HPD_NONE; 1635 radeon_add_legacy_encoder(dev, 1636 radeon_get_encoder_enum(dev, 1637 ATOM_DEVICE_TV1_SUPPORT, 1638 2), 1639 ATOM_DEVICE_TV1_SUPPORT); 1640 radeon_add_legacy_connector(dev, 2, 1641 ATOM_DEVICE_TV1_SUPPORT, 1642 DRM_MODE_CONNECTOR_SVIDEO, 1643 &ddc_i2c, 1644 CONNECTOR_OBJECT_ID_SVIDEO, 1645 &hpd); 1646 } 1647 break; 1648 case CT_IBOOK: 1649 DRM_INFO("Connector Table: %d (ibook)\n", 1650 rdev->mode_info.connector_table); 1651 /* LVDS */ 1652 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1653 hpd.hpd = RADEON_HPD_NONE; 1654 radeon_add_legacy_encoder(dev, 1655 radeon_get_encoder_enum(dev, 1656 ATOM_DEVICE_LCD1_SUPPORT, 1657 0), 1658 ATOM_DEVICE_LCD1_SUPPORT); 1659 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1660 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1661 CONNECTOR_OBJECT_ID_LVDS, 1662 &hpd); 1663 /* VGA - TV DAC */ 1664 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1665 hpd.hpd = RADEON_HPD_NONE; 1666 radeon_add_legacy_encoder(dev, 1667 radeon_get_encoder_enum(dev, 1668 ATOM_DEVICE_CRT2_SUPPORT, 1669 2), 1670 ATOM_DEVICE_CRT2_SUPPORT); 1671 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1672 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1673 CONNECTOR_OBJECT_ID_VGA, 1674 &hpd); 1675 /* TV - TV DAC */ 1676 ddc_i2c.valid = false; 1677 hpd.hpd = RADEON_HPD_NONE; 1678 radeon_add_legacy_encoder(dev, 1679 radeon_get_encoder_enum(dev, 1680 ATOM_DEVICE_TV1_SUPPORT, 1681 2), 1682 ATOM_DEVICE_TV1_SUPPORT); 1683 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1684 DRM_MODE_CONNECTOR_SVIDEO, 1685 &ddc_i2c, 1686 CONNECTOR_OBJECT_ID_SVIDEO, 1687 &hpd); 1688 break; 1689 case CT_POWERBOOK_EXTERNAL: 1690 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1691 rdev->mode_info.connector_table); 1692 /* LVDS */ 1693 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1694 hpd.hpd = RADEON_HPD_NONE; 1695 radeon_add_legacy_encoder(dev, 1696 radeon_get_encoder_enum(dev, 1697 ATOM_DEVICE_LCD1_SUPPORT, 1698 0), 1699 ATOM_DEVICE_LCD1_SUPPORT); 1700 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1701 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1702 CONNECTOR_OBJECT_ID_LVDS, 1703 &hpd); 1704 /* DVI-I - primary dac, ext tmds */ 1705 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1706 hpd.hpd = RADEON_HPD_2; /* ??? */ 1707 radeon_add_legacy_encoder(dev, 1708 radeon_get_encoder_enum(dev, 1709 ATOM_DEVICE_DFP2_SUPPORT, 1710 0), 1711 ATOM_DEVICE_DFP2_SUPPORT); 1712 radeon_add_legacy_encoder(dev, 1713 radeon_get_encoder_enum(dev, 1714 ATOM_DEVICE_CRT1_SUPPORT, 1715 1), 1716 ATOM_DEVICE_CRT1_SUPPORT); 1717 /* XXX some are SL */ 1718 radeon_add_legacy_connector(dev, 1, 1719 ATOM_DEVICE_DFP2_SUPPORT | 1720 ATOM_DEVICE_CRT1_SUPPORT, 1721 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1722 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1723 &hpd); 1724 /* TV - TV DAC */ 1725 ddc_i2c.valid = false; 1726 hpd.hpd = RADEON_HPD_NONE; 1727 radeon_add_legacy_encoder(dev, 1728 radeon_get_encoder_enum(dev, 1729 ATOM_DEVICE_TV1_SUPPORT, 1730 2), 1731 ATOM_DEVICE_TV1_SUPPORT); 1732 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1733 DRM_MODE_CONNECTOR_SVIDEO, 1734 &ddc_i2c, 1735 CONNECTOR_OBJECT_ID_SVIDEO, 1736 &hpd); 1737 break; 1738 case CT_POWERBOOK_INTERNAL: 1739 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1740 rdev->mode_info.connector_table); 1741 /* LVDS */ 1742 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1743 hpd.hpd = RADEON_HPD_NONE; 1744 radeon_add_legacy_encoder(dev, 1745 radeon_get_encoder_enum(dev, 1746 ATOM_DEVICE_LCD1_SUPPORT, 1747 0), 1748 ATOM_DEVICE_LCD1_SUPPORT); 1749 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1750 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1751 CONNECTOR_OBJECT_ID_LVDS, 1752 &hpd); 1753 /* DVI-I - primary dac, int tmds */ 1754 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1755 hpd.hpd = RADEON_HPD_1; /* ??? */ 1756 radeon_add_legacy_encoder(dev, 1757 radeon_get_encoder_enum(dev, 1758 ATOM_DEVICE_DFP1_SUPPORT, 1759 0), 1760 ATOM_DEVICE_DFP1_SUPPORT); 1761 radeon_add_legacy_encoder(dev, 1762 radeon_get_encoder_enum(dev, 1763 ATOM_DEVICE_CRT1_SUPPORT, 1764 1), 1765 ATOM_DEVICE_CRT1_SUPPORT); 1766 radeon_add_legacy_connector(dev, 1, 1767 ATOM_DEVICE_DFP1_SUPPORT | 1768 ATOM_DEVICE_CRT1_SUPPORT, 1769 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1770 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1771 &hpd); 1772 /* TV - TV DAC */ 1773 ddc_i2c.valid = false; 1774 hpd.hpd = RADEON_HPD_NONE; 1775 radeon_add_legacy_encoder(dev, 1776 radeon_get_encoder_enum(dev, 1777 ATOM_DEVICE_TV1_SUPPORT, 1778 2), 1779 ATOM_DEVICE_TV1_SUPPORT); 1780 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1781 DRM_MODE_CONNECTOR_SVIDEO, 1782 &ddc_i2c, 1783 CONNECTOR_OBJECT_ID_SVIDEO, 1784 &hpd); 1785 break; 1786 case CT_POWERBOOK_VGA: 1787 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1788 rdev->mode_info.connector_table); 1789 /* LVDS */ 1790 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1791 hpd.hpd = RADEON_HPD_NONE; 1792 radeon_add_legacy_encoder(dev, 1793 radeon_get_encoder_enum(dev, 1794 ATOM_DEVICE_LCD1_SUPPORT, 1795 0), 1796 ATOM_DEVICE_LCD1_SUPPORT); 1797 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1798 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1799 CONNECTOR_OBJECT_ID_LVDS, 1800 &hpd); 1801 /* VGA - primary dac */ 1802 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1803 hpd.hpd = RADEON_HPD_NONE; 1804 radeon_add_legacy_encoder(dev, 1805 radeon_get_encoder_enum(dev, 1806 ATOM_DEVICE_CRT1_SUPPORT, 1807 1), 1808 ATOM_DEVICE_CRT1_SUPPORT); 1809 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1810 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1811 CONNECTOR_OBJECT_ID_VGA, 1812 &hpd); 1813 /* TV - TV DAC */ 1814 ddc_i2c.valid = false; 1815 hpd.hpd = RADEON_HPD_NONE; 1816 radeon_add_legacy_encoder(dev, 1817 radeon_get_encoder_enum(dev, 1818 ATOM_DEVICE_TV1_SUPPORT, 1819 2), 1820 ATOM_DEVICE_TV1_SUPPORT); 1821 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1822 DRM_MODE_CONNECTOR_SVIDEO, 1823 &ddc_i2c, 1824 CONNECTOR_OBJECT_ID_SVIDEO, 1825 &hpd); 1826 break; 1827 case CT_MINI_EXTERNAL: 1828 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1829 rdev->mode_info.connector_table); 1830 /* DVI-I - tv dac, ext tmds */ 1831 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1832 hpd.hpd = RADEON_HPD_2; /* ??? */ 1833 radeon_add_legacy_encoder(dev, 1834 radeon_get_encoder_enum(dev, 1835 ATOM_DEVICE_DFP2_SUPPORT, 1836 0), 1837 ATOM_DEVICE_DFP2_SUPPORT); 1838 radeon_add_legacy_encoder(dev, 1839 radeon_get_encoder_enum(dev, 1840 ATOM_DEVICE_CRT2_SUPPORT, 1841 2), 1842 ATOM_DEVICE_CRT2_SUPPORT); 1843 /* XXX are any DL? */ 1844 radeon_add_legacy_connector(dev, 0, 1845 ATOM_DEVICE_DFP2_SUPPORT | 1846 ATOM_DEVICE_CRT2_SUPPORT, 1847 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1848 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1849 &hpd); 1850 /* TV - TV DAC */ 1851 ddc_i2c.valid = false; 1852 hpd.hpd = RADEON_HPD_NONE; 1853 radeon_add_legacy_encoder(dev, 1854 radeon_get_encoder_enum(dev, 1855 ATOM_DEVICE_TV1_SUPPORT, 1856 2), 1857 ATOM_DEVICE_TV1_SUPPORT); 1858 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1859 DRM_MODE_CONNECTOR_SVIDEO, 1860 &ddc_i2c, 1861 CONNECTOR_OBJECT_ID_SVIDEO, 1862 &hpd); 1863 break; 1864 case CT_MINI_INTERNAL: 1865 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1866 rdev->mode_info.connector_table); 1867 /* DVI-I - tv dac, int tmds */ 1868 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1869 hpd.hpd = RADEON_HPD_1; /* ??? */ 1870 radeon_add_legacy_encoder(dev, 1871 radeon_get_encoder_enum(dev, 1872 ATOM_DEVICE_DFP1_SUPPORT, 1873 0), 1874 ATOM_DEVICE_DFP1_SUPPORT); 1875 radeon_add_legacy_encoder(dev, 1876 radeon_get_encoder_enum(dev, 1877 ATOM_DEVICE_CRT2_SUPPORT, 1878 2), 1879 ATOM_DEVICE_CRT2_SUPPORT); 1880 radeon_add_legacy_connector(dev, 0, 1881 ATOM_DEVICE_DFP1_SUPPORT | 1882 ATOM_DEVICE_CRT2_SUPPORT, 1883 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1884 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1885 &hpd); 1886 /* TV - TV DAC */ 1887 ddc_i2c.valid = false; 1888 hpd.hpd = RADEON_HPD_NONE; 1889 radeon_add_legacy_encoder(dev, 1890 radeon_get_encoder_enum(dev, 1891 ATOM_DEVICE_TV1_SUPPORT, 1892 2), 1893 ATOM_DEVICE_TV1_SUPPORT); 1894 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1895 DRM_MODE_CONNECTOR_SVIDEO, 1896 &ddc_i2c, 1897 CONNECTOR_OBJECT_ID_SVIDEO, 1898 &hpd); 1899 break; 1900 case CT_IMAC_G5_ISIGHT: 1901 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1902 rdev->mode_info.connector_table); 1903 /* DVI-D - int tmds */ 1904 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1905 hpd.hpd = RADEON_HPD_1; /* ??? */ 1906 radeon_add_legacy_encoder(dev, 1907 radeon_get_encoder_enum(dev, 1908 ATOM_DEVICE_DFP1_SUPPORT, 1909 0), 1910 ATOM_DEVICE_DFP1_SUPPORT); 1911 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1912 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1913 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1914 &hpd); 1915 /* VGA - tv dac */ 1916 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1917 hpd.hpd = RADEON_HPD_NONE; 1918 radeon_add_legacy_encoder(dev, 1919 radeon_get_encoder_enum(dev, 1920 ATOM_DEVICE_CRT2_SUPPORT, 1921 2), 1922 ATOM_DEVICE_CRT2_SUPPORT); 1923 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1924 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1925 CONNECTOR_OBJECT_ID_VGA, 1926 &hpd); 1927 /* TV - TV DAC */ 1928 ddc_i2c.valid = false; 1929 hpd.hpd = RADEON_HPD_NONE; 1930 radeon_add_legacy_encoder(dev, 1931 radeon_get_encoder_enum(dev, 1932 ATOM_DEVICE_TV1_SUPPORT, 1933 2), 1934 ATOM_DEVICE_TV1_SUPPORT); 1935 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1936 DRM_MODE_CONNECTOR_SVIDEO, 1937 &ddc_i2c, 1938 CONNECTOR_OBJECT_ID_SVIDEO, 1939 &hpd); 1940 break; 1941 case CT_EMAC: 1942 DRM_INFO("Connector Table: %d (emac)\n", 1943 rdev->mode_info.connector_table); 1944 /* VGA - primary dac */ 1945 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1946 hpd.hpd = RADEON_HPD_NONE; 1947 radeon_add_legacy_encoder(dev, 1948 radeon_get_encoder_enum(dev, 1949 ATOM_DEVICE_CRT1_SUPPORT, 1950 1), 1951 ATOM_DEVICE_CRT1_SUPPORT); 1952 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1953 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1954 CONNECTOR_OBJECT_ID_VGA, 1955 &hpd); 1956 /* VGA - tv dac */ 1957 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1958 hpd.hpd = RADEON_HPD_NONE; 1959 radeon_add_legacy_encoder(dev, 1960 radeon_get_encoder_enum(dev, 1961 ATOM_DEVICE_CRT2_SUPPORT, 1962 2), 1963 ATOM_DEVICE_CRT2_SUPPORT); 1964 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1965 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1966 CONNECTOR_OBJECT_ID_VGA, 1967 &hpd); 1968 /* TV - TV DAC */ 1969 ddc_i2c.valid = false; 1970 hpd.hpd = RADEON_HPD_NONE; 1971 radeon_add_legacy_encoder(dev, 1972 radeon_get_encoder_enum(dev, 1973 ATOM_DEVICE_TV1_SUPPORT, 1974 2), 1975 ATOM_DEVICE_TV1_SUPPORT); 1976 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1977 DRM_MODE_CONNECTOR_SVIDEO, 1978 &ddc_i2c, 1979 CONNECTOR_OBJECT_ID_SVIDEO, 1980 &hpd); 1981 break; 1982 case CT_RN50_POWER: 1983 DRM_INFO("Connector Table: %d (rn50-power)\n", 1984 rdev->mode_info.connector_table); 1985 /* VGA - primary dac */ 1986 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1987 hpd.hpd = RADEON_HPD_NONE; 1988 radeon_add_legacy_encoder(dev, 1989 radeon_get_encoder_enum(dev, 1990 ATOM_DEVICE_CRT1_SUPPORT, 1991 1), 1992 ATOM_DEVICE_CRT1_SUPPORT); 1993 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1994 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1995 CONNECTOR_OBJECT_ID_VGA, 1996 &hpd); 1997 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1998 hpd.hpd = RADEON_HPD_NONE; 1999 radeon_add_legacy_encoder(dev, 2000 radeon_get_encoder_enum(dev, 2001 ATOM_DEVICE_CRT2_SUPPORT, 2002 2), 2003 ATOM_DEVICE_CRT2_SUPPORT); 2004 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 2005 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2006 CONNECTOR_OBJECT_ID_VGA, 2007 &hpd); 2008 break; 2009 case CT_MAC_X800: 2010 DRM_INFO("Connector Table: %d (mac x800)\n", 2011 rdev->mode_info.connector_table); 2012 /* DVI - primary dac, internal tmds */ 2013 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2014 hpd.hpd = RADEON_HPD_1; /* ??? */ 2015 radeon_add_legacy_encoder(dev, 2016 radeon_get_encoder_enum(dev, 2017 ATOM_DEVICE_DFP1_SUPPORT, 2018 0), 2019 ATOM_DEVICE_DFP1_SUPPORT); 2020 radeon_add_legacy_encoder(dev, 2021 radeon_get_encoder_enum(dev, 2022 ATOM_DEVICE_CRT1_SUPPORT, 2023 1), 2024 ATOM_DEVICE_CRT1_SUPPORT); 2025 radeon_add_legacy_connector(dev, 0, 2026 ATOM_DEVICE_DFP1_SUPPORT | 2027 ATOM_DEVICE_CRT1_SUPPORT, 2028 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2029 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2030 &hpd); 2031 /* DVI - tv dac, dvo */ 2032 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2033 hpd.hpd = RADEON_HPD_2; /* ??? */ 2034 radeon_add_legacy_encoder(dev, 2035 radeon_get_encoder_enum(dev, 2036 ATOM_DEVICE_DFP2_SUPPORT, 2037 0), 2038 ATOM_DEVICE_DFP2_SUPPORT); 2039 radeon_add_legacy_encoder(dev, 2040 radeon_get_encoder_enum(dev, 2041 ATOM_DEVICE_CRT2_SUPPORT, 2042 2), 2043 ATOM_DEVICE_CRT2_SUPPORT); 2044 radeon_add_legacy_connector(dev, 1, 2045 ATOM_DEVICE_DFP2_SUPPORT | 2046 ATOM_DEVICE_CRT2_SUPPORT, 2047 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2048 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2049 &hpd); 2050 break; 2051 case CT_MAC_G5_9600: 2052 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2053 rdev->mode_info.connector_table); 2054 /* DVI - tv dac, dvo */ 2055 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2056 hpd.hpd = RADEON_HPD_1; /* ??? */ 2057 radeon_add_legacy_encoder(dev, 2058 radeon_get_encoder_enum(dev, 2059 ATOM_DEVICE_DFP2_SUPPORT, 2060 0), 2061 ATOM_DEVICE_DFP2_SUPPORT); 2062 radeon_add_legacy_encoder(dev, 2063 radeon_get_encoder_enum(dev, 2064 ATOM_DEVICE_CRT2_SUPPORT, 2065 2), 2066 ATOM_DEVICE_CRT2_SUPPORT); 2067 radeon_add_legacy_connector(dev, 0, 2068 ATOM_DEVICE_DFP2_SUPPORT | 2069 ATOM_DEVICE_CRT2_SUPPORT, 2070 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2071 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2072 &hpd); 2073 /* ADC - primary dac, internal tmds */ 2074 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2075 hpd.hpd = RADEON_HPD_2; /* ??? */ 2076 radeon_add_legacy_encoder(dev, 2077 radeon_get_encoder_enum(dev, 2078 ATOM_DEVICE_DFP1_SUPPORT, 2079 0), 2080 ATOM_DEVICE_DFP1_SUPPORT); 2081 radeon_add_legacy_encoder(dev, 2082 radeon_get_encoder_enum(dev, 2083 ATOM_DEVICE_CRT1_SUPPORT, 2084 1), 2085 ATOM_DEVICE_CRT1_SUPPORT); 2086 radeon_add_legacy_connector(dev, 1, 2087 ATOM_DEVICE_DFP1_SUPPORT | 2088 ATOM_DEVICE_CRT1_SUPPORT, 2089 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2090 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2091 &hpd); 2092 /* TV - TV DAC */ 2093 ddc_i2c.valid = false; 2094 hpd.hpd = RADEON_HPD_NONE; 2095 radeon_add_legacy_encoder(dev, 2096 radeon_get_encoder_enum(dev, 2097 ATOM_DEVICE_TV1_SUPPORT, 2098 2), 2099 ATOM_DEVICE_TV1_SUPPORT); 2100 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2101 DRM_MODE_CONNECTOR_SVIDEO, 2102 &ddc_i2c, 2103 CONNECTOR_OBJECT_ID_SVIDEO, 2104 &hpd); 2105 break; 2106 case CT_SAM440EP: 2107 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2108 rdev->mode_info.connector_table); 2109 /* LVDS */ 2110 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2111 hpd.hpd = RADEON_HPD_NONE; 2112 radeon_add_legacy_encoder(dev, 2113 radeon_get_encoder_enum(dev, 2114 ATOM_DEVICE_LCD1_SUPPORT, 2115 0), 2116 ATOM_DEVICE_LCD1_SUPPORT); 2117 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2118 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2119 CONNECTOR_OBJECT_ID_LVDS, 2120 &hpd); 2121 /* DVI-I - secondary dac, int tmds */ 2122 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2123 hpd.hpd = RADEON_HPD_1; /* ??? */ 2124 radeon_add_legacy_encoder(dev, 2125 radeon_get_encoder_enum(dev, 2126 ATOM_DEVICE_DFP1_SUPPORT, 2127 0), 2128 ATOM_DEVICE_DFP1_SUPPORT); 2129 radeon_add_legacy_encoder(dev, 2130 radeon_get_encoder_enum(dev, 2131 ATOM_DEVICE_CRT2_SUPPORT, 2132 2), 2133 ATOM_DEVICE_CRT2_SUPPORT); 2134 radeon_add_legacy_connector(dev, 1, 2135 ATOM_DEVICE_DFP1_SUPPORT | 2136 ATOM_DEVICE_CRT2_SUPPORT, 2137 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2138 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2139 &hpd); 2140 /* VGA - primary dac */ 2141 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2142 hpd.hpd = RADEON_HPD_NONE; 2143 radeon_add_legacy_encoder(dev, 2144 radeon_get_encoder_enum(dev, 2145 ATOM_DEVICE_CRT1_SUPPORT, 2146 1), 2147 ATOM_DEVICE_CRT1_SUPPORT); 2148 radeon_add_legacy_connector(dev, 2, 2149 ATOM_DEVICE_CRT1_SUPPORT, 2150 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2151 CONNECTOR_OBJECT_ID_VGA, 2152 &hpd); 2153 /* TV - TV DAC */ 2154 ddc_i2c.valid = false; 2155 hpd.hpd = RADEON_HPD_NONE; 2156 radeon_add_legacy_encoder(dev, 2157 radeon_get_encoder_enum(dev, 2158 ATOM_DEVICE_TV1_SUPPORT, 2159 2), 2160 ATOM_DEVICE_TV1_SUPPORT); 2161 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2162 DRM_MODE_CONNECTOR_SVIDEO, 2163 &ddc_i2c, 2164 CONNECTOR_OBJECT_ID_SVIDEO, 2165 &hpd); 2166 break; 2167 case CT_MAC_G4_SILVER: 2168 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2169 rdev->mode_info.connector_table); 2170 /* DVI-I - tv dac, int tmds */ 2171 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2172 hpd.hpd = RADEON_HPD_1; /* ??? */ 2173 radeon_add_legacy_encoder(dev, 2174 radeon_get_encoder_enum(dev, 2175 ATOM_DEVICE_DFP1_SUPPORT, 2176 0), 2177 ATOM_DEVICE_DFP1_SUPPORT); 2178 radeon_add_legacy_encoder(dev, 2179 radeon_get_encoder_enum(dev, 2180 ATOM_DEVICE_CRT2_SUPPORT, 2181 2), 2182 ATOM_DEVICE_CRT2_SUPPORT); 2183 radeon_add_legacy_connector(dev, 0, 2184 ATOM_DEVICE_DFP1_SUPPORT | 2185 ATOM_DEVICE_CRT2_SUPPORT, 2186 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2187 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2188 &hpd); 2189 /* VGA - primary dac */ 2190 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2191 hpd.hpd = RADEON_HPD_NONE; 2192 radeon_add_legacy_encoder(dev, 2193 radeon_get_encoder_enum(dev, 2194 ATOM_DEVICE_CRT1_SUPPORT, 2195 1), 2196 ATOM_DEVICE_CRT1_SUPPORT); 2197 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2198 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2199 CONNECTOR_OBJECT_ID_VGA, 2200 &hpd); 2201 /* TV - TV DAC */ 2202 ddc_i2c.valid = false; 2203 hpd.hpd = RADEON_HPD_NONE; 2204 radeon_add_legacy_encoder(dev, 2205 radeon_get_encoder_enum(dev, 2206 ATOM_DEVICE_TV1_SUPPORT, 2207 2), 2208 ATOM_DEVICE_TV1_SUPPORT); 2209 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2210 DRM_MODE_CONNECTOR_SVIDEO, 2211 &ddc_i2c, 2212 CONNECTOR_OBJECT_ID_SVIDEO, 2213 &hpd); 2214 break; 2215 default: 2216 DRM_INFO("Connector table: %d (invalid)\n", 2217 rdev->mode_info.connector_table); 2218 return false; 2219 } 2220 2221 radeon_link_encoder_connector(dev); 2222 2223 return true; 2224 } 2225 2226 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2227 int bios_index, 2228 enum radeon_combios_connector 2229 *legacy_connector, 2230 struct radeon_i2c_bus_rec *ddc_i2c, 2231 struct radeon_hpd *hpd) 2232 { 2233 2234 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2235 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2236 if (dev->pdev->device == 0x515e && 2237 dev->pdev->subsystem_vendor == 0x1014) { 2238 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2239 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2240 return false; 2241 } 2242 2243 /* X300 card with extra non-existent DVI port */ 2244 if (dev->pdev->device == 0x5B60 && 2245 dev->pdev->subsystem_vendor == 0x17af && 2246 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2247 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2248 return false; 2249 } 2250 2251 return true; 2252 } 2253 2254 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2255 { 2256 /* Acer 5102 has non-existent TV port */ 2257 if (dev->pdev->device == 0x5975 && 2258 dev->pdev->subsystem_vendor == 0x1025 && 2259 dev->pdev->subsystem_device == 0x009f) 2260 return false; 2261 2262 /* HP dc5750 has non-existent TV port */ 2263 if (dev->pdev->device == 0x5974 && 2264 dev->pdev->subsystem_vendor == 0x103c && 2265 dev->pdev->subsystem_device == 0x280a) 2266 return false; 2267 2268 /* MSI S270 has non-existent TV port */ 2269 if (dev->pdev->device == 0x5955 && 2270 dev->pdev->subsystem_vendor == 0x1462 && 2271 dev->pdev->subsystem_device == 0x0131) 2272 return false; 2273 2274 return true; 2275 } 2276 2277 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2278 { 2279 struct radeon_device *rdev = dev->dev_private; 2280 uint32_t ext_tmds_info; 2281 2282 if (rdev->flags & RADEON_IS_IGP) { 2283 if (is_dvi_d) 2284 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2285 else 2286 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2287 } 2288 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2289 if (ext_tmds_info) { 2290 uint8_t rev = RBIOS8(ext_tmds_info); 2291 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2292 if (rev >= 3) { 2293 if (is_dvi_d) 2294 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2295 else 2296 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2297 } else { 2298 if (flags & 1) { 2299 if (is_dvi_d) 2300 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2301 else 2302 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2303 } 2304 } 2305 } 2306 if (is_dvi_d) 2307 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2308 else 2309 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2310 } 2311 2312 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2313 { 2314 struct radeon_device *rdev = dev->dev_private; 2315 uint32_t conn_info, entry, devices; 2316 uint16_t tmp, connector_object_id; 2317 enum radeon_combios_ddc ddc_type; 2318 enum radeon_combios_connector connector; 2319 int i = 0; 2320 struct radeon_i2c_bus_rec ddc_i2c; 2321 struct radeon_hpd hpd; 2322 2323 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2324 if (conn_info) { 2325 for (i = 0; i < 4; i++) { 2326 entry = conn_info + 2 + i * 2; 2327 2328 if (!RBIOS16(entry)) 2329 break; 2330 2331 tmp = RBIOS16(entry); 2332 2333 connector = (tmp >> 12) & 0xf; 2334 2335 ddc_type = (tmp >> 8) & 0xf; 2336 if (ddc_type == 5) 2337 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2338 else 2339 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2340 2341 switch (connector) { 2342 case CONNECTOR_PROPRIETARY_LEGACY: 2343 case CONNECTOR_DVI_I_LEGACY: 2344 case CONNECTOR_DVI_D_LEGACY: 2345 if ((tmp >> 4) & 0x1) 2346 hpd.hpd = RADEON_HPD_2; 2347 else 2348 hpd.hpd = RADEON_HPD_1; 2349 break; 2350 default: 2351 hpd.hpd = RADEON_HPD_NONE; 2352 break; 2353 } 2354 2355 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2356 &ddc_i2c, &hpd)) 2357 continue; 2358 2359 switch (connector) { 2360 case CONNECTOR_PROPRIETARY_LEGACY: 2361 if ((tmp >> 4) & 0x1) 2362 devices = ATOM_DEVICE_DFP2_SUPPORT; 2363 else 2364 devices = ATOM_DEVICE_DFP1_SUPPORT; 2365 radeon_add_legacy_encoder(dev, 2366 radeon_get_encoder_enum 2367 (dev, devices, 0), 2368 devices); 2369 radeon_add_legacy_connector(dev, i, devices, 2370 legacy_connector_convert 2371 [connector], 2372 &ddc_i2c, 2373 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2374 &hpd); 2375 break; 2376 case CONNECTOR_CRT_LEGACY: 2377 if (tmp & 0x1) { 2378 devices = ATOM_DEVICE_CRT2_SUPPORT; 2379 radeon_add_legacy_encoder(dev, 2380 radeon_get_encoder_enum 2381 (dev, 2382 ATOM_DEVICE_CRT2_SUPPORT, 2383 2), 2384 ATOM_DEVICE_CRT2_SUPPORT); 2385 } else { 2386 devices = ATOM_DEVICE_CRT1_SUPPORT; 2387 radeon_add_legacy_encoder(dev, 2388 radeon_get_encoder_enum 2389 (dev, 2390 ATOM_DEVICE_CRT1_SUPPORT, 2391 1), 2392 ATOM_DEVICE_CRT1_SUPPORT); 2393 } 2394 radeon_add_legacy_connector(dev, 2395 i, 2396 devices, 2397 legacy_connector_convert 2398 [connector], 2399 &ddc_i2c, 2400 CONNECTOR_OBJECT_ID_VGA, 2401 &hpd); 2402 break; 2403 case CONNECTOR_DVI_I_LEGACY: 2404 devices = 0; 2405 if (tmp & 0x1) { 2406 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2407 radeon_add_legacy_encoder(dev, 2408 radeon_get_encoder_enum 2409 (dev, 2410 ATOM_DEVICE_CRT2_SUPPORT, 2411 2), 2412 ATOM_DEVICE_CRT2_SUPPORT); 2413 } else { 2414 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2415 radeon_add_legacy_encoder(dev, 2416 radeon_get_encoder_enum 2417 (dev, 2418 ATOM_DEVICE_CRT1_SUPPORT, 2419 1), 2420 ATOM_DEVICE_CRT1_SUPPORT); 2421 } 2422 /* RV100 board with external TDMS bit mis-set. 2423 * Actually uses internal TMDS, clear the bit. 2424 */ 2425 if (dev->pdev->device == 0x5159 && 2426 dev->pdev->subsystem_vendor == 0x1014 && 2427 dev->pdev->subsystem_device == 0x029A) { 2428 tmp &= ~(1 << 4); 2429 } 2430 if ((tmp >> 4) & 0x1) { 2431 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2432 radeon_add_legacy_encoder(dev, 2433 radeon_get_encoder_enum 2434 (dev, 2435 ATOM_DEVICE_DFP2_SUPPORT, 2436 0), 2437 ATOM_DEVICE_DFP2_SUPPORT); 2438 connector_object_id = combios_check_dl_dvi(dev, 0); 2439 } else { 2440 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2441 radeon_add_legacy_encoder(dev, 2442 radeon_get_encoder_enum 2443 (dev, 2444 ATOM_DEVICE_DFP1_SUPPORT, 2445 0), 2446 ATOM_DEVICE_DFP1_SUPPORT); 2447 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2448 } 2449 radeon_add_legacy_connector(dev, 2450 i, 2451 devices, 2452 legacy_connector_convert 2453 [connector], 2454 &ddc_i2c, 2455 connector_object_id, 2456 &hpd); 2457 break; 2458 case CONNECTOR_DVI_D_LEGACY: 2459 if ((tmp >> 4) & 0x1) { 2460 devices = ATOM_DEVICE_DFP2_SUPPORT; 2461 connector_object_id = combios_check_dl_dvi(dev, 1); 2462 } else { 2463 devices = ATOM_DEVICE_DFP1_SUPPORT; 2464 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2465 } 2466 radeon_add_legacy_encoder(dev, 2467 radeon_get_encoder_enum 2468 (dev, devices, 0), 2469 devices); 2470 radeon_add_legacy_connector(dev, i, devices, 2471 legacy_connector_convert 2472 [connector], 2473 &ddc_i2c, 2474 connector_object_id, 2475 &hpd); 2476 break; 2477 case CONNECTOR_CTV_LEGACY: 2478 case CONNECTOR_STV_LEGACY: 2479 radeon_add_legacy_encoder(dev, 2480 radeon_get_encoder_enum 2481 (dev, 2482 ATOM_DEVICE_TV1_SUPPORT, 2483 2), 2484 ATOM_DEVICE_TV1_SUPPORT); 2485 radeon_add_legacy_connector(dev, i, 2486 ATOM_DEVICE_TV1_SUPPORT, 2487 legacy_connector_convert 2488 [connector], 2489 &ddc_i2c, 2490 CONNECTOR_OBJECT_ID_SVIDEO, 2491 &hpd); 2492 break; 2493 default: 2494 DRM_ERROR("Unknown connector type: %d\n", 2495 connector); 2496 continue; 2497 } 2498 2499 } 2500 } else { 2501 uint16_t tmds_info = 2502 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2503 if (tmds_info) { 2504 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2505 2506 radeon_add_legacy_encoder(dev, 2507 radeon_get_encoder_enum(dev, 2508 ATOM_DEVICE_CRT1_SUPPORT, 2509 1), 2510 ATOM_DEVICE_CRT1_SUPPORT); 2511 radeon_add_legacy_encoder(dev, 2512 radeon_get_encoder_enum(dev, 2513 ATOM_DEVICE_DFP1_SUPPORT, 2514 0), 2515 ATOM_DEVICE_DFP1_SUPPORT); 2516 2517 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2518 hpd.hpd = RADEON_HPD_1; 2519 radeon_add_legacy_connector(dev, 2520 0, 2521 ATOM_DEVICE_CRT1_SUPPORT | 2522 ATOM_DEVICE_DFP1_SUPPORT, 2523 DRM_MODE_CONNECTOR_DVII, 2524 &ddc_i2c, 2525 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2526 &hpd); 2527 } else { 2528 uint16_t crt_info = 2529 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2530 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2531 if (crt_info) { 2532 radeon_add_legacy_encoder(dev, 2533 radeon_get_encoder_enum(dev, 2534 ATOM_DEVICE_CRT1_SUPPORT, 2535 1), 2536 ATOM_DEVICE_CRT1_SUPPORT); 2537 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2538 hpd.hpd = RADEON_HPD_NONE; 2539 radeon_add_legacy_connector(dev, 2540 0, 2541 ATOM_DEVICE_CRT1_SUPPORT, 2542 DRM_MODE_CONNECTOR_VGA, 2543 &ddc_i2c, 2544 CONNECTOR_OBJECT_ID_VGA, 2545 &hpd); 2546 } else { 2547 DRM_DEBUG_KMS("No connector info found\n"); 2548 return false; 2549 } 2550 } 2551 } 2552 2553 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2554 uint16_t lcd_info = 2555 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2556 if (lcd_info) { 2557 uint16_t lcd_ddc_info = 2558 combios_get_table_offset(dev, 2559 COMBIOS_LCD_DDC_INFO_TABLE); 2560 2561 radeon_add_legacy_encoder(dev, 2562 radeon_get_encoder_enum(dev, 2563 ATOM_DEVICE_LCD1_SUPPORT, 2564 0), 2565 ATOM_DEVICE_LCD1_SUPPORT); 2566 2567 if (lcd_ddc_info) { 2568 ddc_type = RBIOS8(lcd_ddc_info + 2); 2569 switch (ddc_type) { 2570 case DDC_LCD: 2571 ddc_i2c = 2572 combios_setup_i2c_bus(rdev, 2573 DDC_LCD, 2574 RBIOS32(lcd_ddc_info + 3), 2575 RBIOS32(lcd_ddc_info + 7)); 2576 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2577 break; 2578 case DDC_GPIO: 2579 ddc_i2c = 2580 combios_setup_i2c_bus(rdev, 2581 DDC_GPIO, 2582 RBIOS32(lcd_ddc_info + 3), 2583 RBIOS32(lcd_ddc_info + 7)); 2584 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2585 break; 2586 default: 2587 ddc_i2c = 2588 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2589 break; 2590 } 2591 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2592 } else 2593 ddc_i2c.valid = false; 2594 2595 hpd.hpd = RADEON_HPD_NONE; 2596 radeon_add_legacy_connector(dev, 2597 5, 2598 ATOM_DEVICE_LCD1_SUPPORT, 2599 DRM_MODE_CONNECTOR_LVDS, 2600 &ddc_i2c, 2601 CONNECTOR_OBJECT_ID_LVDS, 2602 &hpd); 2603 } 2604 } 2605 2606 /* check TV table */ 2607 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2608 uint32_t tv_info = 2609 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2610 if (tv_info) { 2611 if (RBIOS8(tv_info + 6) == 'T') { 2612 if (radeon_apply_legacy_tv_quirks(dev)) { 2613 hpd.hpd = RADEON_HPD_NONE; 2614 ddc_i2c.valid = false; 2615 radeon_add_legacy_encoder(dev, 2616 radeon_get_encoder_enum 2617 (dev, 2618 ATOM_DEVICE_TV1_SUPPORT, 2619 2), 2620 ATOM_DEVICE_TV1_SUPPORT); 2621 radeon_add_legacy_connector(dev, 6, 2622 ATOM_DEVICE_TV1_SUPPORT, 2623 DRM_MODE_CONNECTOR_SVIDEO, 2624 &ddc_i2c, 2625 CONNECTOR_OBJECT_ID_SVIDEO, 2626 &hpd); 2627 } 2628 } 2629 } 2630 } 2631 2632 radeon_link_encoder_connector(dev); 2633 2634 return true; 2635 } 2636 2637 static const char *thermal_controller_names[] = { 2638 "NONE", 2639 "lm63", 2640 "adm1032", 2641 }; 2642 2643 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2644 { 2645 struct drm_device *dev = rdev->ddev; 2646 u16 offset, misc, misc2 = 0; 2647 u8 rev, tmp; 2648 int state_index = 0; 2649 struct radeon_i2c_bus_rec i2c_bus; 2650 2651 rdev->pm.default_power_state_index = -1; 2652 2653 /* allocate 2 power states */ 2654 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state), 2655 GFP_KERNEL); 2656 if (rdev->pm.power_state) { 2657 /* allocate 1 clock mode per state */ 2658 rdev->pm.power_state[0].clock_info = 2659 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2660 GFP_KERNEL); 2661 rdev->pm.power_state[1].clock_info = 2662 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2663 GFP_KERNEL); 2664 if (!rdev->pm.power_state[0].clock_info || 2665 !rdev->pm.power_state[1].clock_info) 2666 goto pm_failed; 2667 } else 2668 goto pm_failed; 2669 2670 /* check for a thermal chip */ 2671 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2672 if (offset) { 2673 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2674 2675 rev = RBIOS8(offset); 2676 2677 if (rev == 0) { 2678 thermal_controller = RBIOS8(offset + 3); 2679 gpio = RBIOS8(offset + 4) & 0x3f; 2680 i2c_addr = RBIOS8(offset + 5); 2681 } else if (rev == 1) { 2682 thermal_controller = RBIOS8(offset + 4); 2683 gpio = RBIOS8(offset + 5) & 0x3f; 2684 i2c_addr = RBIOS8(offset + 6); 2685 } else if (rev == 2) { 2686 thermal_controller = RBIOS8(offset + 4); 2687 gpio = RBIOS8(offset + 5) & 0x3f; 2688 i2c_addr = RBIOS8(offset + 6); 2689 clk_bit = RBIOS8(offset + 0xa); 2690 data_bit = RBIOS8(offset + 0xb); 2691 } 2692 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2693 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2694 thermal_controller_names[thermal_controller], 2695 i2c_addr >> 1); 2696 if (gpio == DDC_LCD) { 2697 /* MM i2c */ 2698 i2c_bus.valid = true; 2699 i2c_bus.hw_capable = true; 2700 i2c_bus.mm_i2c = true; 2701 i2c_bus.i2c_id = 0xa0; 2702 } else if (gpio == DDC_GPIO) 2703 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2704 else 2705 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2706 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2707 if (rdev->pm.i2c_bus) { 2708 struct i2c_board_info info = { }; 2709 const char *name = thermal_controller_names[thermal_controller]; 2710 info.addr = i2c_addr >> 1; 2711 strlcpy(info.type, name, sizeof(info.type)); 2712 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2713 } 2714 } 2715 } else { 2716 /* boards with a thermal chip, but no overdrive table */ 2717 2718 /* Asus 9600xt has an f75375 on the monid bus */ 2719 if ((dev->pdev->device == 0x4152) && 2720 (dev->pdev->subsystem_vendor == 0x1043) && 2721 (dev->pdev->subsystem_device == 0xc002)) { 2722 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2723 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2724 if (rdev->pm.i2c_bus) { 2725 struct i2c_board_info info = { }; 2726 const char *name = "f75375"; 2727 info.addr = 0x28; 2728 strlcpy(info.type, name, sizeof(info.type)); 2729 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2730 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2731 name, info.addr); 2732 } 2733 } 2734 } 2735 2736 if (rdev->flags & RADEON_IS_MOBILITY) { 2737 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2738 if (offset) { 2739 rev = RBIOS8(offset); 2740 /* power mode 0 tends to be the only valid one */ 2741 rdev->pm.power_state[state_index].num_clock_modes = 1; 2742 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2743 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2744 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2745 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2746 goto default_mode; 2747 rdev->pm.power_state[state_index].type = 2748 POWER_STATE_TYPE_BATTERY; 2749 misc = RBIOS16(offset + 0x5 + 0x0); 2750 if (rev > 4) 2751 misc2 = RBIOS16(offset + 0x5 + 0xe); 2752 rdev->pm.power_state[state_index].misc = misc; 2753 rdev->pm.power_state[state_index].misc2 = misc2; 2754 if (misc & 0x4) { 2755 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2756 if (misc & 0x8) 2757 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2758 true; 2759 else 2760 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2761 false; 2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2763 if (rev < 6) { 2764 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2765 RBIOS16(offset + 0x5 + 0xb) * 4; 2766 tmp = RBIOS8(offset + 0x5 + 0xd); 2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2768 } else { 2769 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2770 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2771 if (entries && voltage_table_offset) { 2772 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2773 RBIOS16(voltage_table_offset) * 4; 2774 tmp = RBIOS8(voltage_table_offset + 0x2); 2775 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2776 } else 2777 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2778 } 2779 switch ((misc2 & 0x700) >> 8) { 2780 case 0: 2781 default: 2782 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2783 break; 2784 case 1: 2785 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2786 break; 2787 case 2: 2788 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2789 break; 2790 case 3: 2791 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2792 break; 2793 case 4: 2794 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2795 break; 2796 } 2797 } else 2798 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2799 if (rev > 6) 2800 rdev->pm.power_state[state_index].pcie_lanes = 2801 RBIOS8(offset + 0x5 + 0x10); 2802 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2803 state_index++; 2804 } else { 2805 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2806 } 2807 } else { 2808 /* XXX figure out some good default low power mode for desktop cards */ 2809 } 2810 2811 default_mode: 2812 /* add the default mode */ 2813 rdev->pm.power_state[state_index].type = 2814 POWER_STATE_TYPE_DEFAULT; 2815 rdev->pm.power_state[state_index].num_clock_modes = 1; 2816 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2817 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2818 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2819 if ((state_index > 0) && 2820 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2821 rdev->pm.power_state[state_index].clock_info[0].voltage = 2822 rdev->pm.power_state[0].clock_info[0].voltage; 2823 else 2824 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2825 rdev->pm.power_state[state_index].pcie_lanes = 16; 2826 rdev->pm.power_state[state_index].flags = 0; 2827 rdev->pm.default_power_state_index = state_index; 2828 rdev->pm.num_power_states = state_index + 1; 2829 2830 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2831 rdev->pm.current_clock_mode_index = 0; 2832 return; 2833 2834 pm_failed: 2835 rdev->pm.default_power_state_index = state_index; 2836 rdev->pm.num_power_states = 0; 2837 2838 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2839 rdev->pm.current_clock_mode_index = 0; 2840 } 2841 2842 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2843 { 2844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2845 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2846 2847 if (!tmds) 2848 return; 2849 2850 switch (tmds->dvo_chip) { 2851 case DVO_SIL164: 2852 /* sil 164 */ 2853 radeon_i2c_put_byte(tmds->i2c_bus, 2854 tmds->slave_addr, 2855 0x08, 0x30); 2856 radeon_i2c_put_byte(tmds->i2c_bus, 2857 tmds->slave_addr, 2858 0x09, 0x00); 2859 radeon_i2c_put_byte(tmds->i2c_bus, 2860 tmds->slave_addr, 2861 0x0a, 0x90); 2862 radeon_i2c_put_byte(tmds->i2c_bus, 2863 tmds->slave_addr, 2864 0x0c, 0x89); 2865 radeon_i2c_put_byte(tmds->i2c_bus, 2866 tmds->slave_addr, 2867 0x08, 0x3b); 2868 break; 2869 case DVO_SIL1178: 2870 /* sil 1178 - untested */ 2871 /* 2872 * 0x0f, 0x44 2873 * 0x0f, 0x4c 2874 * 0x0e, 0x01 2875 * 0x0a, 0x80 2876 * 0x09, 0x30 2877 * 0x0c, 0xc9 2878 * 0x0d, 0x70 2879 * 0x08, 0x32 2880 * 0x08, 0x33 2881 */ 2882 break; 2883 default: 2884 break; 2885 } 2886 2887 } 2888 2889 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2890 { 2891 struct drm_device *dev = encoder->dev; 2892 struct radeon_device *rdev = dev->dev_private; 2893 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2894 uint16_t offset; 2895 uint8_t blocks, slave_addr, rev; 2896 uint32_t index, id; 2897 uint32_t reg, val, and_mask, or_mask; 2898 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2899 2900 if (!tmds) 2901 return false; 2902 2903 if (rdev->flags & RADEON_IS_IGP) { 2904 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2905 rev = RBIOS8(offset); 2906 if (offset) { 2907 rev = RBIOS8(offset); 2908 if (rev > 1) { 2909 blocks = RBIOS8(offset + 3); 2910 index = offset + 4; 2911 while (blocks > 0) { 2912 id = RBIOS16(index); 2913 index += 2; 2914 switch (id >> 13) { 2915 case 0: 2916 reg = (id & 0x1fff) * 4; 2917 val = RBIOS32(index); 2918 index += 4; 2919 WREG32(reg, val); 2920 break; 2921 case 2: 2922 reg = (id & 0x1fff) * 4; 2923 and_mask = RBIOS32(index); 2924 index += 4; 2925 or_mask = RBIOS32(index); 2926 index += 4; 2927 val = RREG32(reg); 2928 val = (val & and_mask) | or_mask; 2929 WREG32(reg, val); 2930 break; 2931 case 3: 2932 val = RBIOS16(index); 2933 index += 2; 2934 udelay(val); 2935 break; 2936 case 4: 2937 val = RBIOS16(index); 2938 index += 2; 2939 mdelay(val); 2940 break; 2941 case 6: 2942 slave_addr = id & 0xff; 2943 slave_addr >>= 1; /* 7 bit addressing */ 2944 index++; 2945 reg = RBIOS8(index); 2946 index++; 2947 val = RBIOS8(index); 2948 index++; 2949 radeon_i2c_put_byte(tmds->i2c_bus, 2950 slave_addr, 2951 reg, val); 2952 break; 2953 default: 2954 DRM_ERROR("Unknown id %d\n", id >> 13); 2955 break; 2956 } 2957 blocks--; 2958 } 2959 return true; 2960 } 2961 } 2962 } else { 2963 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2964 if (offset) { 2965 index = offset + 10; 2966 id = RBIOS16(index); 2967 while (id != 0xffff) { 2968 index += 2; 2969 switch (id >> 13) { 2970 case 0: 2971 reg = (id & 0x1fff) * 4; 2972 val = RBIOS32(index); 2973 WREG32(reg, val); 2974 break; 2975 case 2: 2976 reg = (id & 0x1fff) * 4; 2977 and_mask = RBIOS32(index); 2978 index += 4; 2979 or_mask = RBIOS32(index); 2980 index += 4; 2981 val = RREG32(reg); 2982 val = (val & and_mask) | or_mask; 2983 WREG32(reg, val); 2984 break; 2985 case 4: 2986 val = RBIOS16(index); 2987 index += 2; 2988 udelay(val); 2989 break; 2990 case 5: 2991 reg = id & 0x1fff; 2992 and_mask = RBIOS32(index); 2993 index += 4; 2994 or_mask = RBIOS32(index); 2995 index += 4; 2996 val = RREG32_PLL(reg); 2997 val = (val & and_mask) | or_mask; 2998 WREG32_PLL(reg, val); 2999 break; 3000 case 6: 3001 reg = id & 0x1fff; 3002 val = RBIOS8(index); 3003 index += 1; 3004 radeon_i2c_put_byte(tmds->i2c_bus, 3005 tmds->slave_addr, 3006 reg, val); 3007 break; 3008 default: 3009 DRM_ERROR("Unknown id %d\n", id >> 13); 3010 break; 3011 } 3012 id = RBIOS16(index); 3013 } 3014 return true; 3015 } 3016 } 3017 return false; 3018 } 3019 3020 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3021 { 3022 struct radeon_device *rdev = dev->dev_private; 3023 3024 if (offset) { 3025 while (RBIOS16(offset)) { 3026 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3027 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3028 uint32_t val, and_mask, or_mask; 3029 uint32_t tmp; 3030 3031 offset += 2; 3032 switch (cmd) { 3033 case 0: 3034 val = RBIOS32(offset); 3035 offset += 4; 3036 WREG32(addr, val); 3037 break; 3038 case 1: 3039 val = RBIOS32(offset); 3040 offset += 4; 3041 WREG32(addr, val); 3042 break; 3043 case 2: 3044 and_mask = RBIOS32(offset); 3045 offset += 4; 3046 or_mask = RBIOS32(offset); 3047 offset += 4; 3048 tmp = RREG32(addr); 3049 tmp &= and_mask; 3050 tmp |= or_mask; 3051 WREG32(addr, tmp); 3052 break; 3053 case 3: 3054 and_mask = RBIOS32(offset); 3055 offset += 4; 3056 or_mask = RBIOS32(offset); 3057 offset += 4; 3058 tmp = RREG32(addr); 3059 tmp &= and_mask; 3060 tmp |= or_mask; 3061 WREG32(addr, tmp); 3062 break; 3063 case 4: 3064 val = RBIOS16(offset); 3065 offset += 2; 3066 udelay(val); 3067 break; 3068 case 5: 3069 val = RBIOS16(offset); 3070 offset += 2; 3071 switch (addr) { 3072 case 8: 3073 while (val--) { 3074 if (! 3075 (RREG32_PLL 3076 (RADEON_CLK_PWRMGT_CNTL) & 3077 RADEON_MC_BUSY)) 3078 break; 3079 } 3080 break; 3081 case 9: 3082 while (val--) { 3083 if ((RREG32(RADEON_MC_STATUS) & 3084 RADEON_MC_IDLE)) 3085 break; 3086 } 3087 break; 3088 default: 3089 break; 3090 } 3091 break; 3092 default: 3093 break; 3094 } 3095 } 3096 } 3097 } 3098 3099 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3100 { 3101 struct radeon_device *rdev = dev->dev_private; 3102 3103 if (offset) { 3104 while (RBIOS8(offset)) { 3105 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3106 uint8_t addr = (RBIOS8(offset) & 0x3f); 3107 uint32_t val, shift, tmp; 3108 uint32_t and_mask, or_mask; 3109 3110 offset++; 3111 switch (cmd) { 3112 case 0: 3113 val = RBIOS32(offset); 3114 offset += 4; 3115 WREG32_PLL(addr, val); 3116 break; 3117 case 1: 3118 shift = RBIOS8(offset) * 8; 3119 offset++; 3120 and_mask = RBIOS8(offset) << shift; 3121 and_mask |= ~(0xff << shift); 3122 offset++; 3123 or_mask = RBIOS8(offset) << shift; 3124 offset++; 3125 tmp = RREG32_PLL(addr); 3126 tmp &= and_mask; 3127 tmp |= or_mask; 3128 WREG32_PLL(addr, tmp); 3129 break; 3130 case 2: 3131 case 3: 3132 tmp = 1000; 3133 switch (addr) { 3134 case 1: 3135 udelay(150); 3136 break; 3137 case 2: 3138 mdelay(1); 3139 break; 3140 case 3: 3141 while (tmp--) { 3142 if (! 3143 (RREG32_PLL 3144 (RADEON_CLK_PWRMGT_CNTL) & 3145 RADEON_MC_BUSY)) 3146 break; 3147 } 3148 break; 3149 case 4: 3150 while (tmp--) { 3151 if (RREG32_PLL 3152 (RADEON_CLK_PWRMGT_CNTL) & 3153 RADEON_DLL_READY) 3154 break; 3155 } 3156 break; 3157 case 5: 3158 tmp = 3159 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3160 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3161 #if 0 3162 uint32_t mclk_cntl = 3163 RREG32_PLL 3164 (RADEON_MCLK_CNTL); 3165 mclk_cntl &= 0xffff0000; 3166 /*mclk_cntl |= 0x00001111;*//* ??? */ 3167 WREG32_PLL(RADEON_MCLK_CNTL, 3168 mclk_cntl); 3169 mdelay(10); 3170 #endif 3171 WREG32_PLL 3172 (RADEON_CLK_PWRMGT_CNTL, 3173 tmp & 3174 ~RADEON_CG_NO1_DEBUG_0); 3175 mdelay(10); 3176 } 3177 break; 3178 default: 3179 break; 3180 } 3181 break; 3182 default: 3183 break; 3184 } 3185 } 3186 } 3187 } 3188 3189 static void combios_parse_ram_reset_table(struct drm_device *dev, 3190 uint16_t offset) 3191 { 3192 struct radeon_device *rdev = dev->dev_private; 3193 uint32_t tmp; 3194 3195 if (offset) { 3196 uint8_t val = RBIOS8(offset); 3197 while (val != 0xff) { 3198 offset++; 3199 3200 if (val == 0x0f) { 3201 uint32_t channel_complete_mask; 3202 3203 if (ASIC_IS_R300(rdev)) 3204 channel_complete_mask = 3205 R300_MEM_PWRUP_COMPLETE; 3206 else 3207 channel_complete_mask = 3208 RADEON_MEM_PWRUP_COMPLETE; 3209 tmp = 20000; 3210 while (tmp--) { 3211 if ((RREG32(RADEON_MEM_STR_CNTL) & 3212 channel_complete_mask) == 3213 channel_complete_mask) 3214 break; 3215 } 3216 } else { 3217 uint32_t or_mask = RBIOS16(offset); 3218 offset += 2; 3219 3220 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3221 tmp &= RADEON_SDRAM_MODE_MASK; 3222 tmp |= or_mask; 3223 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3224 3225 or_mask = val << 24; 3226 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3227 tmp &= RADEON_B3MEM_RESET_MASK; 3228 tmp |= or_mask; 3229 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3230 } 3231 val = RBIOS8(offset); 3232 } 3233 } 3234 } 3235 3236 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3237 int mem_addr_mapping) 3238 { 3239 struct radeon_device *rdev = dev->dev_private; 3240 uint32_t mem_cntl; 3241 uint32_t mem_size; 3242 uint32_t addr = 0; 3243 3244 mem_cntl = RREG32(RADEON_MEM_CNTL); 3245 if (mem_cntl & RV100_HALF_MODE) 3246 ram /= 2; 3247 mem_size = ram; 3248 mem_cntl &= ~(0xff << 8); 3249 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3250 WREG32(RADEON_MEM_CNTL, mem_cntl); 3251 RREG32(RADEON_MEM_CNTL); 3252 3253 /* sdram reset ? */ 3254 3255 /* something like this???? */ 3256 while (ram--) { 3257 addr = ram * 1024 * 1024; 3258 /* write to each page */ 3259 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3260 /* read back and verify */ 3261 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3262 return 0; 3263 } 3264 3265 return mem_size; 3266 } 3267 3268 static void combios_write_ram_size(struct drm_device *dev) 3269 { 3270 struct radeon_device *rdev = dev->dev_private; 3271 uint8_t rev; 3272 uint16_t offset; 3273 uint32_t mem_size = 0; 3274 uint32_t mem_cntl = 0; 3275 3276 /* should do something smarter here I guess... */ 3277 if (rdev->flags & RADEON_IS_IGP) 3278 return; 3279 3280 /* first check detected mem table */ 3281 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3282 if (offset) { 3283 rev = RBIOS8(offset); 3284 if (rev < 3) { 3285 mem_cntl = RBIOS32(offset + 1); 3286 mem_size = RBIOS16(offset + 5); 3287 if ((rdev->family < CHIP_R200) && 3288 !ASIC_IS_RN50(rdev)) 3289 WREG32(RADEON_MEM_CNTL, mem_cntl); 3290 } 3291 } 3292 3293 if (!mem_size) { 3294 offset = 3295 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3296 if (offset) { 3297 rev = RBIOS8(offset - 1); 3298 if (rev < 1) { 3299 if ((rdev->family < CHIP_R200) 3300 && !ASIC_IS_RN50(rdev)) { 3301 int ram = 0; 3302 int mem_addr_mapping = 0; 3303 3304 while (RBIOS8(offset)) { 3305 ram = RBIOS8(offset); 3306 mem_addr_mapping = 3307 RBIOS8(offset + 1); 3308 if (mem_addr_mapping != 0x25) 3309 ram *= 2; 3310 mem_size = 3311 combios_detect_ram(dev, ram, 3312 mem_addr_mapping); 3313 if (mem_size) 3314 break; 3315 offset += 2; 3316 } 3317 } else 3318 mem_size = RBIOS8(offset); 3319 } else { 3320 mem_size = RBIOS8(offset); 3321 mem_size *= 2; /* convert to MB */ 3322 } 3323 } 3324 } 3325 3326 mem_size *= (1024 * 1024); /* convert to bytes */ 3327 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3328 } 3329 3330 void radeon_combios_asic_init(struct drm_device *dev) 3331 { 3332 struct radeon_device *rdev = dev->dev_private; 3333 uint16_t table; 3334 3335 /* port hardcoded mac stuff from radeonfb */ 3336 if (rdev->bios == NULL) 3337 return; 3338 3339 /* ASIC INIT 1 */ 3340 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3341 if (table) 3342 combios_parse_mmio_table(dev, table); 3343 3344 /* PLL INIT */ 3345 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3346 if (table) 3347 combios_parse_pll_table(dev, table); 3348 3349 /* ASIC INIT 2 */ 3350 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3351 if (table) 3352 combios_parse_mmio_table(dev, table); 3353 3354 if (!(rdev->flags & RADEON_IS_IGP)) { 3355 /* ASIC INIT 4 */ 3356 table = 3357 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3358 if (table) 3359 combios_parse_mmio_table(dev, table); 3360 3361 /* RAM RESET */ 3362 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3363 if (table) 3364 combios_parse_ram_reset_table(dev, table); 3365 3366 /* ASIC INIT 3 */ 3367 table = 3368 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3369 if (table) 3370 combios_parse_mmio_table(dev, table); 3371 3372 /* write CONFIG_MEMSIZE */ 3373 combios_write_ram_size(dev); 3374 } 3375 3376 /* quirk for rs4xx HP nx6125 laptop to make it resume 3377 * - it hangs on resume inside the dynclk 1 table. 3378 */ 3379 if (rdev->family == CHIP_RS480 && 3380 rdev->pdev->subsystem_vendor == 0x103c && 3381 rdev->pdev->subsystem_device == 0x308b) 3382 return; 3383 3384 /* quirk for rs4xx HP dv5000 laptop to make it resume 3385 * - it hangs on resume inside the dynclk 1 table. 3386 */ 3387 if (rdev->family == CHIP_RS480 && 3388 rdev->pdev->subsystem_vendor == 0x103c && 3389 rdev->pdev->subsystem_device == 0x30a4) 3390 return; 3391 3392 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3393 * - it hangs on resume inside the dynclk 1 table. 3394 */ 3395 if (rdev->family == CHIP_RS480 && 3396 rdev->pdev->subsystem_vendor == 0x103c && 3397 rdev->pdev->subsystem_device == 0x30ae) 3398 return; 3399 3400 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume 3401 * - it hangs on resume inside the dynclk 1 table. 3402 */ 3403 if (rdev->family == CHIP_RS480 && 3404 rdev->pdev->subsystem_vendor == 0x103c && 3405 rdev->pdev->subsystem_device == 0x280a) 3406 return; 3407 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3408 * - it hangs on resume inside the dynclk 1 table. 3409 */ 3410 if (rdev->family == CHIP_RS400 && 3411 rdev->pdev->subsystem_vendor == 0x1179 && 3412 rdev->pdev->subsystem_device == 0xff31) 3413 return; 3414 3415 /* DYN CLK 1 */ 3416 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3417 if (table) 3418 combios_parse_pll_table(dev, table); 3419 3420 } 3421 3422 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3423 { 3424 struct radeon_device *rdev = dev->dev_private; 3425 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3426 3427 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3428 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3429 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3430 3431 /* let the bios control the backlight */ 3432 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3433 3434 /* tell the bios not to handle mode switching */ 3435 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3436 RADEON_ACC_MODE_CHANGE); 3437 3438 /* tell the bios a driver is loaded */ 3439 bios_7_scratch |= RADEON_DRV_LOADED; 3440 3441 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3442 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3443 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3444 } 3445 3446 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3447 { 3448 struct drm_device *dev = encoder->dev; 3449 struct radeon_device *rdev = dev->dev_private; 3450 uint32_t bios_6_scratch; 3451 3452 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3453 3454 if (lock) 3455 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3456 else 3457 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3458 3459 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3460 } 3461 3462 void 3463 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3464 struct drm_encoder *encoder, 3465 bool connected) 3466 { 3467 struct drm_device *dev = connector->dev; 3468 struct radeon_device *rdev = dev->dev_private; 3469 struct radeon_connector *radeon_connector = 3470 to_radeon_connector(connector); 3471 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3472 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3473 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3474 3475 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3476 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3477 if (connected) { 3478 DRM_DEBUG_KMS("TV1 connected\n"); 3479 /* fix me */ 3480 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3481 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3482 bios_5_scratch |= RADEON_TV1_ON; 3483 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3484 } else { 3485 DRM_DEBUG_KMS("TV1 disconnected\n"); 3486 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3487 bios_5_scratch &= ~RADEON_TV1_ON; 3488 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3489 } 3490 } 3491 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3492 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3493 if (connected) { 3494 DRM_DEBUG_KMS("LCD1 connected\n"); 3495 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3496 bios_5_scratch |= RADEON_LCD1_ON; 3497 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3498 } else { 3499 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3500 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3501 bios_5_scratch &= ~RADEON_LCD1_ON; 3502 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3503 } 3504 } 3505 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3506 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3507 if (connected) { 3508 DRM_DEBUG_KMS("CRT1 connected\n"); 3509 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3510 bios_5_scratch |= RADEON_CRT1_ON; 3511 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3512 } else { 3513 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3514 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3515 bios_5_scratch &= ~RADEON_CRT1_ON; 3516 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3517 } 3518 } 3519 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3520 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3521 if (connected) { 3522 DRM_DEBUG_KMS("CRT2 connected\n"); 3523 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3524 bios_5_scratch |= RADEON_CRT2_ON; 3525 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3526 } else { 3527 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3528 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3529 bios_5_scratch &= ~RADEON_CRT2_ON; 3530 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3531 } 3532 } 3533 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3534 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3535 if (connected) { 3536 DRM_DEBUG_KMS("DFP1 connected\n"); 3537 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3538 bios_5_scratch |= RADEON_DFP1_ON; 3539 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3540 } else { 3541 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3542 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3543 bios_5_scratch &= ~RADEON_DFP1_ON; 3544 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3545 } 3546 } 3547 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3548 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3549 if (connected) { 3550 DRM_DEBUG_KMS("DFP2 connected\n"); 3551 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3552 bios_5_scratch |= RADEON_DFP2_ON; 3553 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3554 } else { 3555 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3556 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3557 bios_5_scratch &= ~RADEON_DFP2_ON; 3558 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3559 } 3560 } 3561 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3562 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3563 } 3564 3565 void 3566 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3567 { 3568 struct drm_device *dev = encoder->dev; 3569 struct radeon_device *rdev = dev->dev_private; 3570 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3571 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3572 3573 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3574 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3575 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3576 } 3577 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3578 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3579 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3580 } 3581 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3582 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3583 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3584 } 3585 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3586 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3587 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3588 } 3589 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3590 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3591 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3592 } 3593 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3594 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3595 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3596 } 3597 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3598 } 3599 3600 void 3601 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3602 { 3603 struct drm_device *dev = encoder->dev; 3604 struct radeon_device *rdev = dev->dev_private; 3605 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3606 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3607 3608 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3609 if (on) 3610 bios_6_scratch |= RADEON_TV_DPMS_ON; 3611 else 3612 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3613 } 3614 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3615 if (on) 3616 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3617 else 3618 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3619 } 3620 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3621 if (on) 3622 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3623 else 3624 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3625 } 3626 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3627 if (on) 3628 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3629 else 3630 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3631 } 3632 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3633 } 3634
Indexes created Sat Sep 20 22:09:52 GMT 2025