1 /* $NetBSD: radeon_i2c.c,v 1.8 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_i2c.c,v 1.8 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <linux/export.h> 33 #include <linux/pci.h> 34 35 #include <drm/drm_device.h> 36 #include <drm/drm_edid.h> 37 #include <drm/radeon_drm.h> 38 39 #include "radeon.h" 40 #include "atom.h" 41 42 #include <linux/nbsd-namespace.h> 43 44 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 45 struct i2c_msg *msgs, int num); 46 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 47 48 /** 49 * radeon_ddc_probe 50 * 51 */ 52 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 53 { 54 u8 out = 0x0; 55 u8 buf[8]; 56 int ret; 57 struct i2c_msg msgs[] = { 58 { 59 .addr = DDC_ADDR, 60 .flags = 0, 61 .len = 1, 62 .buf = &out, 63 }, 64 { 65 .addr = DDC_ADDR, 66 .flags = I2C_M_RD, 67 .len = 8, 68 .buf = buf, 69 } 70 }; 71 72 /* on hw with routers, select right port */ 73 if (radeon_connector->router.ddc_valid) 74 radeon_router_select_ddc_port(radeon_connector); 75 76 if (use_aux) { 77 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 78 } else { 79 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 80 } 81 82 if (ret != 2) 83 /* Couldn't find an accessible DDC on this connector */ 84 return false; 85 /* Probe also for valid EDID header 86 * EDID header starts with: 87 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 88 * Only the first 6 bytes must be valid as 89 * drm_edid_block_valid() can fix the last 2 bytes */ 90 if (drm_edid_header_is_valid(buf) < 6) { 91 /* Couldn't find an accessible EDID on this 92 * connector */ 93 return false; 94 } 95 return true; 96 } 97 98 /* bit banging i2c */ 99 100 static int pre_xfer(struct i2c_adapter *i2c_adap) 101 { 102 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 103 struct radeon_device *rdev = i2c->dev->dev_private; 104 struct radeon_i2c_bus_rec *rec = &i2c->rec; 105 uint32_t temp; 106 107 mutex_lock(&i2c->mutex); 108 109 /* RV410 appears to have a bug where the hw i2c in reset 110 * holds the i2c port in a bad state - switch hw i2c away before 111 * doing DDC - do this for all r200s/r300s/r400s for safety sake 112 */ 113 if (rec->hw_capable) { 114 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 115 u32 reg; 116 117 if (rdev->family >= CHIP_RV350) 118 reg = RADEON_GPIO_MONID; 119 else if ((rdev->family == CHIP_R300) || 120 (rdev->family == CHIP_R350)) 121 reg = RADEON_GPIO_DVI_DDC; 122 else 123 reg = RADEON_GPIO_CRT2_DDC; 124 125 mutex_lock(&rdev->dc_hw_i2c_mutex); 126 if (rec->a_clk_reg == reg) { 127 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 128 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 129 } else { 130 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 131 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 132 } 133 mutex_unlock(&rdev->dc_hw_i2c_mutex); 134 } 135 } 136 137 /* switch the pads to ddc mode */ 138 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 139 temp = RREG32(rec->mask_clk_reg); 140 temp &= ~(1 << 16); 141 WREG32(rec->mask_clk_reg, temp); 142 } 143 144 /* clear the output pin values */ 145 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 146 WREG32(rec->a_clk_reg, temp); 147 148 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 149 WREG32(rec->a_data_reg, temp); 150 151 /* set the pins to input */ 152 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 153 WREG32(rec->en_clk_reg, temp); 154 155 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 156 WREG32(rec->en_data_reg, temp); 157 158 /* mask the gpio pins for software use */ 159 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 160 WREG32(rec->mask_clk_reg, temp); 161 temp = RREG32(rec->mask_clk_reg); 162 163 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 164 WREG32(rec->mask_data_reg, temp); 165 temp = RREG32(rec->mask_data_reg); 166 167 return 0; 168 } 169 170 static void post_xfer(struct i2c_adapter *i2c_adap) 171 { 172 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 173 struct radeon_device *rdev = i2c->dev->dev_private; 174 struct radeon_i2c_bus_rec *rec = &i2c->rec; 175 uint32_t temp; 176 177 /* unmask the gpio pins for software use */ 178 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 179 WREG32(rec->mask_clk_reg, temp); 180 temp = RREG32(rec->mask_clk_reg); 181 182 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 183 WREG32(rec->mask_data_reg, temp); 184 temp = RREG32(rec->mask_data_reg); 185 186 mutex_unlock(&i2c->mutex); 187 } 188 189 static int get_clock(void *i2c_priv) 190 { 191 struct radeon_i2c_chan *i2c = i2c_priv; 192 struct radeon_device *rdev = i2c->dev->dev_private; 193 struct radeon_i2c_bus_rec *rec = &i2c->rec; 194 uint32_t val; 195 196 /* read the value off the pin */ 197 val = RREG32(rec->y_clk_reg); 198 val &= rec->y_clk_mask; 199 200 return (val != 0); 201 } 202 203 204 static int get_data(void *i2c_priv) 205 { 206 struct radeon_i2c_chan *i2c = i2c_priv; 207 struct radeon_device *rdev = i2c->dev->dev_private; 208 struct radeon_i2c_bus_rec *rec = &i2c->rec; 209 uint32_t val; 210 211 /* read the value off the pin */ 212 val = RREG32(rec->y_data_reg); 213 val &= rec->y_data_mask; 214 215 return (val != 0); 216 } 217 218 static void set_clock(void *i2c_priv, int clock) 219 { 220 struct radeon_i2c_chan *i2c = i2c_priv; 221 struct radeon_device *rdev = i2c->dev->dev_private; 222 struct radeon_i2c_bus_rec *rec = &i2c->rec; 223 uint32_t val; 224 225 /* set pin direction */ 226 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 227 val |= clock ? 0 : rec->en_clk_mask; 228 WREG32(rec->en_clk_reg, val); 229 } 230 231 static void set_data(void *i2c_priv, int data) 232 { 233 struct radeon_i2c_chan *i2c = i2c_priv; 234 struct radeon_device *rdev = i2c->dev->dev_private; 235 struct radeon_i2c_bus_rec *rec = &i2c->rec; 236 uint32_t val; 237 238 /* set pin direction */ 239 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 240 val |= data ? 0 : rec->en_data_mask; 241 WREG32(rec->en_data_reg, val); 242 } 243 244 /* hw i2c */ 245 246 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 247 { 248 u32 sclk = rdev->pm.current_sclk; 249 u32 prescale = 0; 250 u32 nm; 251 u8 n, m, loop; 252 int i2c_clock; 253 254 switch (rdev->family) { 255 case CHIP_R100: 256 case CHIP_RV100: 257 case CHIP_RS100: 258 case CHIP_RV200: 259 case CHIP_RS200: 260 case CHIP_R200: 261 case CHIP_RV250: 262 case CHIP_RS300: 263 case CHIP_RV280: 264 case CHIP_R300: 265 case CHIP_R350: 266 case CHIP_RV350: 267 i2c_clock = 60; 268 nm = (sclk * 10) / (i2c_clock * 4); 269 for (loop = 1; loop < 255; loop++) { 270 if ((nm / loop) < loop) 271 break; 272 } 273 n = loop - 1; 274 m = loop - 2; 275 prescale = m | (n << 8); 276 break; 277 case CHIP_RV380: 278 case CHIP_RS400: 279 case CHIP_RS480: 280 case CHIP_R420: 281 case CHIP_R423: 282 case CHIP_RV410: 283 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 284 break; 285 case CHIP_RS600: 286 case CHIP_RS690: 287 case CHIP_RS740: 288 /* todo */ 289 break; 290 case CHIP_RV515: 291 case CHIP_R520: 292 case CHIP_RV530: 293 case CHIP_RV560: 294 case CHIP_RV570: 295 case CHIP_R580: 296 i2c_clock = 50; 297 if (rdev->family == CHIP_R520) 298 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 299 else 300 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 301 break; 302 case CHIP_R600: 303 case CHIP_RV610: 304 case CHIP_RV630: 305 case CHIP_RV670: 306 /* todo */ 307 break; 308 case CHIP_RV620: 309 case CHIP_RV635: 310 case CHIP_RS780: 311 case CHIP_RS880: 312 case CHIP_RV770: 313 case CHIP_RV730: 314 case CHIP_RV710: 315 case CHIP_RV740: 316 /* todo */ 317 break; 318 case CHIP_CEDAR: 319 case CHIP_REDWOOD: 320 case CHIP_JUNIPER: 321 case CHIP_CYPRESS: 322 case CHIP_HEMLOCK: 323 /* todo */ 324 break; 325 default: 326 DRM_ERROR("i2c: unhandled radeon chip\n"); 327 break; 328 } 329 return prescale; 330 } 331 332 333 /* hw i2c engine for r1xx-4xx hardware 334 * hw can buffer up to 15 bytes 335 */ 336 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 337 struct i2c_msg *msgs, int num) 338 { 339 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 340 struct radeon_device *rdev = i2c->dev->dev_private; 341 struct radeon_i2c_bus_rec *rec = &i2c->rec; 342 struct i2c_msg *p; 343 int i, j, k, ret = num; 344 u32 prescale; 345 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 346 u32 tmp, reg; 347 348 mutex_lock(&rdev->dc_hw_i2c_mutex); 349 /* take the pm lock since we need a constant sclk */ 350 mutex_lock(&rdev->pm.mutex); 351 352 prescale = radeon_get_i2c_prescale(rdev); 353 354 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 355 RADEON_I2C_DRIVE_EN | 356 RADEON_I2C_START | 357 RADEON_I2C_STOP | 358 RADEON_I2C_GO); 359 360 if (rdev->is_atom_bios) { 361 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 362 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 363 } 364 365 if (rec->mm_i2c) { 366 i2c_cntl_0 = RADEON_I2C_CNTL_0; 367 i2c_cntl_1 = RADEON_I2C_CNTL_1; 368 i2c_data = RADEON_I2C_DATA; 369 } else { 370 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 371 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 372 i2c_data = RADEON_DVI_I2C_DATA; 373 374 switch (rdev->family) { 375 case CHIP_R100: 376 case CHIP_RV100: 377 case CHIP_RS100: 378 case CHIP_RV200: 379 case CHIP_RS200: 380 case CHIP_RS300: 381 switch (rec->mask_clk_reg) { 382 case RADEON_GPIO_DVI_DDC: 383 /* no gpio select bit */ 384 break; 385 default: 386 DRM_ERROR("gpio not supported with hw i2c\n"); 387 ret = -EINVAL; 388 goto done; 389 } 390 break; 391 case CHIP_R200: 392 /* only bit 4 on r200 */ 393 switch (rec->mask_clk_reg) { 394 case RADEON_GPIO_DVI_DDC: 395 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 396 break; 397 case RADEON_GPIO_MONID: 398 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 399 break; 400 default: 401 DRM_ERROR("gpio not supported with hw i2c\n"); 402 ret = -EINVAL; 403 goto done; 404 } 405 break; 406 case CHIP_RV250: 407 case CHIP_RV280: 408 /* bits 3 and 4 */ 409 switch (rec->mask_clk_reg) { 410 case RADEON_GPIO_DVI_DDC: 411 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 412 break; 413 case RADEON_GPIO_VGA_DDC: 414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 415 break; 416 case RADEON_GPIO_CRT2_DDC: 417 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 418 break; 419 default: 420 DRM_ERROR("gpio not supported with hw i2c\n"); 421 ret = -EINVAL; 422 goto done; 423 } 424 break; 425 case CHIP_R300: 426 case CHIP_R350: 427 /* only bit 4 on r300/r350 */ 428 switch (rec->mask_clk_reg) { 429 case RADEON_GPIO_VGA_DDC: 430 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 431 break; 432 case RADEON_GPIO_DVI_DDC: 433 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 434 break; 435 default: 436 DRM_ERROR("gpio not supported with hw i2c\n"); 437 ret = -EINVAL; 438 goto done; 439 } 440 break; 441 case CHIP_RV350: 442 case CHIP_RV380: 443 case CHIP_R420: 444 case CHIP_R423: 445 case CHIP_RV410: 446 case CHIP_RS400: 447 case CHIP_RS480: 448 /* bits 3 and 4 */ 449 switch (rec->mask_clk_reg) { 450 case RADEON_GPIO_VGA_DDC: 451 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 452 break; 453 case RADEON_GPIO_DVI_DDC: 454 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 455 break; 456 case RADEON_GPIO_MONID: 457 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 458 break; 459 default: 460 DRM_ERROR("gpio not supported with hw i2c\n"); 461 ret = -EINVAL; 462 goto done; 463 } 464 break; 465 default: 466 DRM_ERROR("unsupported asic\n"); 467 ret = -EINVAL; 468 goto done; 469 break; 470 } 471 } 472 473 /* check for bus probe */ 474 p = &msgs[0]; 475 if ((num == 1) && (p->len == 0)) { 476 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 477 RADEON_I2C_NACK | 478 RADEON_I2C_HALT | 479 RADEON_I2C_SOFT_RST)); 480 WREG32(i2c_data, (p->addr << 1) & 0xff); 481 WREG32(i2c_data, 0); 482 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 483 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 484 RADEON_I2C_EN | 485 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 486 WREG32(i2c_cntl_0, reg); 487 for (k = 0; k < 32; k++) { 488 udelay(10); 489 tmp = RREG32(i2c_cntl_0); 490 if (tmp & RADEON_I2C_GO) 491 continue; 492 tmp = RREG32(i2c_cntl_0); 493 if (tmp & RADEON_I2C_DONE) 494 break; 495 else { 496 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 497 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 498 ret = -EIO; 499 goto done; 500 } 501 } 502 goto done; 503 } 504 505 for (i = 0; i < num; i++) { 506 p = &msgs[i]; 507 for (j = 0; j < p->len; j++) { 508 if (p->flags & I2C_M_RD) { 509 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 510 RADEON_I2C_NACK | 511 RADEON_I2C_HALT | 512 RADEON_I2C_SOFT_RST)); 513 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 514 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 515 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 516 RADEON_I2C_EN | 517 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 518 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 519 for (k = 0; k < 32; k++) { 520 udelay(10); 521 tmp = RREG32(i2c_cntl_0); 522 if (tmp & RADEON_I2C_GO) 523 continue; 524 tmp = RREG32(i2c_cntl_0); 525 if (tmp & RADEON_I2C_DONE) 526 break; 527 else { 528 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 529 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 530 ret = -EIO; 531 goto done; 532 } 533 } 534 p->buf[j] = RREG32(i2c_data) & 0xff; 535 } else { 536 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 537 RADEON_I2C_NACK | 538 RADEON_I2C_HALT | 539 RADEON_I2C_SOFT_RST)); 540 WREG32(i2c_data, (p->addr << 1) & 0xff); 541 WREG32(i2c_data, p->buf[j]); 542 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 543 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 544 RADEON_I2C_EN | 545 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 546 WREG32(i2c_cntl_0, reg); 547 for (k = 0; k < 32; k++) { 548 udelay(10); 549 tmp = RREG32(i2c_cntl_0); 550 if (tmp & RADEON_I2C_GO) 551 continue; 552 tmp = RREG32(i2c_cntl_0); 553 if (tmp & RADEON_I2C_DONE) 554 break; 555 else { 556 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 557 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 558 ret = -EIO; 559 goto done; 560 } 561 } 562 } 563 } 564 } 565 566 done: 567 WREG32(i2c_cntl_0, 0); 568 WREG32(i2c_cntl_1, 0); 569 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 570 RADEON_I2C_NACK | 571 RADEON_I2C_HALT | 572 RADEON_I2C_SOFT_RST)); 573 574 if (rdev->is_atom_bios) { 575 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 576 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 577 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 578 } 579 580 mutex_unlock(&rdev->pm.mutex); 581 mutex_unlock(&rdev->dc_hw_i2c_mutex); 582 583 return ret; 584 } 585 586 /* hw i2c engine for r5xx hardware 587 * hw can buffer up to 15 bytes 588 */ 589 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 590 struct i2c_msg *msgs, int num) 591 { 592 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 593 struct radeon_device *rdev = i2c->dev->dev_private; 594 struct radeon_i2c_bus_rec *rec = &i2c->rec; 595 struct i2c_msg *p; 596 int i, j, remaining, current_count, buffer_offset, ret = num; 597 u32 prescale; 598 u32 tmp, reg; 599 u32 saved1, saved2; 600 601 mutex_lock(&rdev->dc_hw_i2c_mutex); 602 /* take the pm lock since we need a constant sclk */ 603 mutex_lock(&rdev->pm.mutex); 604 605 prescale = radeon_get_i2c_prescale(rdev); 606 607 /* clear gpio mask bits */ 608 tmp = RREG32(rec->mask_clk_reg); 609 tmp &= ~rec->mask_clk_mask; 610 WREG32(rec->mask_clk_reg, tmp); 611 tmp = RREG32(rec->mask_clk_reg); 612 613 tmp = RREG32(rec->mask_data_reg); 614 tmp &= ~rec->mask_data_mask; 615 WREG32(rec->mask_data_reg, tmp); 616 tmp = RREG32(rec->mask_data_reg); 617 618 /* clear pin values */ 619 tmp = RREG32(rec->a_clk_reg); 620 tmp &= ~rec->a_clk_mask; 621 WREG32(rec->a_clk_reg, tmp); 622 tmp = RREG32(rec->a_clk_reg); 623 624 tmp = RREG32(rec->a_data_reg); 625 tmp &= ~rec->a_data_mask; 626 WREG32(rec->a_data_reg, tmp); 627 tmp = RREG32(rec->a_data_reg); 628 629 /* set the pins to input */ 630 tmp = RREG32(rec->en_clk_reg); 631 tmp &= ~rec->en_clk_mask; 632 WREG32(rec->en_clk_reg, tmp); 633 tmp = RREG32(rec->en_clk_reg); 634 635 tmp = RREG32(rec->en_data_reg); 636 tmp &= ~rec->en_data_mask; 637 WREG32(rec->en_data_reg, tmp); 638 tmp = RREG32(rec->en_data_reg); 639 640 /* */ 641 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 642 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 643 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 644 saved2 = RREG32(0x494); 645 WREG32(0x494, saved2 | 0x1); 646 647 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 648 for (i = 0; i < 50; i++) { 649 udelay(1); 650 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 651 break; 652 } 653 if (i == 50) { 654 DRM_ERROR("failed to get i2c bus\n"); 655 ret = -EBUSY; 656 goto done; 657 } 658 659 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 660 switch (rec->mask_clk_reg) { 661 case AVIVO_DC_GPIO_DDC1_MASK: 662 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 663 break; 664 case AVIVO_DC_GPIO_DDC2_MASK: 665 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 666 break; 667 case AVIVO_DC_GPIO_DDC3_MASK: 668 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 669 break; 670 default: 671 DRM_ERROR("gpio not supported with hw i2c\n"); 672 ret = -EINVAL; 673 goto done; 674 } 675 676 /* check for bus probe */ 677 p = &msgs[0]; 678 if ((num == 1) && (p->len == 0)) { 679 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 680 AVIVO_DC_I2C_NACK | 681 AVIVO_DC_I2C_HALT)); 682 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 683 udelay(1); 684 WREG32(AVIVO_DC_I2C_RESET, 0); 685 686 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 687 WREG32(AVIVO_DC_I2C_DATA, 0); 688 689 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 690 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 691 AVIVO_DC_I2C_DATA_COUNT(1) | 692 (prescale << 16))); 693 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 694 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 695 for (j = 0; j < 200; j++) { 696 udelay(50); 697 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 698 if (tmp & AVIVO_DC_I2C_GO) 699 continue; 700 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 701 if (tmp & AVIVO_DC_I2C_DONE) 702 break; 703 else { 704 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 705 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 706 ret = -EIO; 707 goto done; 708 } 709 } 710 goto done; 711 } 712 713 for (i = 0; i < num; i++) { 714 p = &msgs[i]; 715 remaining = p->len; 716 buffer_offset = 0; 717 if (p->flags & I2C_M_RD) { 718 while (remaining) { 719 if (remaining > 15) 720 current_count = 15; 721 else 722 current_count = remaining; 723 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 724 AVIVO_DC_I2C_NACK | 725 AVIVO_DC_I2C_HALT)); 726 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 727 udelay(1); 728 WREG32(AVIVO_DC_I2C_RESET, 0); 729 730 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 731 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 732 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 733 AVIVO_DC_I2C_DATA_COUNT(current_count) | 734 (prescale << 16))); 735 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 736 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 737 for (j = 0; j < 200; j++) { 738 udelay(50); 739 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 740 if (tmp & AVIVO_DC_I2C_GO) 741 continue; 742 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 743 if (tmp & AVIVO_DC_I2C_DONE) 744 break; 745 else { 746 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 747 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 748 ret = -EIO; 749 goto done; 750 } 751 } 752 for (j = 0; j < current_count; j++) 753 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 754 remaining -= current_count; 755 buffer_offset += current_count; 756 } 757 } else { 758 while (remaining) { 759 if (remaining > 15) 760 current_count = 15; 761 else 762 current_count = remaining; 763 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 764 AVIVO_DC_I2C_NACK | 765 AVIVO_DC_I2C_HALT)); 766 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 767 udelay(1); 768 WREG32(AVIVO_DC_I2C_RESET, 0); 769 770 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 771 for (j = 0; j < current_count; j++) 772 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 773 774 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 775 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 776 AVIVO_DC_I2C_DATA_COUNT(current_count) | 777 (prescale << 16))); 778 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 779 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 780 for (j = 0; j < 200; j++) { 781 udelay(50); 782 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 783 if (tmp & AVIVO_DC_I2C_GO) 784 continue; 785 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 786 if (tmp & AVIVO_DC_I2C_DONE) 787 break; 788 else { 789 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 790 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 791 ret = -EIO; 792 goto done; 793 } 794 } 795 remaining -= current_count; 796 buffer_offset += current_count; 797 } 798 } 799 } 800 801 done: 802 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 803 AVIVO_DC_I2C_NACK | 804 AVIVO_DC_I2C_HALT)); 805 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 806 udelay(1); 807 WREG32(AVIVO_DC_I2C_RESET, 0); 808 809 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 810 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 811 WREG32(0x494, saved2); 812 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 813 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 814 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 815 816 mutex_unlock(&rdev->pm.mutex); 817 mutex_unlock(&rdev->dc_hw_i2c_mutex); 818 819 return ret; 820 } 821 822 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 823 struct i2c_msg *msgs, int num) 824 { 825 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 826 struct radeon_device *rdev = i2c->dev->dev_private; 827 struct radeon_i2c_bus_rec *rec = &i2c->rec; 828 int ret = 0; 829 830 mutex_lock(&i2c->mutex); 831 832 switch (rdev->family) { 833 case CHIP_R100: 834 case CHIP_RV100: 835 case CHIP_RS100: 836 case CHIP_RV200: 837 case CHIP_RS200: 838 case CHIP_R200: 839 case CHIP_RV250: 840 case CHIP_RS300: 841 case CHIP_RV280: 842 case CHIP_R300: 843 case CHIP_R350: 844 case CHIP_RV350: 845 case CHIP_RV380: 846 case CHIP_R420: 847 case CHIP_R423: 848 case CHIP_RV410: 849 case CHIP_RS400: 850 case CHIP_RS480: 851 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 852 break; 853 case CHIP_RS600: 854 case CHIP_RS690: 855 case CHIP_RS740: 856 /* XXX fill in hw i2c implementation */ 857 break; 858 case CHIP_RV515: 859 case CHIP_R520: 860 case CHIP_RV530: 861 case CHIP_RV560: 862 case CHIP_RV570: 863 case CHIP_R580: 864 if (rec->mm_i2c) 865 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 866 else 867 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 868 break; 869 case CHIP_R600: 870 case CHIP_RV610: 871 case CHIP_RV630: 872 case CHIP_RV670: 873 /* XXX fill in hw i2c implementation */ 874 break; 875 case CHIP_RV620: 876 case CHIP_RV635: 877 case CHIP_RS780: 878 case CHIP_RS880: 879 case CHIP_RV770: 880 case CHIP_RV730: 881 case CHIP_RV710: 882 case CHIP_RV740: 883 /* XXX fill in hw i2c implementation */ 884 break; 885 case CHIP_CEDAR: 886 case CHIP_REDWOOD: 887 case CHIP_JUNIPER: 888 case CHIP_CYPRESS: 889 case CHIP_HEMLOCK: 890 /* XXX fill in hw i2c implementation */ 891 break; 892 default: 893 DRM_ERROR("i2c: unhandled radeon chip\n"); 894 ret = -EIO; 895 break; 896 } 897 898 mutex_unlock(&i2c->mutex); 899 900 return ret; 901 } 902 903 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 904 { 905 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 906 } 907 908 static const struct i2c_algorithm radeon_i2c_algo = { 909 .master_xfer = radeon_hw_i2c_xfer, 910 .functionality = radeon_hw_i2c_func, 911 }; 912 913 static const struct i2c_algorithm radeon_atom_i2c_algo = { 914 .master_xfer = radeon_atom_hw_i2c_xfer, 915 .functionality = radeon_atom_hw_i2c_func, 916 }; 917 918 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 919 struct radeon_i2c_bus_rec *rec, 920 const char *name) 921 { 922 struct radeon_device *rdev = dev->dev_private; 923 struct radeon_i2c_chan *i2c; 924 int ret; 925 926 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 927 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 928 return NULL; 929 930 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 931 if (i2c == NULL) 932 return NULL; 933 934 i2c->rec = *rec; 935 i2c->adapter.owner = THIS_MODULE; 936 i2c->adapter.class = I2C_CLASS_DDC; 937 i2c->adapter.dev.parent = dev->dev; 938 i2c->dev = dev; 939 i2c_set_adapdata(&i2c->adapter, i2c); 940 mutex_init(&i2c->mutex); 941 if (rec->mm_i2c || 942 (rec->hw_capable && 943 radeon_hw_i2c && 944 ((rdev->family <= CHIP_RS480) || 945 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 946 /* set the radeon hw i2c adapter */ 947 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 948 "Radeon i2c hw bus %s", name); 949 i2c->adapter.algo = &radeon_i2c_algo; 950 ret = i2c_add_adapter(&i2c->adapter); 951 if (ret) 952 goto out_free; 953 } else if (rec->hw_capable && 954 radeon_hw_i2c && 955 ASIC_IS_DCE3(rdev)) { 956 /* hw i2c using atom */ 957 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 958 "Radeon i2c hw bus %s", name); 959 i2c->adapter.algo = &radeon_atom_i2c_algo; 960 ret = i2c_add_adapter(&i2c->adapter); 961 if (ret) 962 goto out_free; 963 } else { 964 /* set the radeon bit adapter */ 965 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 966 "Radeon i2c bit bus %s", name); 967 i2c->adapter.algo_data = &i2c->bit; 968 i2c->bit.pre_xfer = pre_xfer; 969 i2c->bit.post_xfer = post_xfer; 970 i2c->bit.setsda = set_data; 971 i2c->bit.setscl = set_clock; 972 i2c->bit.getsda = get_data; 973 i2c->bit.getscl = get_clock; 974 i2c->bit.udelay = 10; 975 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 976 i2c->bit.data = i2c; 977 ret = i2c_bit_add_bus(&i2c->adapter); 978 if (ret) { 979 DRM_ERROR("Failed to register bit i2c %s\n", name); 980 goto out_free; 981 } 982 } 983 984 return i2c; 985 out_free: 986 mutex_destroy(&i2c->mutex); 987 kfree(i2c); 988 return NULL; 989 990 } 991 992 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 993 { 994 if (!i2c) 995 return; 996 WARN_ON(i2c->has_aux); 997 i2c_del_adapter(&i2c->adapter); 998 kfree(i2c); 999 } 1000 1001 /* Add the default buses */ 1002 void radeon_i2c_init(struct radeon_device *rdev) 1003 { 1004 if (radeon_hw_i2c) 1005 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1006 1007 if (rdev->is_atom_bios) 1008 radeon_atombios_i2c_init(rdev); 1009 else 1010 radeon_combios_i2c_init(rdev); 1011 } 1012 1013 /* remove all the buses */ 1014 void radeon_i2c_fini(struct radeon_device *rdev) 1015 { 1016 int i; 1017 1018 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1019 if (rdev->i2c_bus[i]) { 1020 radeon_i2c_destroy(rdev->i2c_bus[i]); 1021 rdev->i2c_bus[i] = NULL; 1022 } 1023 } 1024 } 1025 1026 /* Add additional buses */ 1027 void radeon_i2c_add(struct radeon_device *rdev, 1028 struct radeon_i2c_bus_rec *rec, 1029 const char *name) 1030 { 1031 struct drm_device *dev = rdev->ddev; 1032 int i; 1033 1034 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1035 if (!rdev->i2c_bus[i]) { 1036 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1037 return; 1038 } 1039 } 1040 } 1041 1042 /* looks up bus based on id */ 1043 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1044 struct radeon_i2c_bus_rec *i2c_bus) 1045 { 1046 int i; 1047 1048 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1049 if (rdev->i2c_bus[i] && 1050 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1051 return rdev->i2c_bus[i]; 1052 } 1053 } 1054 return NULL; 1055 } 1056 1057 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1058 u8 slave_addr, 1059 u8 addr, 1060 u8 *val) 1061 { 1062 u8 out_buf[2]; 1063 u8 in_buf[2]; 1064 struct i2c_msg msgs[] = { 1065 { 1066 .addr = slave_addr, 1067 .flags = 0, 1068 .len = 1, 1069 .buf = out_buf, 1070 }, 1071 { 1072 .addr = slave_addr, 1073 .flags = I2C_M_RD, 1074 .len = 1, 1075 .buf = in_buf, 1076 } 1077 }; 1078 1079 out_buf[0] = addr; 1080 out_buf[1] = 0; 1081 1082 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1083 *val = in_buf[0]; 1084 DRM_DEBUG("val = 0x%02x\n", *val); 1085 } else { 1086 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1087 addr, *val); 1088 } 1089 } 1090 1091 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1092 u8 slave_addr, 1093 u8 addr, 1094 u8 val) 1095 { 1096 uint8_t out_buf[2]; 1097 struct i2c_msg msg = { 1098 .addr = slave_addr, 1099 .flags = 0, 1100 .len = 2, 1101 .buf = out_buf, 1102 }; 1103 1104 out_buf[0] = addr; 1105 out_buf[1] = val; 1106 1107 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1108 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1109 addr, val); 1110 } 1111 1112 /* ddc router switching */ 1113 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1114 { 1115 u8 val; 1116 1117 if (!radeon_connector->router.ddc_valid) 1118 return; 1119 1120 if (!radeon_connector->router_bus) 1121 return; 1122 1123 radeon_i2c_get_byte(radeon_connector->router_bus, 1124 radeon_connector->router.i2c_addr, 1125 0x3, &val); 1126 val &= ~radeon_connector->router.ddc_mux_control_pin; 1127 radeon_i2c_put_byte(radeon_connector->router_bus, 1128 radeon_connector->router.i2c_addr, 1129 0x3, val); 1130 radeon_i2c_get_byte(radeon_connector->router_bus, 1131 radeon_connector->router.i2c_addr, 1132 0x1, &val); 1133 val &= ~radeon_connector->router.ddc_mux_control_pin; 1134 val |= radeon_connector->router.ddc_mux_state; 1135 radeon_i2c_put_byte(radeon_connector->router_bus, 1136 radeon_connector->router.i2c_addr, 1137 0x1, val); 1138 } 1139 1140 /* clock/data router switching */ 1141 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1142 { 1143 u8 val; 1144 1145 if (!radeon_connector->router.cd_valid) 1146 return; 1147 1148 if (!radeon_connector->router_bus) 1149 return; 1150 1151 radeon_i2c_get_byte(radeon_connector->router_bus, 1152 radeon_connector->router.i2c_addr, 1153 0x3, &val); 1154 val &= ~radeon_connector->router.cd_mux_control_pin; 1155 radeon_i2c_put_byte(radeon_connector->router_bus, 1156 radeon_connector->router.i2c_addr, 1157 0x3, val); 1158 radeon_i2c_get_byte(radeon_connector->router_bus, 1159 radeon_connector->router.i2c_addr, 1160 0x1, &val); 1161 val &= ~radeon_connector->router.cd_mux_control_pin; 1162 val |= radeon_connector->router.cd_mux_state; 1163 radeon_i2c_put_byte(radeon_connector->router_bus, 1164 radeon_connector->router.i2c_addr, 1165 0x1, val); 1166 } 1167 1168
Indexes created Sun Sep 21 20:09:37 GMT 2025