1 /* $NetBSD: radeon_legacy_crtc.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_crtc.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_fixed.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_vblank.h> 37 #include <drm/radeon_drm.h> 38 39 #include "atom.h" 40 #include "radeon.h" 41 42 static void radeon_overscan_setup(struct drm_crtc *crtc, 43 struct drm_display_mode *mode) 44 { 45 struct drm_device *dev = crtc->dev; 46 struct radeon_device *rdev = dev->dev_private; 47 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 48 49 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 50 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 51 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 52 } 53 54 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 55 struct drm_display_mode *mode) 56 { 57 struct drm_device *dev = crtc->dev; 58 struct radeon_device *rdev = dev->dev_private; 59 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 60 int xres = mode->hdisplay; 61 int yres = mode->vdisplay; 62 bool hscale = true, vscale = true; 63 int hsync_wid; 64 int vsync_wid; 65 int hsync_start; 66 int blank_width; 67 u32 scale, inc, crtc_more_cntl; 68 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 69 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 70 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 71 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 72 73 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 74 (RADEON_VERT_STRETCH_RESERVED | 75 RADEON_VERT_AUTO_RATIO_INC); 76 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 77 (RADEON_HORZ_FP_LOOP_STRETCH | 78 RADEON_HORZ_AUTO_RATIO_INC); 79 80 crtc_more_cntl = 0; 81 if ((rdev->family == CHIP_RS100) || 82 (rdev->family == CHIP_RS200)) { 83 /* This is to workaround the asic bug for RMX, some versions 84 of BIOS dosen't have this register initialized correctly. */ 85 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 86 } 87 88 89 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 90 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 91 92 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 93 if (!hsync_wid) 94 hsync_wid = 1; 95 hsync_start = mode->crtc_hsync_start - 8; 96 97 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 98 | ((hsync_wid & 0x3f) << 16) 99 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 100 ? RADEON_CRTC_H_SYNC_POL 101 : 0)); 102 103 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 104 | ((mode->crtc_vdisplay - 1) << 16)); 105 106 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 107 if (!vsync_wid) 108 vsync_wid = 1; 109 110 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 111 | ((vsync_wid & 0x1f) << 16) 112 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 113 ? RADEON_CRTC_V_SYNC_POL 114 : 0)); 115 116 fp_horz_vert_active = 0; 117 118 if (native_mode->hdisplay == 0 || 119 native_mode->vdisplay == 0) { 120 hscale = false; 121 vscale = false; 122 } else { 123 if (xres > native_mode->hdisplay) 124 xres = native_mode->hdisplay; 125 if (yres > native_mode->vdisplay) 126 yres = native_mode->vdisplay; 127 128 if (xres == native_mode->hdisplay) 129 hscale = false; 130 if (yres == native_mode->vdisplay) 131 vscale = false; 132 } 133 134 switch (radeon_crtc->rmx_type) { 135 case RMX_FULL: 136 case RMX_ASPECT: 137 if (!hscale) 138 fp_horz_stretch |= ((xres/8-1) << 16); 139 else { 140 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 141 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 142 / native_mode->hdisplay + 1; 143 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 144 RADEON_HORZ_STRETCH_BLEND | 145 RADEON_HORZ_STRETCH_ENABLE | 146 ((native_mode->hdisplay/8-1) << 16)); 147 } 148 149 if (!vscale) 150 fp_vert_stretch |= ((yres-1) << 12); 151 else { 152 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 153 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 154 / native_mode->vdisplay + 1; 155 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 156 RADEON_VERT_STRETCH_ENABLE | 157 RADEON_VERT_STRETCH_BLEND | 158 ((native_mode->vdisplay-1) << 12)); 159 } 160 break; 161 case RMX_CENTER: 162 fp_horz_stretch |= ((xres/8-1) << 16); 163 fp_vert_stretch |= ((yres-1) << 12); 164 165 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 166 RADEON_CRTC_AUTO_VERT_CENTER_EN); 167 168 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 169 if (blank_width > 110) 170 blank_width = 110; 171 172 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 173 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 174 175 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 176 if (!hsync_wid) 177 hsync_wid = 1; 178 179 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 180 | ((hsync_wid & 0x3f) << 16) 181 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 182 ? RADEON_CRTC_H_SYNC_POL 183 : 0)); 184 185 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 186 | ((mode->crtc_vdisplay - 1) << 16)); 187 188 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 189 if (!vsync_wid) 190 vsync_wid = 1; 191 192 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 193 | ((vsync_wid & 0x1f) << 16) 194 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 195 ? RADEON_CRTC_V_SYNC_POL 196 : 0))); 197 198 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 199 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 200 break; 201 case RMX_OFF: 202 default: 203 fp_horz_stretch |= ((xres/8-1) << 16); 204 fp_vert_stretch |= ((yres-1) << 12); 205 break; 206 } 207 208 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 209 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 210 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 211 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 212 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 213 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 214 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 215 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 216 } 217 218 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 219 { 220 struct radeon_device *rdev = dev->dev_private; 221 int i = 0; 222 223 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 224 the cause yet, but this workaround will mask the problem for now. 225 Other chips usually will pass at the very first test, so the 226 workaround shouldn't have any effect on them. */ 227 for (i = 0; 228 (i < 10000 && 229 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 230 i++); 231 } 232 233 static void radeon_pll_write_update(struct drm_device *dev) 234 { 235 struct radeon_device *rdev = dev->dev_private; 236 237 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 238 239 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 240 RADEON_PPLL_ATOMIC_UPDATE_W, 241 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 242 } 243 244 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 245 { 246 struct radeon_device *rdev = dev->dev_private; 247 int i = 0; 248 249 250 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 251 the cause yet, but this workaround will mask the problem for now. 252 Other chips usually will pass at the very first test, so the 253 workaround shouldn't have any effect on them. */ 254 for (i = 0; 255 (i < 10000 && 256 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 257 i++); 258 } 259 260 static void radeon_pll2_write_update(struct drm_device *dev) 261 { 262 struct radeon_device *rdev = dev->dev_private; 263 264 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 265 266 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 267 RADEON_P2PLL_ATOMIC_UPDATE_W, 268 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 269 } 270 271 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 272 uint16_t fb_div) 273 { 274 unsigned int vcoFreq; 275 276 if (!ref_div) 277 return 1; 278 279 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 280 281 /* 282 * This is horribly crude: the VCO frequency range is divided into 283 * 3 parts, each part having a fixed PLL gain value. 284 */ 285 if (vcoFreq >= 30000) 286 /* 287 * [300..max] MHz : 7 288 */ 289 return 7; 290 else if (vcoFreq >= 18000) 291 /* 292 * [180..300) MHz : 4 293 */ 294 return 4; 295 else 296 /* 297 * [0..180) MHz : 1 298 */ 299 return 1; 300 } 301 302 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 303 { 304 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 305 struct drm_device *dev = crtc->dev; 306 struct radeon_device *rdev = dev->dev_private; 307 uint32_t crtc_ext_cntl = 0; 308 uint32_t mask; 309 310 if (radeon_crtc->crtc_id) 311 mask = (RADEON_CRTC2_DISP_DIS | 312 RADEON_CRTC2_VSYNC_DIS | 313 RADEON_CRTC2_HSYNC_DIS | 314 RADEON_CRTC2_DISP_REQ_EN_B); 315 else 316 mask = (RADEON_CRTC_DISPLAY_DIS | 317 RADEON_CRTC_VSYNC_DIS | 318 RADEON_CRTC_HSYNC_DIS); 319 320 /* 321 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. 322 * Therefore it is set in the DAC DMPS function. 323 * This is different for GPU's with a single CRTC but a primary and a 324 * TV DAC: here it controls the single CRTC no matter where it is 325 * routed. Therefore we set it here. 326 */ 327 if (rdev->flags & RADEON_SINGLE_CRTC) 328 crtc_ext_cntl = RADEON_CRTC_CRT_ON; 329 330 switch (mode) { 331 case DRM_MODE_DPMS_ON: 332 radeon_crtc->enabled = true; 333 /* adjust pm to dpms changes BEFORE enabling crtcs */ 334 radeon_pm_compute_clocks(rdev); 335 if (radeon_crtc->crtc_id) 336 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 337 else { 338 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 339 RADEON_CRTC_DISP_REQ_EN_B)); 340 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 341 } 342 if (dev->num_crtcs > radeon_crtc->crtc_id) 343 drm_crtc_vblank_on(crtc); 344 radeon_crtc_load_lut(crtc); 345 break; 346 case DRM_MODE_DPMS_STANDBY: 347 case DRM_MODE_DPMS_SUSPEND: 348 case DRM_MODE_DPMS_OFF: 349 if (dev->num_crtcs > radeon_crtc->crtc_id) 350 drm_crtc_vblank_off(crtc); 351 if (radeon_crtc->crtc_id) 352 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 353 else { 354 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 355 RADEON_CRTC_DISP_REQ_EN_B)); 356 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); 357 } 358 radeon_crtc->enabled = false; 359 /* adjust pm to dpms changes AFTER disabling crtcs */ 360 radeon_pm_compute_clocks(rdev); 361 break; 362 } 363 } 364 365 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 366 struct drm_framebuffer *old_fb) 367 { 368 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 369 } 370 371 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 372 struct drm_framebuffer *fb, 373 int x, int y, enum mode_set_atomic state) 374 { 375 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 376 } 377 378 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 379 struct drm_framebuffer *fb, 380 int x, int y, int atomic) 381 { 382 struct drm_device *dev = crtc->dev; 383 struct radeon_device *rdev = dev->dev_private; 384 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 385 struct drm_framebuffer *target_fb; 386 struct drm_gem_object *obj; 387 struct radeon_bo *rbo; 388 uint64_t base; 389 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 390 uint32_t crtc_pitch, pitch_pixels; 391 uint32_t tiling_flags; 392 int format; 393 uint32_t gen_cntl_reg, gen_cntl_val; 394 int r; 395 396 DRM_DEBUG_KMS("\n"); 397 /* no fb bound */ 398 if (!atomic && !crtc->primary->fb) { 399 DRM_DEBUG_KMS("No FB bound\n"); 400 return 0; 401 } 402 403 if (atomic) 404 target_fb = fb; 405 else 406 target_fb = crtc->primary->fb; 407 408 switch (target_fb->format->cpp[0] * 8) { 409 case 8: 410 format = 2; 411 break; 412 case 15: /* 555 */ 413 format = 3; 414 break; 415 case 16: /* 565 */ 416 format = 4; 417 break; 418 case 24: /* RGB */ 419 format = 5; 420 break; 421 case 32: /* xRGB */ 422 format = 6; 423 break; 424 default: 425 return false; 426 } 427 428 /* Pin framebuffer & get tilling informations */ 429 obj = target_fb->obj[0]; 430 rbo = gem_to_radeon_bo(obj); 431 if (atomic) { 432 /* 433 * If you want to do this in atomic, better have it 434 * pinned ahead of time. 435 */ 436 BUG_ON(rbo->pin_count == 0); 437 base = radeon_bo_gpu_offset(rbo); 438 tiling_flags = 0; 439 goto pinned; 440 } 441 retry: 442 r = radeon_bo_reserve(rbo, false); 443 if (unlikely(r != 0)) 444 return r; 445 /* Only 27 bit offset for legacy CRTC */ 446 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 447 &base); 448 if (unlikely(r != 0)) { 449 radeon_bo_unreserve(rbo); 450 451 /* On old GPU like RN50 with little vram pining can fails because 452 * current fb is taking all space needed. So instead of unpining 453 * the old buffer after pining the new one, first unpin old one 454 * and then retry pining new one. 455 * 456 * As only master can set mode only master can pin and it is 457 * unlikely the master client will race with itself especialy 458 * on those old gpu with single crtc. 459 * 460 * We don't shutdown the display controller because new buffer 461 * will end up in same spot. 462 */ 463 if (fb && fb != crtc->primary->fb) { 464 struct radeon_bo *old_rbo; 465 unsigned long nsize, osize; 466 467 old_rbo = gem_to_radeon_bo(fb->obj[0]); 468 osize = radeon_bo_size(old_rbo); 469 nsize = radeon_bo_size(rbo); 470 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { 471 radeon_bo_unpin(old_rbo); 472 radeon_bo_unreserve(old_rbo); 473 fb = NULL; 474 goto retry; 475 } 476 } 477 return -EINVAL; 478 } 479 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 480 radeon_bo_unreserve(rbo); 481 pinned: 482 if (tiling_flags & RADEON_TILING_MICRO) 483 DRM_ERROR("trying to scanout microtiled buffer\n"); 484 485 /* if scanout was in GTT this really wouldn't work */ 486 /* crtc offset is from display base addr not FB location */ 487 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 488 489 base -= radeon_crtc->legacy_display_base_addr; 490 491 crtc_offset_cntl = 0; 492 493 pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 494 crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8, 495 target_fb->format->cpp[0] * 8 * 8); 496 crtc_pitch |= crtc_pitch << 16; 497 498 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 499 if (tiling_flags & RADEON_TILING_MACRO) { 500 if (ASIC_IS_R300(rdev)) 501 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 502 R300_CRTC_MICRO_TILE_BUFFER_DIS | 503 R300_CRTC_MACRO_TILE_EN); 504 else 505 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 506 } else { 507 if (ASIC_IS_R300(rdev)) 508 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 509 R300_CRTC_MICRO_TILE_BUFFER_DIS | 510 R300_CRTC_MACRO_TILE_EN); 511 else 512 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 513 } 514 515 if (tiling_flags & RADEON_TILING_MACRO) { 516 if (ASIC_IS_R300(rdev)) { 517 crtc_tile_x0_y0 = x | (y << 16); 518 base &= ~0x7ff; 519 } else { 520 int byteshift = target_fb->format->cpp[0] * 8 >> 4; 521 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 522 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 523 crtc_offset_cntl |= (y % 16); 524 } 525 } else { 526 int offset = y * pitch_pixels + x; 527 switch (target_fb->format->cpp[0] * 8) { 528 case 8: 529 offset *= 1; 530 break; 531 case 15: 532 case 16: 533 offset *= 2; 534 break; 535 case 24: 536 offset *= 3; 537 break; 538 case 32: 539 offset *= 4; 540 break; 541 default: 542 return false; 543 } 544 base += offset; 545 } 546 547 base &= ~7; 548 549 if (radeon_crtc->crtc_id == 1) 550 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 551 else 552 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 553 554 gen_cntl_val = RREG32(gen_cntl_reg); 555 gen_cntl_val &= ~(0xf << 8); 556 gen_cntl_val |= (format << 8); 557 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 558 WREG32(gen_cntl_reg, gen_cntl_val); 559 560 crtc_offset = (u32)base; 561 562 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 563 564 if (ASIC_IS_R300(rdev)) { 565 if (radeon_crtc->crtc_id) 566 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 567 else 568 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 569 } 570 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 571 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 572 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 573 574 if (!atomic && fb && fb != crtc->primary->fb) { 575 rbo = gem_to_radeon_bo(fb->obj[0]); 576 r = radeon_bo_reserve(rbo, false); 577 if (unlikely(r != 0)) 578 return r; 579 radeon_bo_unpin(rbo); 580 radeon_bo_unreserve(rbo); 581 } 582 583 /* Bytes per pixel may have changed */ 584 radeon_bandwidth_update(rdev); 585 586 return 0; 587 } 588 589 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 590 { 591 struct drm_device *dev = crtc->dev; 592 struct radeon_device *rdev = dev->dev_private; 593 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 594 const struct drm_framebuffer *fb = crtc->primary->fb; 595 struct drm_encoder *encoder; 596 int format; 597 int hsync_start; 598 int hsync_wid; 599 int vsync_wid; 600 uint32_t crtc_h_total_disp; 601 uint32_t crtc_h_sync_strt_wid; 602 uint32_t crtc_v_total_disp; 603 uint32_t crtc_v_sync_strt_wid; 604 bool is_tv = false; 605 606 DRM_DEBUG_KMS("\n"); 607 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 608 if (encoder->crtc == crtc) { 609 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 610 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 611 is_tv = true; 612 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 613 break; 614 } 615 } 616 } 617 618 switch (fb->format->cpp[0] * 8) { 619 case 8: 620 format = 2; 621 break; 622 case 15: /* 555 */ 623 format = 3; 624 break; 625 case 16: /* 565 */ 626 format = 4; 627 break; 628 case 24: /* RGB */ 629 format = 5; 630 break; 631 case 32: /* xRGB */ 632 format = 6; 633 break; 634 default: 635 return false; 636 } 637 638 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 639 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 640 641 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 642 if (!hsync_wid) 643 hsync_wid = 1; 644 hsync_start = mode->crtc_hsync_start - 8; 645 646 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 647 | ((hsync_wid & 0x3f) << 16) 648 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 649 ? RADEON_CRTC_H_SYNC_POL 650 : 0)); 651 652 /* This works for double scan mode. */ 653 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 654 | ((mode->crtc_vdisplay - 1) << 16)); 655 656 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 657 if (!vsync_wid) 658 vsync_wid = 1; 659 660 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 661 | ((vsync_wid & 0x1f) << 16) 662 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 663 ? RADEON_CRTC_V_SYNC_POL 664 : 0)); 665 666 if (radeon_crtc->crtc_id) { 667 uint32_t crtc2_gen_cntl; 668 uint32_t disp2_merge_cntl; 669 670 /* if TV DAC is enabled for another crtc and keep it enabled */ 671 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 672 crtc2_gen_cntl |= ((format << 8) 673 | RADEON_CRTC2_VSYNC_DIS 674 | RADEON_CRTC2_HSYNC_DIS 675 | RADEON_CRTC2_DISP_DIS 676 | RADEON_CRTC2_DISP_REQ_EN_B 677 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 678 ? RADEON_CRTC2_DBL_SCAN_EN 679 : 0) 680 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 681 ? RADEON_CRTC2_CSYNC_EN 682 : 0) 683 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 684 ? RADEON_CRTC2_INTERLACE_EN 685 : 0)); 686 687 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 688 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 689 crtc2_gen_cntl |= RADEON_CRTC2_EN; 690 691 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 692 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 693 694 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 695 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 696 697 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 698 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 699 } else { 700 uint32_t crtc_gen_cntl; 701 uint32_t crtc_ext_cntl; 702 uint32_t disp_merge_cntl; 703 704 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 705 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 706 | (format << 8) 707 | RADEON_CRTC_DISP_REQ_EN_B 708 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 709 ? RADEON_CRTC_DBL_SCAN_EN 710 : 0) 711 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 712 ? RADEON_CRTC_CSYNC_EN 713 : 0) 714 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 715 ? RADEON_CRTC_INTERLACE_EN 716 : 0)); 717 718 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 719 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 720 crtc_gen_cntl |= RADEON_CRTC_EN; 721 722 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 723 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 724 RADEON_CRTC_VSYNC_DIS | 725 RADEON_CRTC_HSYNC_DIS | 726 RADEON_CRTC_DISPLAY_DIS); 727 728 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 729 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 730 731 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 732 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 733 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 734 } 735 736 if (is_tv) 737 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 738 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 739 &crtc_v_sync_strt_wid); 740 741 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 742 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 743 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 744 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 745 746 return true; 747 } 748 749 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 750 { 751 struct drm_device *dev = crtc->dev; 752 struct radeon_device *rdev = dev->dev_private; 753 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 754 struct drm_encoder *encoder; 755 uint32_t feedback_div = 0; 756 uint32_t frac_fb_div = 0; 757 uint32_t reference_div = 0; 758 uint32_t post_divider = 0; 759 uint32_t freq = 0; 760 uint8_t pll_gain; 761 bool use_bios_divs = false; 762 /* PLL registers */ 763 uint32_t pll_ref_div = 0; 764 uint32_t pll_fb_post_div = 0; 765 uint32_t htotal_cntl = 0; 766 bool is_tv = false; 767 struct radeon_pll *pll; 768 769 struct { 770 int divider; 771 int bitvalue; 772 } *post_div, post_divs[] = { 773 /* From RAGE 128 VR/RAGE 128 GL Register 774 * Reference Manual (Technical Reference 775 * Manual P/N RRG-G04100-C Rev. 0.04), page 776 * 3-17 (PLL_DIV_[3:0]). 777 */ 778 { 1, 0 }, /* VCLK_SRC */ 779 { 2, 1 }, /* VCLK_SRC/2 */ 780 { 4, 2 }, /* VCLK_SRC/4 */ 781 { 8, 3 }, /* VCLK_SRC/8 */ 782 { 3, 4 }, /* VCLK_SRC/3 */ 783 { 16, 5 }, /* VCLK_SRC/16 */ 784 { 6, 6 }, /* VCLK_SRC/6 */ 785 { 12, 7 }, /* VCLK_SRC/12 */ 786 { 0, 0 } 787 }; 788 789 if (radeon_crtc->crtc_id) 790 pll = &rdev->clock.p2pll; 791 else 792 pll = &rdev->clock.p1pll; 793 794 pll->flags = RADEON_PLL_LEGACY; 795 796 if (mode->clock > 200000) /* range limits??? */ 797 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 798 else 799 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 800 801 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 802 if (encoder->crtc == crtc) { 803 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 804 805 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 806 is_tv = true; 807 break; 808 } 809 810 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 811 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 812 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 813 if (!rdev->is_atom_bios) { 814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 815 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 816 if (lvds) { 817 if (lvds->use_bios_dividers) { 818 pll_ref_div = lvds->panel_ref_divider; 819 pll_fb_post_div = (lvds->panel_fb_divider | 820 (lvds->panel_post_divider << 16)); 821 htotal_cntl = 0; 822 use_bios_divs = true; 823 } 824 } 825 } 826 pll->flags |= RADEON_PLL_USE_REF_DIV; 827 } 828 } 829 } 830 831 DRM_DEBUG_KMS("\n"); 832 833 if (!use_bios_divs) { 834 radeon_compute_pll_legacy(pll, mode->clock, 835 &freq, &feedback_div, &frac_fb_div, 836 &reference_div, &post_divider); 837 838 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 839 if (post_div->divider == post_divider) 840 break; 841 } 842 843 if (!post_div->divider) 844 post_div = &post_divs[0]; 845 846 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 847 (unsigned)freq, 848 feedback_div, 849 reference_div, 850 post_divider); 851 852 pll_ref_div = reference_div; 853 #if defined(__powerpc__) && (0) /* TODO */ 854 /* apparently programming this otherwise causes a hang??? */ 855 if (info->MacModel == RADEON_MAC_IBOOK) 856 pll_fb_post_div = 0x000600ad; 857 else 858 #endif 859 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 860 861 htotal_cntl = mode->htotal & 0x7; 862 863 } 864 865 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 866 pll_ref_div & 0x3ff, 867 pll_fb_post_div & 0x7ff); 868 869 if (radeon_crtc->crtc_id) { 870 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 871 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 872 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 873 874 if (is_tv) { 875 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 876 &pll_ref_div, &pll_fb_post_div, 877 &pixclks_cntl); 878 } 879 880 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 881 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 882 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 883 884 WREG32_PLL_P(RADEON_P2PLL_CNTL, 885 RADEON_P2PLL_RESET 886 | RADEON_P2PLL_ATOMIC_UPDATE_EN 887 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 888 ~(RADEON_P2PLL_RESET 889 | RADEON_P2PLL_ATOMIC_UPDATE_EN 890 | RADEON_P2PLL_PVG_MASK)); 891 892 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 893 pll_ref_div, 894 ~RADEON_P2PLL_REF_DIV_MASK); 895 896 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 897 pll_fb_post_div, 898 ~RADEON_P2PLL_FB0_DIV_MASK); 899 900 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 901 pll_fb_post_div, 902 ~RADEON_P2PLL_POST0_DIV_MASK); 903 904 radeon_pll2_write_update(dev); 905 radeon_pll2_wait_for_read_update_complete(dev); 906 907 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 908 909 WREG32_PLL_P(RADEON_P2PLL_CNTL, 910 0, 911 ~(RADEON_P2PLL_RESET 912 | RADEON_P2PLL_SLEEP 913 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 914 915 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 916 (unsigned)pll_ref_div, 917 (unsigned)pll_fb_post_div, 918 (unsigned)htotal_cntl, 919 RREG32_PLL(RADEON_P2PLL_CNTL)); 920 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 921 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 922 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 923 (unsigned)((pll_fb_post_div & 924 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 925 926 mdelay(50); /* Let the clock to lock */ 927 928 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 929 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 930 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 931 932 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 933 } else { 934 uint32_t pixclks_cntl; 935 936 937 if (is_tv) { 938 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 939 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 940 &pll_fb_post_div, &pixclks_cntl); 941 } 942 943 if (rdev->flags & RADEON_IS_MOBILITY) { 944 /* A temporal workaround for the occasional blanking on certain laptop panels. 945 This appears to related to the PLL divider registers (fail to lock?). 946 It occurs even when all dividers are the same with their old settings. 947 In this case we really don't need to fiddle with PLL registers. 948 By doing this we can avoid the blanking problem with some panels. 949 */ 950 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 951 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 952 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 953 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 954 RADEON_PLL_DIV_SEL, 955 ~(RADEON_PLL_DIV_SEL)); 956 r100_pll_errata_after_index(rdev); 957 return; 958 } 959 } 960 961 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 962 RADEON_VCLK_SRC_SEL_CPUCLK, 963 ~(RADEON_VCLK_SRC_SEL_MASK)); 964 WREG32_PLL_P(RADEON_PPLL_CNTL, 965 RADEON_PPLL_RESET 966 | RADEON_PPLL_ATOMIC_UPDATE_EN 967 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 968 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 969 ~(RADEON_PPLL_RESET 970 | RADEON_PPLL_ATOMIC_UPDATE_EN 971 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 972 | RADEON_PPLL_PVG_MASK)); 973 974 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 975 RADEON_PLL_DIV_SEL, 976 ~(RADEON_PLL_DIV_SEL)); 977 r100_pll_errata_after_index(rdev); 978 979 if (ASIC_IS_R300(rdev) || 980 (rdev->family == CHIP_RS300) || 981 (rdev->family == CHIP_RS400) || 982 (rdev->family == CHIP_RS480)) { 983 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 984 /* When restoring console mode, use saved PPLL_REF_DIV 985 * setting. 986 */ 987 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 988 pll_ref_div, 989 0); 990 } else { 991 /* R300 uses ref_div_acc field as real ref divider */ 992 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 993 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 994 ~R300_PPLL_REF_DIV_ACC_MASK); 995 } 996 } else 997 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 998 pll_ref_div, 999 ~RADEON_PPLL_REF_DIV_MASK); 1000 1001 WREG32_PLL_P(RADEON_PPLL_DIV_3, 1002 pll_fb_post_div, 1003 ~RADEON_PPLL_FB3_DIV_MASK); 1004 1005 WREG32_PLL_P(RADEON_PPLL_DIV_3, 1006 pll_fb_post_div, 1007 ~RADEON_PPLL_POST3_DIV_MASK); 1008 1009 radeon_pll_write_update(dev); 1010 radeon_pll_wait_for_read_update_complete(dev); 1011 1012 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 1013 1014 WREG32_PLL_P(RADEON_PPLL_CNTL, 1015 0, 1016 ~(RADEON_PPLL_RESET 1017 | RADEON_PPLL_SLEEP 1018 | RADEON_PPLL_ATOMIC_UPDATE_EN 1019 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 1020 1021 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 1022 pll_ref_div, 1023 pll_fb_post_div, 1024 (unsigned)htotal_cntl, 1025 RREG32_PLL(RADEON_PPLL_CNTL)); 1026 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 1027 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 1028 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 1029 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 1030 1031 mdelay(50); /* Let the clock to lock */ 1032 1033 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 1034 RADEON_VCLK_SRC_SEL_PPLLCLK, 1035 ~(RADEON_VCLK_SRC_SEL_MASK)); 1036 1037 if (is_tv) 1038 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1039 } 1040 } 1041 1042 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 1043 const struct drm_display_mode *mode, 1044 struct drm_display_mode *adjusted_mode) 1045 { 1046 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1047 return false; 1048 return true; 1049 } 1050 1051 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1052 struct drm_display_mode *mode, 1053 struct drm_display_mode *adjusted_mode, 1054 int x, int y, struct drm_framebuffer *old_fb) 1055 { 1056 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1057 1058 /* TODO TV */ 1059 radeon_crtc_set_base(crtc, x, y, old_fb); 1060 radeon_set_crtc_timing(crtc, adjusted_mode); 1061 radeon_set_pll(crtc, adjusted_mode); 1062 radeon_overscan_setup(crtc, adjusted_mode); 1063 if (radeon_crtc->crtc_id == 0) { 1064 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1065 } else { 1066 if (radeon_crtc->rmx_type != RMX_OFF) { 1067 /* FIXME: only first crtc has rmx what should we 1068 * do ? 1069 */ 1070 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1071 } 1072 } 1073 radeon_cursor_reset(crtc); 1074 return 0; 1075 } 1076 1077 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1078 { 1079 struct drm_device *dev = crtc->dev; 1080 struct drm_crtc *crtci; 1081 1082 /* 1083 * The hardware wedges sometimes if you reconfigure one CRTC 1084 * whilst another is running (see fdo bug #24611). 1085 */ 1086 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1087 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1088 } 1089 1090 static void radeon_crtc_commit(struct drm_crtc *crtc) 1091 { 1092 struct drm_device *dev = crtc->dev; 1093 struct drm_crtc *crtci; 1094 1095 /* 1096 * Reenable the CRTCs that should be running. 1097 */ 1098 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1099 if (crtci->enabled) 1100 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1101 } 1102 } 1103 1104 static void radeon_crtc_disable(struct drm_crtc *crtc) 1105 { 1106 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1107 if (crtc->primary->fb) { 1108 int r; 1109 struct radeon_bo *rbo; 1110 1111 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); 1112 r = radeon_bo_reserve(rbo, false); 1113 if (unlikely(r)) 1114 DRM_ERROR("failed to reserve rbo before unpin\n"); 1115 else { 1116 radeon_bo_unpin(rbo); 1117 radeon_bo_unreserve(rbo); 1118 } 1119 } 1120 } 1121 1122 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1123 .dpms = radeon_crtc_dpms, 1124 .mode_fixup = radeon_crtc_mode_fixup, 1125 .mode_set = radeon_crtc_mode_set, 1126 .mode_set_base = radeon_crtc_set_base, 1127 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1128 .prepare = radeon_crtc_prepare, 1129 .commit = radeon_crtc_commit, 1130 .disable = radeon_crtc_disable 1131 }; 1132 1133 1134 void radeon_legacy_init_crtc(struct drm_device *dev, 1135 struct radeon_crtc *radeon_crtc) 1136 { 1137 if (radeon_crtc->crtc_id == 1) 1138 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1139 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1140 } 1141
Indexes created Thu Sep 25 16:09:42 GMT 2025