1 /* $NetBSD: radeon_legacy_encoders.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_encoders.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <linux/backlight.h> 33 #include <linux/pci.h> 34 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_device.h> 37 #include <drm/drm_file.h> 38 #include <drm/drm_util.h> 39 #include <drm/radeon_drm.h> 40 41 #include "radeon.h" 42 #include "radeon_asic.h" 43 #include "atom.h" 44 #ifdef CONFIG_PMAC_BACKLIGHT 45 #include <asm/backlight.h> 46 #endif 47 48 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) 49 { 50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 51 const struct drm_encoder_helper_funcs *encoder_funcs; 52 53 encoder_funcs = encoder->helper_private; 54 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 55 radeon_encoder->active_device = 0; 56 } 57 58 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) 59 { 60 struct drm_device *dev = encoder->dev; 61 struct radeon_device *rdev = dev->dev_private; 62 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 63 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 64 int panel_pwr_delay = 2000; 65 bool is_mac = false; 66 uint8_t backlight_level; 67 DRM_DEBUG_KMS("\n"); 68 69 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 70 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 71 72 if (radeon_encoder->enc_priv) { 73 if (rdev->is_atom_bios) { 74 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 75 panel_pwr_delay = lvds->panel_pwr_delay; 76 if (lvds->bl_dev) 77 backlight_level = lvds->backlight_level; 78 } else { 79 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 80 panel_pwr_delay = lvds->panel_pwr_delay; 81 if (lvds->bl_dev) 82 backlight_level = lvds->backlight_level; 83 } 84 } 85 86 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely 87 * Taken from radeonfb. 88 */ 89 if ((rdev->mode_info.connector_table == CT_IBOOK) || 90 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || 91 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || 92 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) 93 is_mac = true; 94 95 switch (mode) { 96 case DRM_MODE_DPMS_ON: 97 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 98 disp_pwr_man |= RADEON_AUTO_PWRUP_EN; 99 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); 100 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 101 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 102 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 103 mdelay(1); 104 105 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 106 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 107 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 108 109 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 110 RADEON_LVDS_BL_MOD_LEVEL_MASK); 111 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | 112 RADEON_LVDS_DIGON | RADEON_LVDS_BLON | 113 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); 114 if (is_mac) 115 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 116 mdelay(panel_pwr_delay); 117 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 118 break; 119 case DRM_MODE_DPMS_STANDBY: 120 case DRM_MODE_DPMS_SUSPEND: 121 case DRM_MODE_DPMS_OFF: 122 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 123 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 124 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 125 if (is_mac) { 126 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; 127 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 128 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 129 } else { 130 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 131 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 132 } 133 mdelay(panel_pwr_delay); 134 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 135 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 136 mdelay(panel_pwr_delay); 137 break; 138 } 139 140 if (rdev->is_atom_bios) 141 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 142 else 143 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 144 145 } 146 147 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) 148 { 149 struct radeon_device *rdev = encoder->dev->dev_private; 150 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 151 DRM_DEBUG("\n"); 152 153 if (radeon_encoder->enc_priv) { 154 if (rdev->is_atom_bios) { 155 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 156 lvds->dpms_mode = mode; 157 } else { 158 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 159 lvds->dpms_mode = mode; 160 } 161 } 162 163 radeon_legacy_lvds_update(encoder, mode); 164 } 165 166 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) 167 { 168 struct radeon_device *rdev = encoder->dev->dev_private; 169 170 if (rdev->is_atom_bios) 171 radeon_atom_output_lock(encoder, true); 172 else 173 radeon_combios_output_lock(encoder, true); 174 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 175 } 176 177 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 178 { 179 struct radeon_device *rdev = encoder->dev->dev_private; 180 181 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); 182 if (rdev->is_atom_bios) 183 radeon_atom_output_lock(encoder, false); 184 else 185 radeon_combios_output_lock(encoder, false); 186 } 187 188 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, 189 struct drm_display_mode *mode, 190 struct drm_display_mode *adjusted_mode) 191 { 192 struct drm_device *dev = encoder->dev; 193 struct radeon_device *rdev = dev->dev_private; 194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 195 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 196 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; 197 198 DRM_DEBUG_KMS("\n"); 199 200 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 201 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; 202 203 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 204 if (rdev->is_atom_bios) { 205 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl 206 * need to call that on resume to set up the reg properly. 207 */ 208 radeon_encoder->pixel_clock = adjusted_mode->clock; 209 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 210 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 211 } else { 212 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 213 if (lvds) { 214 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); 215 lvds_gen_cntl = lvds->lvds_gen_cntl; 216 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 217 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 218 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 219 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 220 } else 221 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 222 } 223 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 224 lvds_gen_cntl &= ~(RADEON_LVDS_ON | 225 RADEON_LVDS_BLON | 226 RADEON_LVDS_EN | 227 RADEON_LVDS_RST_FM); 228 229 if (ASIC_IS_R300(rdev)) 230 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); 231 232 if (radeon_crtc->crtc_id == 0) { 233 if (ASIC_IS_R300(rdev)) { 234 if (radeon_encoder->rmx_type != RMX_OFF) 235 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; 236 } else 237 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; 238 } else { 239 if (ASIC_IS_R300(rdev)) 240 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; 241 else 242 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; 243 } 244 245 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 246 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 247 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); 248 249 if (rdev->family == CHIP_RV410) 250 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); 251 252 if (rdev->is_atom_bios) 253 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 254 else 255 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 256 } 257 258 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, 259 const struct drm_display_mode *mode, 260 struct drm_display_mode *adjusted_mode) 261 { 262 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 263 264 /* set the active encoder to connector routing */ 265 radeon_encoder_set_active_device(encoder); 266 drm_mode_set_crtcinfo(adjusted_mode, 0); 267 268 /* get the native mode for LVDS */ 269 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 270 radeon_panel_mode_fixup(encoder, adjusted_mode); 271 272 return true; 273 } 274 275 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { 276 .dpms = radeon_legacy_lvds_dpms, 277 .mode_fixup = radeon_legacy_mode_fixup, 278 .prepare = radeon_legacy_lvds_prepare, 279 .mode_set = radeon_legacy_lvds_mode_set, 280 .commit = radeon_legacy_lvds_commit, 281 .disable = radeon_legacy_encoder_disable, 282 }; 283 284 u8 285 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) 286 { 287 struct drm_device *dev = radeon_encoder->base.dev; 288 struct radeon_device *rdev = dev->dev_private; 289 u8 backlight_level; 290 291 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 292 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 293 294 return backlight_level; 295 } 296 297 void 298 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 299 { 300 struct drm_device *dev = radeon_encoder->base.dev; 301 struct radeon_device *rdev = dev->dev_private; 302 int dpms_mode = DRM_MODE_DPMS_ON; 303 304 if (radeon_encoder->enc_priv) { 305 if (rdev->is_atom_bios) { 306 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 307 if (lvds->backlight_level > 0) 308 dpms_mode = lvds->dpms_mode; 309 else 310 dpms_mode = DRM_MODE_DPMS_OFF; 311 lvds->backlight_level = level; 312 } else { 313 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 314 if (lvds->backlight_level > 0) 315 dpms_mode = lvds->dpms_mode; 316 else 317 dpms_mode = DRM_MODE_DPMS_OFF; 318 lvds->backlight_level = level; 319 } 320 } 321 322 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); 323 } 324 325 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) || IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 326 327 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) 328 { 329 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 330 uint8_t level; 331 332 /* Convert brightness to hardware level */ 333 if (bd->props.brightness < 0) 334 level = 0; 335 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 336 level = RADEON_MAX_BL_LEVEL; 337 else 338 level = bd->props.brightness; 339 340 if (pdata->negative) 341 level = RADEON_MAX_BL_LEVEL - level; 342 343 return level; 344 } 345 346 static int radeon_legacy_backlight_update_status(struct backlight_device *bd) 347 { 348 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 349 struct radeon_encoder *radeon_encoder = pdata->encoder; 350 351 radeon_legacy_set_backlight_level(radeon_encoder, 352 radeon_legacy_lvds_level(bd)); 353 354 return 0; 355 } 356 357 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) 358 { 359 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 360 struct radeon_encoder *radeon_encoder = pdata->encoder; 361 struct drm_device *dev = radeon_encoder->base.dev; 362 struct radeon_device *rdev = dev->dev_private; 363 uint8_t backlight_level; 364 365 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 366 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 367 368 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; 369 } 370 371 static const struct backlight_ops radeon_backlight_ops = { 372 .get_brightness = radeon_legacy_backlight_get_brightness, 373 .update_status = radeon_legacy_backlight_update_status, 374 }; 375 376 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 377 struct drm_connector *drm_connector) 378 { 379 struct drm_device *dev = radeon_encoder->base.dev; 380 struct radeon_device *rdev = dev->dev_private; 381 struct backlight_device *bd; 382 struct backlight_properties props; 383 struct radeon_backlight_privdata *pdata; 384 uint8_t backlight_level; 385 char bl_name[16]; 386 387 if (!radeon_encoder->enc_priv) 388 return; 389 390 #ifdef CONFIG_PMAC_BACKLIGHT 391 if (!pmac_has_backlight_type("ati") && 392 !pmac_has_backlight_type("mnca")) 393 return; 394 #endif 395 396 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 397 if (!pdata) { 398 DRM_ERROR("Memory allocation failed\n"); 399 goto error; 400 } 401 402 memset(&props, 0, sizeof(props)); 403 props.max_brightness = RADEON_MAX_BL_LEVEL; 404 props.type = BACKLIGHT_RAW; 405 snprintf(bl_name, sizeof(bl_name), 406 "radeon_bl%d", dev->primary->index); 407 bd = backlight_device_register(bl_name, drm_connector->kdev, 408 pdata, &radeon_backlight_ops, &props); 409 if (IS_ERR(bd)) { 410 DRM_ERROR("Backlight registration failed\n"); 411 goto error; 412 } 413 414 pdata->encoder = radeon_encoder; 415 416 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 417 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 418 419 /* First, try to detect backlight level sense based on the assumption 420 * that firmware set it up at full brightness 421 */ 422 if (backlight_level == 0) 423 pdata->negative = true; 424 else if (backlight_level == 0xff) 425 pdata->negative = false; 426 else { 427 /* XXX hack... maybe some day we can figure out in what direction 428 * backlight should work on a given panel? 429 */ 430 pdata->negative = (rdev->family != CHIP_RV200 && 431 rdev->family != CHIP_RV250 && 432 rdev->family != CHIP_RV280 && 433 rdev->family != CHIP_RV350); 434 435 #ifdef CONFIG_PMAC_BACKLIGHT 436 pdata->negative = (pdata->negative || 437 of_machine_is_compatible("PowerBook4,3") || 438 of_machine_is_compatible("PowerBook6,3") || 439 of_machine_is_compatible("PowerBook6,5")); 440 #endif 441 } 442 443 if (rdev->is_atom_bios) { 444 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 445 lvds->bl_dev = bd; 446 } else { 447 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 448 lvds->bl_dev = bd; 449 } 450 451 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); 452 bd->props.power = FB_BLANK_UNBLANK; 453 backlight_update_status(bd); 454 455 DRM_INFO("radeon legacy LVDS backlight initialized\n"); 456 rdev->mode_info.bl_encoder = radeon_encoder; 457 458 return; 459 460 error: 461 kfree(pdata); 462 return; 463 } 464 465 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) 466 { 467 struct drm_device *dev = radeon_encoder->base.dev; 468 struct radeon_device *rdev = dev->dev_private; 469 struct backlight_device *bd = NULL; 470 471 if (!radeon_encoder->enc_priv) 472 return; 473 474 if (rdev->is_atom_bios) { 475 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 476 bd = lvds->bl_dev; 477 lvds->bl_dev = NULL; 478 } else { 479 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 480 bd = lvds->bl_dev; 481 lvds->bl_dev = NULL; 482 } 483 484 if (bd) { 485 struct radeon_backlight_privdata *pdata; 486 487 pdata = bl_get_data(bd); 488 backlight_device_unregister(bd); 489 kfree(pdata); 490 491 DRM_INFO("radeon legacy LVDS backlight unloaded\n"); 492 } 493 } 494 495 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 496 497 void radeon_legacy_backlight_init(struct radeon_encoder *encoder) 498 { 499 } 500 501 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) 502 { 503 } 504 505 #endif 506 507 508 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) 509 { 510 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 511 512 if (radeon_encoder->enc_priv) { 513 radeon_legacy_backlight_exit(radeon_encoder); 514 kfree(radeon_encoder->enc_priv); 515 } 516 drm_encoder_cleanup(encoder); 517 kfree(radeon_encoder); 518 } 519 520 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { 521 .destroy = radeon_lvds_enc_destroy, 522 }; 523 524 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) 525 { 526 struct drm_device *dev = encoder->dev; 527 struct radeon_device *rdev = dev->dev_private; 528 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 529 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); 530 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 531 532 DRM_DEBUG_KMS("\n"); 533 534 switch (mode) { 535 case DRM_MODE_DPMS_ON: 536 crtc_ext_cntl |= RADEON_CRTC_CRT_ON; 537 dac_cntl &= ~RADEON_DAC_PDWN; 538 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | 539 RADEON_DAC_PDWN_G | 540 RADEON_DAC_PDWN_B); 541 break; 542 case DRM_MODE_DPMS_STANDBY: 543 case DRM_MODE_DPMS_SUSPEND: 544 case DRM_MODE_DPMS_OFF: 545 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; 546 dac_cntl |= RADEON_DAC_PDWN; 547 dac_macro_cntl |= (RADEON_DAC_PDWN_R | 548 RADEON_DAC_PDWN_G | 549 RADEON_DAC_PDWN_B); 550 break; 551 } 552 553 /* handled in radeon_crtc_dpms() */ 554 if (!(rdev->flags & RADEON_SINGLE_CRTC)) 555 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 556 WREG32(RADEON_DAC_CNTL, dac_cntl); 557 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 558 559 if (rdev->is_atom_bios) 560 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 561 else 562 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 563 564 } 565 566 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) 567 { 568 struct radeon_device *rdev = encoder->dev->dev_private; 569 570 if (rdev->is_atom_bios) 571 radeon_atom_output_lock(encoder, true); 572 else 573 radeon_combios_output_lock(encoder, true); 574 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 575 } 576 577 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 578 { 579 struct radeon_device *rdev = encoder->dev->dev_private; 580 581 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); 582 583 if (rdev->is_atom_bios) 584 radeon_atom_output_lock(encoder, false); 585 else 586 radeon_combios_output_lock(encoder, false); 587 } 588 589 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, 590 struct drm_display_mode *mode, 591 struct drm_display_mode *adjusted_mode) 592 { 593 struct drm_device *dev = encoder->dev; 594 struct radeon_device *rdev = dev->dev_private; 595 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 596 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 597 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; 598 599 DRM_DEBUG_KMS("\n"); 600 601 if (radeon_crtc->crtc_id == 0) { 602 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 603 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 604 ~(RADEON_DISP_DAC_SOURCE_MASK); 605 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 606 } else { 607 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); 608 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 609 } 610 } else { 611 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 612 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 613 ~(RADEON_DISP_DAC_SOURCE_MASK); 614 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; 615 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 616 } else { 617 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; 618 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 619 } 620 } 621 622 dac_cntl = (RADEON_DAC_MASK_ALL | 623 RADEON_DAC_VGA_ADR_EN | 624 /* TODO 6-bits */ 625 RADEON_DAC_8BIT_EN); 626 627 WREG32_P(RADEON_DAC_CNTL, 628 dac_cntl, 629 RADEON_DAC_RANGE_CNTL | 630 RADEON_DAC_BLANKING); 631 632 if (radeon_encoder->enc_priv) { 633 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; 634 dac_macro_cntl = p_dac->ps2_pdac_adj; 635 } else 636 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 637 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; 638 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 639 640 if (rdev->is_atom_bios) 641 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 642 else 643 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 644 } 645 646 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, 647 struct drm_connector *connector) 648 { 649 struct drm_device *dev = encoder->dev; 650 struct radeon_device *rdev = dev->dev_private; 651 uint32_t vclk_ecp_cntl, crtc_ext_cntl; 652 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; 653 enum drm_connector_status found = connector_status_disconnected; 654 bool color = true; 655 656 /* just don't bother on RN50 those chip are often connected to remoting 657 * console hw and often we get failure to load detect those. So to make 658 * everyone happy report the encoder as always connected. 659 */ 660 if (ASIC_IS_RN50(rdev)) { 661 return connector_status_connected; 662 } 663 664 /* save the regs we need */ 665 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 666 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 667 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 668 dac_cntl = RREG32(RADEON_DAC_CNTL); 669 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 670 671 tmp = vclk_ecp_cntl & 672 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); 673 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 674 675 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 676 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 677 678 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | 679 RADEON_DAC_FORCE_DATA_EN; 680 681 if (color) 682 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 683 else 684 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 685 686 if (ASIC_IS_R300(rdev)) 687 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 688 else if (ASIC_IS_RV100(rdev)) 689 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT); 690 else 691 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 692 693 WREG32(RADEON_DAC_EXT_CNTL, tmp); 694 695 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); 696 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 697 WREG32(RADEON_DAC_CNTL, tmp); 698 699 tmp = dac_macro_cntl; 700 tmp &= ~(RADEON_DAC_PDWN_R | 701 RADEON_DAC_PDWN_G | 702 RADEON_DAC_PDWN_B); 703 704 WREG32(RADEON_DAC_MACRO_CNTL, tmp); 705 706 mdelay(2); 707 708 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) 709 found = connector_status_connected; 710 711 /* restore the regs we used */ 712 WREG32(RADEON_DAC_CNTL, dac_cntl); 713 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 714 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 715 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 716 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); 717 718 return found; 719 } 720 721 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { 722 .dpms = radeon_legacy_primary_dac_dpms, 723 .mode_fixup = radeon_legacy_mode_fixup, 724 .prepare = radeon_legacy_primary_dac_prepare, 725 .mode_set = radeon_legacy_primary_dac_mode_set, 726 .commit = radeon_legacy_primary_dac_commit, 727 .detect = radeon_legacy_primary_dac_detect, 728 .disable = radeon_legacy_encoder_disable, 729 }; 730 731 732 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { 733 .destroy = radeon_enc_destroy, 734 }; 735 736 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) 737 { 738 struct drm_device *dev = encoder->dev; 739 struct radeon_device *rdev = dev->dev_private; 740 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); 741 DRM_DEBUG_KMS("\n"); 742 743 switch (mode) { 744 case DRM_MODE_DPMS_ON: 745 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 746 break; 747 case DRM_MODE_DPMS_STANDBY: 748 case DRM_MODE_DPMS_SUSPEND: 749 case DRM_MODE_DPMS_OFF: 750 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 751 break; 752 } 753 754 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 755 756 if (rdev->is_atom_bios) 757 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 758 else 759 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 760 761 } 762 763 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) 764 { 765 struct radeon_device *rdev = encoder->dev->dev_private; 766 767 if (rdev->is_atom_bios) 768 radeon_atom_output_lock(encoder, true); 769 else 770 radeon_combios_output_lock(encoder, true); 771 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 772 } 773 774 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 775 { 776 struct radeon_device *rdev = encoder->dev->dev_private; 777 778 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); 779 780 if (rdev->is_atom_bios) 781 radeon_atom_output_lock(encoder, true); 782 else 783 radeon_combios_output_lock(encoder, true); 784 } 785 786 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 787 struct drm_display_mode *mode, 788 struct drm_display_mode *adjusted_mode) 789 { 790 struct drm_device *dev = encoder->dev; 791 struct radeon_device *rdev = dev->dev_private; 792 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 793 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 794 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; 795 int i; 796 797 DRM_DEBUG_KMS("\n"); 798 799 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); 800 tmp &= 0xfffff; 801 if (rdev->family == CHIP_RV280) { 802 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ 803 tmp ^= (1 << 22); 804 tmds_pll_cntl ^= (1 << 22); 805 } 806 807 if (radeon_encoder->enc_priv) { 808 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; 809 810 for (i = 0; i < 4; i++) { 811 if (tmds->tmds_pll[i].freq == 0) 812 break; 813 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { 814 tmp = tmds->tmds_pll[i].value ; 815 break; 816 } 817 } 818 } 819 820 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { 821 if (tmp & 0xfff00000) 822 tmds_pll_cntl = tmp; 823 else { 824 tmds_pll_cntl &= 0xfff00000; 825 tmds_pll_cntl |= tmp; 826 } 827 } else 828 tmds_pll_cntl = tmp; 829 830 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & 831 ~(RADEON_TMDS_TRANSMITTER_PLLRST); 832 833 if (rdev->family == CHIP_R200 || 834 rdev->family == CHIP_R100 || 835 ASIC_IS_R300(rdev)) 836 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); 837 else /* RV chips got this bit reversed */ 838 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; 839 840 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | 841 (RADEON_FP_CRTC_DONT_SHADOW_VPAR | 842 RADEON_FP_CRTC_DONT_SHADOW_HEND)); 843 844 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 845 846 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 847 RADEON_FP_DFP_SYNC_SEL | 848 RADEON_FP_CRT_SYNC_SEL | 849 RADEON_FP_CRTC_LOCK_8DOT | 850 RADEON_FP_USE_SHADOW_EN | 851 RADEON_FP_CRTC_USE_SHADOW_VEND | 852 RADEON_FP_CRT_SYNC_ALT); 853 854 if (1) /* FIXME rgbBits == 8 */ 855 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 856 else 857 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ 858 859 if (radeon_crtc->crtc_id == 0) { 860 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 861 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 862 if (radeon_encoder->rmx_type != RMX_OFF) 863 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 864 else 865 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 866 } else 867 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; 868 } else { 869 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 870 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 871 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; 872 } else 873 fp_gen_cntl |= RADEON_FP_SEL_CRTC2; 874 } 875 876 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); 877 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); 878 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 879 880 if (rdev->is_atom_bios) 881 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 882 else 883 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 884 } 885 886 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { 887 .dpms = radeon_legacy_tmds_int_dpms, 888 .mode_fixup = radeon_legacy_mode_fixup, 889 .prepare = radeon_legacy_tmds_int_prepare, 890 .mode_set = radeon_legacy_tmds_int_mode_set, 891 .commit = radeon_legacy_tmds_int_commit, 892 .disable = radeon_legacy_encoder_disable, 893 }; 894 895 896 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { 897 .destroy = radeon_enc_destroy, 898 }; 899 900 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) 901 { 902 struct drm_device *dev = encoder->dev; 903 struct radeon_device *rdev = dev->dev_private; 904 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 905 DRM_DEBUG_KMS("\n"); 906 907 switch (mode) { 908 case DRM_MODE_DPMS_ON: 909 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 910 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 911 break; 912 case DRM_MODE_DPMS_STANDBY: 913 case DRM_MODE_DPMS_SUSPEND: 914 case DRM_MODE_DPMS_OFF: 915 fp2_gen_cntl |= RADEON_FP2_BLANK_EN; 916 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 917 break; 918 } 919 920 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 921 922 if (rdev->is_atom_bios) 923 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 924 else 925 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 926 927 } 928 929 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) 930 { 931 struct radeon_device *rdev = encoder->dev->dev_private; 932 933 if (rdev->is_atom_bios) 934 radeon_atom_output_lock(encoder, true); 935 else 936 radeon_combios_output_lock(encoder, true); 937 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 938 } 939 940 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 941 { 942 struct radeon_device *rdev = encoder->dev->dev_private; 943 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); 944 945 if (rdev->is_atom_bios) 946 radeon_atom_output_lock(encoder, false); 947 else 948 radeon_combios_output_lock(encoder, false); 949 } 950 951 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, 952 struct drm_display_mode *mode, 953 struct drm_display_mode *adjusted_mode) 954 { 955 struct drm_device *dev = encoder->dev; 956 struct radeon_device *rdev = dev->dev_private; 957 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 958 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 959 uint32_t fp2_gen_cntl; 960 961 DRM_DEBUG_KMS("\n"); 962 963 if (rdev->is_atom_bios) { 964 radeon_encoder->pixel_clock = adjusted_mode->clock; 965 atombios_dvo_setup(encoder, ATOM_ENABLE); 966 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 967 } else { 968 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 969 970 if (1) /* FIXME rgbBits == 8 */ 971 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ 972 else 973 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ 974 975 fp2_gen_cntl &= ~(RADEON_FP2_ON | 976 RADEON_FP2_DVO_EN | 977 RADEON_FP2_DVO_RATE_SEL_SDR); 978 979 /* XXX: these are oem specific */ 980 if (ASIC_IS_R300(rdev)) { 981 if ((dev->pdev->device == 0x4850) && 982 (dev->pdev->subsystem_vendor == 0x1028) && 983 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ 984 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; 985 else 986 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; 987 988 /*if (mode->clock > 165000) 989 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ 990 } 991 if (!radeon_combios_external_tmds_setup(encoder)) 992 radeon_external_tmds_setup(encoder); 993 } 994 995 if (radeon_crtc->crtc_id == 0) { 996 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 997 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 998 if (radeon_encoder->rmx_type != RMX_OFF) 999 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 1000 else 1001 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 1002 } else 1003 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; 1004 } else { 1005 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 1006 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 1007 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1008 } else 1009 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; 1010 } 1011 1012 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1013 1014 if (rdev->is_atom_bios) 1015 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1016 else 1017 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1018 } 1019 1020 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) 1021 { 1022 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1023 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */ 1024 kfree(radeon_encoder->enc_priv); 1025 drm_encoder_cleanup(encoder); 1026 kfree(radeon_encoder); 1027 } 1028 1029 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { 1030 .dpms = radeon_legacy_tmds_ext_dpms, 1031 .mode_fixup = radeon_legacy_mode_fixup, 1032 .prepare = radeon_legacy_tmds_ext_prepare, 1033 .mode_set = radeon_legacy_tmds_ext_mode_set, 1034 .commit = radeon_legacy_tmds_ext_commit, 1035 .disable = radeon_legacy_encoder_disable, 1036 }; 1037 1038 1039 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { 1040 .destroy = radeon_ext_tmds_enc_destroy, 1041 }; 1042 1043 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) 1044 { 1045 struct drm_device *dev = encoder->dev; 1046 struct radeon_device *rdev = dev->dev_private; 1047 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1048 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 1049 uint32_t tv_master_cntl = 0; 1050 bool is_tv; 1051 DRM_DEBUG_KMS("\n"); 1052 1053 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1054 1055 if (rdev->family == CHIP_R200) 1056 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1057 else { 1058 if (is_tv) 1059 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1060 else 1061 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1062 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1063 } 1064 1065 switch (mode) { 1066 case DRM_MODE_DPMS_ON: 1067 if (rdev->family == CHIP_R200) { 1068 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1069 } else { 1070 if (is_tv) 1071 tv_master_cntl |= RADEON_TV_ON; 1072 else 1073 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 1074 1075 if (rdev->family == CHIP_R420 || 1076 rdev->family == CHIP_R423 || 1077 rdev->family == CHIP_RV410) 1078 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 1079 R420_TV_DAC_GDACPD | 1080 R420_TV_DAC_BDACPD | 1081 RADEON_TV_DAC_BGSLEEP); 1082 else 1083 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 1084 RADEON_TV_DAC_GDACPD | 1085 RADEON_TV_DAC_BDACPD | 1086 RADEON_TV_DAC_BGSLEEP); 1087 } 1088 break; 1089 case DRM_MODE_DPMS_STANDBY: 1090 case DRM_MODE_DPMS_SUSPEND: 1091 case DRM_MODE_DPMS_OFF: 1092 if (rdev->family == CHIP_R200) 1093 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1094 else { 1095 if (is_tv) 1096 tv_master_cntl &= ~RADEON_TV_ON; 1097 else 1098 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 1099 1100 if (rdev->family == CHIP_R420 || 1101 rdev->family == CHIP_R423 || 1102 rdev->family == CHIP_RV410) 1103 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 1104 R420_TV_DAC_GDACPD | 1105 R420_TV_DAC_BDACPD | 1106 RADEON_TV_DAC_BGSLEEP); 1107 else 1108 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | 1109 RADEON_TV_DAC_GDACPD | 1110 RADEON_TV_DAC_BDACPD | 1111 RADEON_TV_DAC_BGSLEEP); 1112 } 1113 break; 1114 } 1115 1116 if (rdev->family == CHIP_R200) { 1117 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1118 } else { 1119 if (is_tv) 1120 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1121 /* handled in radeon_crtc_dpms() */ 1122 else if (!(rdev->flags & RADEON_SINGLE_CRTC)) 1123 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1124 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1125 } 1126 1127 if (rdev->is_atom_bios) 1128 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1129 else 1130 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1131 1132 } 1133 1134 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) 1135 { 1136 struct radeon_device *rdev = encoder->dev->dev_private; 1137 1138 if (rdev->is_atom_bios) 1139 radeon_atom_output_lock(encoder, true); 1140 else 1141 radeon_combios_output_lock(encoder, true); 1142 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 1143 } 1144 1145 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 1146 { 1147 struct radeon_device *rdev = encoder->dev->dev_private; 1148 1149 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); 1150 1151 if (rdev->is_atom_bios) 1152 radeon_atom_output_lock(encoder, true); 1153 else 1154 radeon_combios_output_lock(encoder, true); 1155 } 1156 1157 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, 1158 struct drm_display_mode *mode, 1159 struct drm_display_mode *adjusted_mode) 1160 { 1161 struct drm_device *dev = encoder->dev; 1162 struct radeon_device *rdev = dev->dev_private; 1163 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1164 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1165 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1166 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; 1167 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; 1168 bool is_tv = false; 1169 1170 DRM_DEBUG_KMS("\n"); 1171 1172 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1173 1174 if (rdev->family != CHIP_R200) { 1175 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1176 if (rdev->family == CHIP_R420 || 1177 rdev->family == CHIP_R423 || 1178 rdev->family == CHIP_RV410) { 1179 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1180 RADEON_TV_DAC_BGADJ_MASK | 1181 R420_TV_DAC_DACADJ_MASK | 1182 R420_TV_DAC_RDACPD | 1183 R420_TV_DAC_GDACPD | 1184 R420_TV_DAC_BDACPD | 1185 R420_TV_DAC_TVENABLE); 1186 } else { 1187 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1188 RADEON_TV_DAC_BGADJ_MASK | 1189 RADEON_TV_DAC_DACADJ_MASK | 1190 RADEON_TV_DAC_RDACPD | 1191 RADEON_TV_DAC_GDACPD | 1192 RADEON_TV_DAC_BDACPD); 1193 } 1194 1195 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 1196 1197 if (is_tv) { 1198 if (tv_dac->tv_std == TV_STD_NTSC || 1199 tv_dac->tv_std == TV_STD_NTSC_J || 1200 tv_dac->tv_std == TV_STD_PAL_M || 1201 tv_dac->tv_std == TV_STD_PAL_60) 1202 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; 1203 else 1204 tv_dac_cntl |= tv_dac->pal_tvdac_adj; 1205 1206 if (tv_dac->tv_std == TV_STD_NTSC || 1207 tv_dac->tv_std == TV_STD_NTSC_J) 1208 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 1209 else 1210 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 1211 } else 1212 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | 1213 tv_dac->ps2_tvdac_adj); 1214 1215 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1216 } 1217 1218 if (ASIC_IS_R300(rdev)) { 1219 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; 1220 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1221 } else if (rdev->family != CHIP_R200) 1222 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1223 else if (rdev->family == CHIP_R200) 1224 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1225 1226 if (rdev->family >= CHIP_R200) 1227 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); 1228 1229 if (is_tv) { 1230 uint32_t dac_cntl; 1231 1232 dac_cntl = RREG32(RADEON_DAC_CNTL); 1233 dac_cntl &= ~RADEON_DAC_TVO_EN; 1234 WREG32(RADEON_DAC_CNTL, dac_cntl); 1235 1236 if (ASIC_IS_R300(rdev)) 1237 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; 1238 1239 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; 1240 if (radeon_crtc->crtc_id == 0) { 1241 if (ASIC_IS_R300(rdev)) { 1242 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1243 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | 1244 RADEON_DISP_TV_SOURCE_CRTC); 1245 } 1246 if (rdev->family >= CHIP_R200) { 1247 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; 1248 } else { 1249 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1250 } 1251 } else { 1252 if (ASIC_IS_R300(rdev)) { 1253 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1254 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; 1255 } 1256 if (rdev->family >= CHIP_R200) { 1257 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; 1258 } else { 1259 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1260 } 1261 } 1262 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1263 } else { 1264 1265 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; 1266 1267 if (radeon_crtc->crtc_id == 0) { 1268 if (ASIC_IS_R300(rdev)) { 1269 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1270 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 1271 } else if (rdev->family == CHIP_R200) { 1272 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1273 RADEON_FP2_DVO_RATE_SEL_SDR); 1274 } else 1275 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1276 } else { 1277 if (ASIC_IS_R300(rdev)) { 1278 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1279 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1280 } else if (rdev->family == CHIP_R200) { 1281 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1282 RADEON_FP2_DVO_RATE_SEL_SDR); 1283 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1284 } else 1285 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1286 } 1287 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1288 } 1289 1290 if (ASIC_IS_R300(rdev)) { 1291 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1292 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1293 } else if (rdev->family != CHIP_R200) 1294 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1295 else if (rdev->family == CHIP_R200) 1296 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1297 1298 if (rdev->family >= CHIP_R200) 1299 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); 1300 1301 if (is_tv) 1302 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); 1303 1304 if (rdev->is_atom_bios) 1305 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1306 else 1307 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1308 1309 } 1310 1311 static bool r300_legacy_tv_detect(struct drm_encoder *encoder, 1312 struct drm_connector *connector) 1313 { 1314 struct drm_device *dev = encoder->dev; 1315 struct radeon_device *rdev = dev->dev_private; 1316 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1317 uint32_t disp_output_cntl, gpiopad_a, tmp; 1318 bool found = false; 1319 1320 /* save regs needed */ 1321 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1322 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1323 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1324 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1325 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1326 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1327 1328 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); 1329 1330 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); 1331 1332 WREG32(RADEON_CRTC2_GEN_CNTL, 1333 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); 1334 1335 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1336 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1337 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1338 1339 WREG32(RADEON_DAC_EXT_CNTL, 1340 RADEON_DAC2_FORCE_BLANK_OFF_EN | 1341 RADEON_DAC2_FORCE_DATA_EN | 1342 RADEON_DAC_FORCE_DATA_SEL_RGB | 1343 (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); 1344 1345 WREG32(RADEON_TV_DAC_CNTL, 1346 RADEON_TV_DAC_STD_NTSC | 1347 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1348 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1349 1350 RREG32(RADEON_TV_DAC_CNTL); 1351 mdelay(4); 1352 1353 WREG32(RADEON_TV_DAC_CNTL, 1354 RADEON_TV_DAC_NBLANK | 1355 RADEON_TV_DAC_NHOLD | 1356 RADEON_TV_MONITOR_DETECT_EN | 1357 RADEON_TV_DAC_STD_NTSC | 1358 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1359 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1360 1361 RREG32(RADEON_TV_DAC_CNTL); 1362 mdelay(6); 1363 1364 tmp = RREG32(RADEON_TV_DAC_CNTL); 1365 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { 1366 found = true; 1367 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1368 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1369 found = true; 1370 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1371 } 1372 1373 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1374 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1375 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1376 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1377 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1378 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1379 return found; 1380 } 1381 1382 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, 1383 struct drm_connector *connector) 1384 { 1385 struct drm_device *dev = encoder->dev; 1386 struct radeon_device *rdev = dev->dev_private; 1387 uint32_t tv_dac_cntl, dac_cntl2; 1388 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; 1389 bool found = false; 1390 1391 if (ASIC_IS_R300(rdev)) 1392 return r300_legacy_tv_detect(encoder, connector); 1393 1394 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1395 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1396 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1397 config_cntl = RREG32(RADEON_CONFIG_CNTL); 1398 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); 1399 1400 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; 1401 WREG32(RADEON_DAC_CNTL2, tmp); 1402 1403 tmp = tv_master_cntl | RADEON_TV_ON; 1404 tmp &= ~(RADEON_TV_ASYNC_RST | 1405 RADEON_RESTART_PHASE_FIX | 1406 RADEON_CRT_FIFO_CE_EN | 1407 RADEON_TV_FIFO_CE_EN | 1408 RADEON_RE_SYNC_NOW_SEL_MASK); 1409 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; 1410 WREG32(RADEON_TV_MASTER_CNTL, tmp); 1411 1412 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | 1413 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | 1414 (8 << RADEON_TV_DAC_BGADJ_SHIFT); 1415 1416 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) 1417 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); 1418 else 1419 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); 1420 WREG32(RADEON_TV_DAC_CNTL, tmp); 1421 1422 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | 1423 RADEON_RED_MX_FORCE_DAC_DATA | 1424 RADEON_GRN_MX_FORCE_DAC_DATA | 1425 RADEON_BLU_MX_FORCE_DAC_DATA | 1426 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); 1427 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); 1428 1429 mdelay(3); 1430 tmp = RREG32(RADEON_TV_DAC_CNTL); 1431 if (tmp & RADEON_TV_DAC_GDACDET) { 1432 found = true; 1433 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1434 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1435 found = true; 1436 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1437 } 1438 1439 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 1440 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1441 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1442 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1443 return found; 1444 } 1445 1446 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, 1447 struct drm_connector *connector) 1448 { 1449 struct drm_device *dev = encoder->dev; 1450 struct radeon_device *rdev = dev->dev_private; 1451 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; 1452 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; 1453 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; 1454 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; 1455 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; 1456 bool found = false; 1457 int i; 1458 1459 /* save the regs we need */ 1460 gpio_monid = RREG32(RADEON_GPIO_MONID); 1461 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1462 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1463 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1464 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); 1465 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); 1466 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); 1467 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D); 1468 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E); 1469 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F); 1470 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP); 1471 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP); 1472 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID); 1473 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID); 1474 1475 tmp = RREG32(RADEON_GPIO_MONID); 1476 tmp &= ~RADEON_GPIO_A_0; 1477 WREG32(RADEON_GPIO_MONID, tmp); 1478 1479 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON | 1480 RADEON_FP2_PANEL_FORMAT | 1481 R200_FP2_SOURCE_SEL_TRANS_UNIT | 1482 RADEON_FP2_DVO_EN | 1483 R200_FP2_DVO_RATE_SEL_SDR)); 1484 1485 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | 1486 RADEON_DISP_TRANS_MATRIX_GRAPHICS)); 1487 1488 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | 1489 RADEON_CRTC2_DISP_REQ_EN_B)); 1490 1491 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); 1492 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); 1493 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); 1494 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); 1495 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); 1496 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); 1497 1498 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); 1499 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); 1500 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); 1501 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); 1502 1503 for (i = 0; i < 200; i++) { 1504 tmp = RREG32(RADEON_GPIO_MONID); 1505 if (tmp & RADEON_GPIO_Y_0) 1506 found = true; 1507 1508 if (found) 1509 break; 1510 1511 if (!drm_can_sleep()) 1512 mdelay(1); 1513 else 1514 msleep(1); 1515 } 1516 1517 /* restore the regs we used */ 1518 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); 1519 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); 1520 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); 1521 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); 1522 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); 1523 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); 1524 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); 1525 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); 1526 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); 1527 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); 1528 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1529 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1530 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1531 WREG32(RADEON_GPIO_MONID, gpio_monid); 1532 1533 return found; 1534 } 1535 1536 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1537 struct drm_connector *connector) 1538 { 1539 struct drm_device *dev = encoder->dev; 1540 struct radeon_device *rdev = dev->dev_private; 1541 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1542 uint32_t gpiopad_a = 0, pixclks_cntl, tmp; 1543 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0; 1544 enum drm_connector_status found = connector_status_disconnected; 1545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1546 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1547 bool color = true; 1548 struct drm_crtc *crtc; 1549 1550 /* find out if crtc2 is in use or if this encoder is using it */ 1551 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1553 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { 1554 if (encoder->crtc != crtc) { 1555 return connector_status_disconnected; 1556 } 1557 } 1558 } 1559 1560 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || 1561 connector->connector_type == DRM_MODE_CONNECTOR_Composite || 1562 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { 1563 bool tv_detect; 1564 1565 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) 1566 return connector_status_disconnected; 1567 1568 tv_detect = radeon_legacy_tv_detect(encoder, connector); 1569 if (tv_detect && tv_dac) 1570 found = connector_status_connected; 1571 return found; 1572 } 1573 1574 /* don't probe if the encoder is being used for something else not CRT related */ 1575 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { 1576 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); 1577 return connector_status_disconnected; 1578 } 1579 1580 /* R200 uses an external DAC for secondary DAC */ 1581 if (rdev->family == CHIP_R200) { 1582 if (radeon_legacy_ext_dac_detect(encoder, connector)) 1583 found = connector_status_connected; 1584 return found; 1585 } 1586 1587 /* save the regs we need */ 1588 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1589 1590 if (rdev->flags & RADEON_SINGLE_CRTC) { 1591 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 1592 } else { 1593 if (ASIC_IS_R300(rdev)) { 1594 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1595 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1596 } else { 1597 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1598 } 1599 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1600 } 1601 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1602 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1603 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1604 1605 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb 1606 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1607 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 1608 1609 if (rdev->flags & RADEON_SINGLE_CRTC) { 1610 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 1611 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 1612 } else { 1613 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; 1614 tmp |= RADEON_CRTC2_CRT2_ON | 1615 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); 1616 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 1617 1618 if (ASIC_IS_R300(rdev)) { 1619 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1620 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1621 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1622 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1623 } else { 1624 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1625 WREG32(RADEON_DISP_HW_DEBUG, tmp); 1626 } 1627 } 1628 1629 tmp = RADEON_TV_DAC_NBLANK | 1630 RADEON_TV_DAC_NHOLD | 1631 RADEON_TV_MONITOR_DETECT_EN | 1632 RADEON_TV_DAC_STD_PS2; 1633 1634 WREG32(RADEON_TV_DAC_CNTL, tmp); 1635 1636 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | 1637 RADEON_DAC2_FORCE_DATA_EN; 1638 1639 if (color) 1640 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1641 else 1642 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1643 1644 if (ASIC_IS_R300(rdev)) 1645 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1646 else 1647 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1648 1649 WREG32(RADEON_DAC_EXT_CNTL, tmp); 1650 1651 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1652 WREG32(RADEON_DAC_CNTL2, tmp); 1653 1654 mdelay(10); 1655 1656 if (ASIC_IS_R300(rdev)) { 1657 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) 1658 found = connector_status_connected; 1659 } else { 1660 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) 1661 found = connector_status_connected; 1662 } 1663 1664 /* restore regs we used */ 1665 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1666 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1667 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1668 1669 if (rdev->flags & RADEON_SINGLE_CRTC) { 1670 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 1671 } else { 1672 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1673 if (ASIC_IS_R300(rdev)) { 1674 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1675 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1676 } else { 1677 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1678 } 1679 } 1680 1681 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1682 1683 return found; 1684 1685 } 1686 1687 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { 1688 .dpms = radeon_legacy_tv_dac_dpms, 1689 .mode_fixup = radeon_legacy_mode_fixup, 1690 .prepare = radeon_legacy_tv_dac_prepare, 1691 .mode_set = radeon_legacy_tv_dac_mode_set, 1692 .commit = radeon_legacy_tv_dac_commit, 1693 .detect = radeon_legacy_tv_dac_detect, 1694 .disable = radeon_legacy_encoder_disable, 1695 }; 1696 1697 1698 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { 1699 .destroy = radeon_enc_destroy, 1700 }; 1701 1702 1703 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) 1704 { 1705 struct drm_device *dev = encoder->base.dev; 1706 struct radeon_device *rdev = dev->dev_private; 1707 struct radeon_encoder_int_tmds *tmds = NULL; 1708 bool ret; 1709 1710 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); 1711 1712 if (!tmds) 1713 return NULL; 1714 1715 if (rdev->is_atom_bios) 1716 ret = radeon_atombios_get_tmds_info(encoder, tmds); 1717 else 1718 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); 1719 1720 if (!ret) 1721 radeon_legacy_get_tmds_info_from_table(encoder, tmds); 1722 1723 return tmds; 1724 } 1725 1726 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) 1727 { 1728 struct drm_device *dev = encoder->base.dev; 1729 struct radeon_device *rdev = dev->dev_private; 1730 struct radeon_encoder_ext_tmds *tmds = NULL; 1731 bool ret; 1732 1733 if (rdev->is_atom_bios) 1734 return NULL; 1735 1736 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); 1737 1738 if (!tmds) 1739 return NULL; 1740 1741 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); 1742 1743 if (!ret) 1744 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); 1745 1746 return tmds; 1747 } 1748 1749 void 1750 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) 1751 { 1752 struct radeon_device *rdev = dev->dev_private; 1753 struct drm_encoder *encoder; 1754 struct radeon_encoder *radeon_encoder; 1755 1756 /* see if we already added it */ 1757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1758 radeon_encoder = to_radeon_encoder(encoder); 1759 if (radeon_encoder->encoder_enum == encoder_enum) { 1760 radeon_encoder->devices |= supported_device; 1761 return; 1762 } 1763 1764 } 1765 1766 /* add a new one */ 1767 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 1768 if (!radeon_encoder) 1769 return; 1770 1771 encoder = &radeon_encoder->base; 1772 if (rdev->flags & RADEON_SINGLE_CRTC) 1773 encoder->possible_crtcs = 0x1; 1774 else 1775 encoder->possible_crtcs = 0x3; 1776 1777 radeon_encoder->enc_priv = NULL; 1778 1779 radeon_encoder->encoder_enum = encoder_enum; 1780 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1781 radeon_encoder->devices = supported_device; 1782 radeon_encoder->rmx_type = RMX_OFF; 1783 1784 switch (radeon_encoder->encoder_id) { 1785 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1786 encoder->possible_crtcs = 0x1; 1787 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, 1788 DRM_MODE_ENCODER_LVDS, NULL); 1789 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); 1790 if (rdev->is_atom_bios) 1791 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1792 else 1793 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); 1794 radeon_encoder->rmx_type = RMX_FULL; 1795 break; 1796 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1797 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, 1798 DRM_MODE_ENCODER_TMDS, NULL); 1799 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); 1800 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); 1801 break; 1802 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1803 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, 1804 DRM_MODE_ENCODER_DAC, NULL); 1805 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); 1806 if (rdev->is_atom_bios) 1807 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); 1808 else 1809 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); 1810 break; 1811 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1812 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, 1813 DRM_MODE_ENCODER_TVDAC, NULL); 1814 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); 1815 if (rdev->is_atom_bios) 1816 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); 1817 else 1818 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); 1819 break; 1820 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1821 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, 1822 DRM_MODE_ENCODER_TMDS, NULL); 1823 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); 1824 if (!rdev->is_atom_bios) 1825 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); 1826 break; 1827 } 1828 } 1829
Indexes created Sat Sep 20 22:09:52 GMT 2025