1 /* $NetBSD: radeonfb.c,v 1.125 2026/07/24 07:40:47 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.125 2026/07/24 07:40:47 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 #include <sys/kmem.h> 84 85 #include <dev/wscons/wsdisplayvar.h> 86 #include <dev/wscons/wsconsio.h> 87 #include <dev/wsfont/wsfont.h> 88 #include <dev/rasops/rasops.h> 89 #include <dev/videomode/videomode.h> 90 #include <dev/videomode/edidvar.h> 91 #include <dev/wscons/wsdisplay_vconsvar.h> 92 #include <dev/pci/wsdisplay_pci.h> 93 #include <dev/wscons/wsdisplay_glyphcachevar.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 #include "opt_vcons.h" 103 104 #ifdef RADEONFB_DEPTH_32 105 #define RADEONFB_DEFAULT_DEPTH 32 106 #else 107 #define RADEONFB_DEFAULT_DEPTH 8 108 #endif 109 110 static int radeonfb_match(device_t, cfdata_t, void *); 111 static void radeonfb_attach(device_t, device_t, void *); 112 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 113 struct lwp *); 114 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 115 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 116 static void radeonfb_loadbios(struct radeonfb_softc *, 117 const struct pci_attach_args *); 118 119 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 120 uintmax_t); 121 static int radeonfb_getclocks(struct radeonfb_softc *); 122 static int radeonfb_gettmds(struct radeonfb_softc *); 123 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 124 uint32_t *, uint32_t *, int); 125 /* flags for radeonfb_calc_dividers */ 126 #define NO_ODD_FBDIV 1 127 128 static int radeonfb_getconnectors(struct radeonfb_softc *); 129 static const struct videomode *radeonfb_modelookup(const char *); 130 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 131 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 132 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 133 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 134 static void radeonfb_modeswitch(struct radeonfb_display *); 135 static void radeonfb_setcrtc(struct radeonfb_display *, int); 136 static void radeonfb_init_misc(struct radeonfb_softc *); 137 static void radeonfb_set_fbloc(struct radeonfb_softc *); 138 static void radeonfb_init_palette(struct radeonfb_display *); 139 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 140 141 static int radeonfb_isblank(struct radeonfb_display *); 142 static void radeonfb_blank(struct radeonfb_display *, int); 143 static int radeonfb_set_cursor(struct radeonfb_display *, 144 struct wsdisplay_cursor *); 145 static int radeonfb_set_curpos(struct radeonfb_display *, 146 struct wsdisplay_curpos *); 147 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 148 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 150 151 /* acceleration support */ 152 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 153 int width, int height, uint32_t color); 154 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 155 static void radeonfb_bitblt(void *, int srcx, int srcy, 156 int dstx, int dsty, int width, int height, int rop); 157 158 /* hw cursor support */ 159 static void radeonfb_cursor_cmap(struct radeonfb_display *); 160 static void radeonfb_cursor_shape(struct radeonfb_display *); 161 static void radeonfb_cursor_position(struct radeonfb_display *); 162 static void radeonfb_cursor_visible(struct radeonfb_display *); 163 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 164 165 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 166 static void radeonfb_engine_idle(struct radeonfb_softc *); 167 static void radeonfb_engine_flush(struct radeonfb_softc *); 168 static void radeonfb_engine_reset(struct radeonfb_softc *); 169 static void radeonfb_engine_init(struct radeonfb_display *); 170 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 171 172 static void radeonfb_eraserows(void *, int, int, long); 173 static void radeonfb_erasecols(void *, int, int, int, long); 174 static void radeonfb_copyrows(void *, int, int, int); 175 static void radeonfb_copycols(void *, int, int, int, int); 176 static void radeonfb_cursor(void *, int, int, int); 177 static void radeonfb_putchar(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 179 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 180 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 181 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 182 #endif 183 static int radeonfb_allocattr(void *, int, int, int, long *); 184 185 static int radeonfb_set_backlight(struct radeonfb_display *, int); 186 static int radeonfb_get_backlight(struct radeonfb_display *); 187 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 188 static void radeonfb_lvds_callout(void *); 189 190 static void radeonfb_brightness_up(device_t); 191 static void radeonfb_brightness_down(device_t); 192 193 static struct videomode *radeonfb_best_refresh(struct videomode *, 194 struct videomode *); 195 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 196 uint16_t *, int); 197 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 198 struct radeonfb_port *, int, int); 199 200 static int radeonfb_drm_print(void *, const char *); 201 202 #ifdef RADEONFB_DEBUG 203 int radeon_debug = 1; 204 #define DPRINTF(x) \ 205 if (radeon_debug) printf x 206 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 207 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 208 #else 209 #define DPRINTF(x) 210 #define PRINTREG(r) 211 #define PRINTPLL(r) 212 #endif 213 214 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 215 216 #ifndef RADEON_DEFAULT_MODE 217 /* any reasonably modern display should handle this */ 218 #define RADEON_DEFAULT_MODE "1024x768x60" 219 #endif 220 221 extern const u_char rasops_cmap[768]; 222 223 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 224 225 static struct { 226 int size; /* minimum memory size (MB) */ 227 int maxx; /* maximum x dimension */ 228 int maxy; /* maximum y dimension */ 229 int maxbpp; /* maximum bpp */ 230 int maxdisp; /* maximum logical display count */ 231 } radeonfb_limits[] = { 232 { 32, 2048, 1536, 32, 2 }, 233 { 16, 1600, 1200, 32, 2 }, 234 { 8, 1600, 1200, 32, 1 }, 235 { 0, 0, 0, 0, 0 }, 236 }; 237 238 static struct wsscreen_descr radeonfb_stdscreen = { 239 "fb", /* name */ 240 0, 0, /* ncols, nrows */ 241 NULL, /* textops */ 242 8, 16, /* fontwidth, fontheight */ 243 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 244 0, /* modecookie */ 245 }; 246 247 struct wsdisplay_accessops radeonfb_accessops = { 248 radeonfb_ioctl, 249 radeonfb_mmap, 250 NULL, /* vcons_alloc_screen */ 251 NULL, /* vcons_free_screen */ 252 NULL, /* vcons_show_screen */ 253 NULL, /* load_font */ 254 NULL, /* pollc */ 255 NULL, /* scroll */ 256 }; 257 258 static struct { 259 uint16_t devid; 260 uint16_t family; 261 uint16_t flags; 262 } radeonfb_devices[] = 263 { 264 /* R100 family */ 265 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 269 270 /* RV100 family */ 271 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 275 276 /* RS100 family */ 277 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 279 280 /* RS200/RS250 family */ 281 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 284 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 285 286 /* R200 family */ 287 /* add more R200 products? , 5148 */ 288 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 293 294 /* RV200 family */ 295 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 299 300 /* RV250 family */ 301 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 305 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 306 307 /* RS300 family */ 308 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 312 313 /* RV280 family */ 314 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 321 322 /* R300 family */ 323 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 331 332 /* RV350/RV360 family */ 333 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 344 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 345 346 /* R350/R360 family */ 347 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 355 356 /* RV380/RV370 family */ 357 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 359 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 367 368 #if notyet 369 /* R420/R423 family */ 370 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 377 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 385 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 386 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 387 #endif 388 389 /* R5xx family */ 390 { 0x7240, RADEON_R580, RFB_IS_AVIVO }, 391 { 0, 0, 0 } 392 }; 393 394 static struct { 395 int divider; 396 int mask; 397 } radeonfb_dividers[] = { 398 { 16, 5 }, 399 { 12, 7 }, 400 { 8, 3 }, 401 { 6, 6 }, 402 { 4, 2 }, 403 { 3, 4 }, 404 { 2, 1 }, 405 { 1, 0 }, 406 { 0, 0 } 407 }; 408 409 /* 410 * This table taken from X11. 411 */ 412 static const struct { 413 int family; 414 struct radeon_tmds_pll plls[4]; 415 } radeonfb_tmds_pll[] = { 416 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 417 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS100, {{0, 0}}}, 419 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 421 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 422 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 423 { RADEON_RS300, {{0, 0}}}, 424 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 425 { RADEON_R300, {{-1, 0xb01cb}}}, 426 { RADEON_R350, {{-1, 0xb01cb}}}, 427 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 428 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 429 { RADEON_R420, {{-1, 0xb01cb}}}, 430 { RADEON_R580, {{-1, 0xb01cb}}}, /* XXX likely bogus */ 431 }; 432 433 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 434 435 436 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 437 radeonfb_match, radeonfb_attach, NULL, NULL); 438 439 static int 440 radeonfb_match(device_t parent, cfdata_t match, void *aux) 441 { 442 const struct pci_attach_args *pa = aux; 443 int i; 444 445 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 446 return 0; 447 448 for (i = 0; radeonfb_devices[i].devid; i++) { 449 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 450 return 100; /* high to defeat VGA/VESA */ 451 } 452 453 return 0; 454 } 455 456 static void 457 radeonfb_attach(device_t parent, device_t dev, void *aux) 458 { 459 struct radeonfb_softc *sc = device_private(dev); 460 const struct pci_attach_args *pa = aux; 461 const char *mptr; 462 bus_size_t bsz; 463 pcireg_t screg; 464 int i, j, fg, bg, ul, flags; 465 uint32_t v; 466 char memstr[16] = ""; 467 468 sc->sc_dev = dev; 469 sc->sc_id = pa->pa_id; 470 for (i = 0; radeonfb_devices[i].devid; i++) { 471 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 472 break; 473 } 474 475 pci_aprint_devinfo(pa, NULL); 476 477 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 478 479 KASSERT(radeonfb_devices[i].devid != 0); 480 sc->sc_pt = pa->pa_tag; 481 sc->sc_iot = pa->pa_iot; 482 sc->sc_pc = pa->pa_pc; 483 sc->sc_family = radeonfb_devices[i].family; 484 sc->sc_flags = radeonfb_devices[i].flags; 485 sc->sc_bios = NULL; 486 sc->sc_biossz = 0; 487 488 /* enable memory and IO access */ 489 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 490 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 491 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 492 493 /* 494 * Some flags are general to entire chip families, and rather 495 * than clutter up the table with them, we go ahead and set 496 * them here. 497 */ 498 switch (sc->sc_family) { 499 case RADEON_RS100: 500 case RADEON_RS200: 501 sc->sc_flags |= RFB_IGP | RFB_RV100; 502 break; 503 504 case RADEON_RV100: 505 case RADEON_RV200: 506 case RADEON_RV250: 507 case RADEON_RV280: 508 sc->sc_flags |= RFB_RV100; 509 break; 510 511 case RADEON_RS300: 512 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 513 break; 514 515 case RADEON_R300: 516 case RADEON_RV350: 517 case RADEON_R350: 518 case RADEON_RV380: 519 case RADEON_R420: 520 case RADEON_R580: 521 /* newer chips */ 522 sc->sc_flags |= RFB_R300; 523 break; 524 525 case RADEON_R100: 526 sc->sc_flags |= RFB_NCRTC2; 527 break; 528 } 529 530 if ((sc->sc_family == RADEON_RV200) || 531 (sc->sc_family == RADEON_RV250) || 532 (sc->sc_family == RADEON_RV280) || 533 (sc->sc_family == RADEON_RV350)) { 534 bool inverted = 0; 535 /* backlight level is linear */ 536 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 537 prop_dictionary_get_bool(device_properties(sc->sc_dev), 538 "backlight_level_reverted", &inverted); 539 if (inverted) { 540 DPRINTF(("nope, it's inverted\n")); 541 sc->sc_flags |= RFB_INV_BLIGHT; 542 } 543 } else 544 sc->sc_flags |= RFB_INV_BLIGHT; 545 546 /* 547 * XXX: to support true multihead, this must change. 548 */ 549 sc->sc_ndisplays = 1; 550 551 /* XXX: */ 552 if (!HAS_CRTC2(sc)) { 553 sc->sc_ndisplays = 1; 554 } 555 556 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 557 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 558 &sc->sc_regsz) != 0) { 559 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 560 goto error; 561 } 562 563 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 564 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 565 { 566 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 567 goto error; 568 } 569 sc->sc_romt = sc->sc_memt; 570 571 sc->sc_mapped = TRUE; 572 573 /* scratch register test... */ 574 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 575 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 576 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 577 goto error; 578 } 579 580 PRINTREG(RADEON_CRTC_EXT_CNTL); 581 PRINTREG(RADEON_CRTC_GEN_CNTL); 582 PRINTREG(RADEON_CRTC2_GEN_CNTL); 583 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 584 PRINTREG(RADEON_DAC_CNTL2); 585 PRINTREG(RADEON_BIOS_4_SCRATCH); 586 PRINTREG(RADEON_FP_GEN_CNTL); 587 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 588 PRINTREG(RADEON_FP2_GEN_CNTL); 589 PRINTREG(RADEON_TMDS_CNTL); 590 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 591 PRINTREG(RADEON_TMDS_PLL_CNTL); 592 PRINTREG(RADEON_LVDS_GEN_CNTL); 593 PRINTREG(RADEON_DISP_HW_DEBUG); 594 if (!IS_AVIVO(sc)) { 595 /* 596 XXX: We can't print this, as it's not correctly aligned 597 PRINTREG(RADEON_PIXCLKS_CNTL); 598 */ 599 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 600 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 601 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 602 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 603 } 604 radeonfb_i2c_init(sc); 605 606 radeonfb_loadbios(sc, pa); 607 608 #ifdef RADEONFB_BIOS_INIT 609 if (radeonfb_bios_init(sc)) { 610 aprint_error("%s: BIOS initialization failed\n", XNAME(sc)); 611 } 612 #endif 613 614 /* 615 * XXX 616 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 617 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 618 * support DVI, so for now let's restrict it to only actual RV100 619 */ 620 if (sc->sc_family == RADEON_RV100) 621 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 622 623 /* XXX 624 * according to xf86-video-radeon R3xx has this bit backwards 625 * 626 * this must happen after radeonfb_bios_init(): the BIOS init 627 * tables rewrite TMDS_TRANSMITTER_CNTL and would disable the 628 * transmitter PLL again 629 */ 630 if (IS_R300(sc)) { 631 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 632 0, 633 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 634 } else { 635 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 636 RADEON_TMDS_TRANSMITTER_PLLEN, 637 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 638 } 639 640 if (radeonfb_getclocks(sc)) { 641 aprint_error("%s: Unable to get reference clocks from BIOS\n", 642 XNAME(sc)); 643 goto error; 644 } 645 646 if (radeonfb_gettmds(sc)) { 647 aprint_error("%s: Unable to identify TMDS PLL settings\n", 648 XNAME(sc)); 649 goto error; 650 } 651 652 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 653 "minpll = %d, maxpll = %d\n", XNAME(sc), 654 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 655 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 656 657 radeonfb_getconnectors(sc); 658 659 radeonfb_set_fbloc(sc); 660 661 /* 64 MB should be enough -- more just wastes map entries */ 662 if (sc->sc_memsz > (64 << 20)) { 663 snprintf(memstr, 16, " %d MB,", (int)sc->sc_memsz >> 20); 664 sc->sc_memsz = (64 << 20); 665 } 666 667 for (i = 0; radeonfb_limits[i].size; i++) { 668 if (sc->sc_memsz >= radeonfb_limits[i].size) { 669 sc->sc_maxx = radeonfb_limits[i].maxx; 670 sc->sc_maxy = radeonfb_limits[i].maxy; 671 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 672 /* framebuffer offset, start at a 4K page */ 673 sc->sc_fboffset = sc->sc_memsz / 674 radeonfb_limits[i].maxdisp; 675 /* 676 * we use the fbsize to figure out where we can store 677 * things like cursor data. 678 */ 679 sc->sc_fbsize = 680 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 681 RADEON_STRIDEALIGN) * sc->sc_maxy, 682 4096); 683 break; 684 } 685 } 686 687 688 radeonfb_init_misc(sc); 689 690 /* program the DAC wirings */ 691 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 692 switch (sc->sc_ports[i].rp_dac_type) { 693 case RADEON_DAC_PRIMARY: 694 PATCH32(sc, RADEON_DAC_CNTL2, 695 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 696 ~RADEON_DAC2_DAC_CLK_SEL); 697 break; 698 case RADEON_DAC_TVDAC: 699 /* we always use the TVDAC to drive a secondary analog 700 * CRT for now. if we ever support TV-out this will 701 * have to change. 702 */ 703 SET32(sc, RADEON_DAC_CNTL2, 704 RADEON_DAC2_DAC2_CLK_SEL); 705 PATCH32(sc, RADEON_DISP_HW_DEBUG, 706 i ? 0 : RADEON_CRT2_DISP1_SEL, 707 ~RADEON_CRT2_DISP1_SEL); 708 /* we're using CRTC2 for the 2nd port */ 709 if (sc->sc_ports[i].rp_number == 1) { 710 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 711 RADEON_DISP_DAC2_SOURCE_CRTC2, 712 ~RADEON_DISP_DAC2_SOURCE_MASK); 713 } 714 break; 715 } 716 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 717 sc->sc_ports[i].rp_tmds_type)); 718 switch (sc->sc_ports[i].rp_tmds_type) { 719 case RADEON_TMDS_INT: 720 /* point FP0 at the CRTC this port uses */ 721 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 722 __func__, sc->sc_ports[i].rp_number)); 723 if (IS_R300(sc)) { 724 PATCH32(sc, RADEON_FP_GEN_CNTL, 725 sc->sc_ports[i].rp_number ? 726 R200_FP_SOURCE_SEL_CRTC2 : 727 R200_FP_SOURCE_SEL_CRTC1, 728 ~R200_FP_SOURCE_SEL_MASK); 729 } else { 730 PATCH32(sc, RADEON_FP_GEN_CNTL, 731 sc->sc_ports[i].rp_number ? 732 RADEON_FP_SEL_CRTC2 : 733 RADEON_FP_SEL_CRTC1, 734 ~RADEON_FP_SEL_MASK); 735 } 736 break; 737 case RADEON_TMDS_EXT: 738 /* point FP2 at the CRTC this port uses */ 739 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 740 __func__, sc->sc_ports[i].rp_number)); 741 if (IS_R300(sc)) { 742 PATCH32(sc, RADEON_FP2_GEN_CNTL, 743 sc->sc_ports[i].rp_number ? 744 R200_FP2_SOURCE_SEL_CRTC2 : 745 R200_FP2_SOURCE_SEL_CRTC1, 746 ~R200_FP2_SOURCE_SEL_CRTC2); 747 } else { 748 PATCH32(sc, RADEON_FP2_GEN_CNTL, 749 sc->sc_ports[i].rp_number ? 750 RADEON_FP2_SRC_SEL_CRTC2 : 751 RADEON_FP2_SRC_SEL_CRTC1, 752 ~RADEON_FP2_SRC_SEL_CRTC2); 753 } 754 break; 755 } 756 } 757 PRINTREG(RADEON_DAC_CNTL2); 758 PRINTREG(RADEON_DISP_HW_DEBUG); 759 760 PRINTREG(RADEON_DAC_CNTL); 761 /* other DAC programming */ 762 v = GET32(sc, RADEON_DAC_CNTL); 763 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 764 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 765 PUT32(sc, RADEON_DAC_CNTL, v); 766 PRINTREG(RADEON_DAC_CNTL); 767 768 /* XXX: this may need more investigation */ 769 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 770 PRINTREG(RADEON_TV_DAC_CNTL); 771 772 /* enable TMDS */ 773 SET32(sc, RADEON_FP_GEN_CNTL, 774 RADEON_FP_TMDS_EN | 775 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 776 RADEON_FP_CRTC_DONT_SHADOW_HEND); 777 /* 778 * XXX 779 * no idea why this is necessary - if I do not clear this bit on my 780 * iBook G4 the screen remains black, even though it's already clear. 781 * It needs to be set on my Sun XVR-100 for the DVI port to work 782 * TODO: 783 * see if this is still necessary now that CRTCs, DACs and outputs are 784 * getting wired up in a halfway sane way 785 * 786 * Only do this when we have no BIOS connector table to go by (Mac 787 * and Sun firmware-initialized cards). On cards never POSTed by 788 * firmware sc_fp_gen_cntl holds meaningless reset defaults, duh. 789 */ 790 if (sc->sc_biossz == 0) { 791 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 792 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 793 } else { 794 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 795 } 796 } 797 798 /* 799 * we use bus_space_map instead of pci_mapreg, because we don't 800 * need the full aperature space. no point in wasting virtual 801 * address space we don't intend to use, right? 802 */ 803 if ((sc->sc_memsz < (4096 * 1024)) || 804 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 805 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 806 (bsz < sc->sc_memsz)) { 807 sc->sc_memsz = 0; 808 aprint_error("%s: Bad frame buffer configuration\n", 809 XNAME(sc)); 810 goto error; 811 } 812 813 sc->sc_memt = pa->pa_memt; 814 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 815 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE, 816 &sc->sc_memh) != 0) { 817 sc->sc_memsz = 0; 818 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 819 goto error; 820 } 821 822 aprint_normal("%s:%s %d MB aperture at 0x%08x, " 823 "%d KB registers at 0x%08x\n", XNAME(sc), memstr, 824 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 825 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 826 827 /* setup default video mode from devprop (allows PROM override) */ 828 sc->sc_defaultmode = radeonfb_default_mode; 829 if (prop_dictionary_get_string(device_properties(sc->sc_dev), 830 "videomode", &mptr)) { 831 832 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 833 sc->sc_defaultmode = sc->sc_modebuf; 834 } 835 836 /* initialize some basic display parameters */ 837 for (i = 0; i < sc->sc_ndisplays; i++) { 838 struct radeonfb_display *dp = &sc->sc_displays[i]; 839 struct rasops_info *ri; 840 long defattr; 841 struct wsemuldisplaydev_attach_args aa; 842 843 /* 844 * Figure out how many "displays" (desktops) we are going to 845 * support. If more than one, then each CRTC gets its own 846 * programming. 847 * 848 * XXX: this code needs to change to support mergedfb. 849 * XXX: would be nice to allow this to be overridden 850 */ 851 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 852 DPRINTF(("dual crtcs!\n")); 853 /* 854 * Only wire up CRTCs for ports that have a physical 855 * connector. 856 */ 857 dp->rd_ncrtcs = 0; 858 for (j = 0; j < 2; j++) { 859 if (sc->sc_ports[j].rp_conn_type == 860 RADEON_CONN_NONE) 861 continue; 862 dp->rd_crtcs[dp->rd_ncrtcs].rc_port = 863 &sc->sc_ports[j]; 864 dp->rd_crtcs[dp->rd_ncrtcs].rc_number = 865 sc->sc_ports[j].rp_number; 866 dp->rd_ncrtcs++; 867 } 868 if (dp->rd_ncrtcs == 0) { 869 /* no connector info at all, be safe */ 870 dp->rd_ncrtcs = 1; 871 dp->rd_crtcs[0].rc_port = &sc->sc_ports[0]; 872 dp->rd_crtcs[0].rc_number = 873 sc->sc_ports[0].rp_number; 874 } 875 } else { 876 dp->rd_ncrtcs = 1; 877 dp->rd_crtcs[0].rc_port = 878 &sc->sc_ports[i]; 879 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 880 } 881 882 dp->rd_softc = sc; 883 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 884 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 885 886 /* for text mode, we pick a resolution that won't 887 * require panning */ 888 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 889 890 aprint_normal("%s: display %d: " 891 "initial virtual resolution %dx%d at %d bpp\n", 892 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 893 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 894 sc->sc_fboffset >> 20); 895 /* now select the *video mode* that we will use */ 896 for (j = 0; j < dp->rd_ncrtcs; j++) { 897 const struct videomode *vmp; 898 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 899 dp->rd_virtx, dp->rd_virty); 900 901 /* 902 * virtual resolution should be at least as high as 903 * physical 904 */ 905 if (dp->rd_virtx < vmp->hdisplay || 906 dp->rd_virty < vmp->vdisplay) { 907 dp->rd_virtx = vmp->hdisplay; 908 dp->rd_virty = vmp->vdisplay; 909 } 910 911 dp->rd_crtcs[j].rc_videomode = *vmp; 912 printf("%s: port %d: physical %dx%d %dHz\n", 913 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 914 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 915 vmp->htotal), vmp->vtotal)); 916 } 917 918 /* N.B.: radeon wants 64-byte aligned stride */ 919 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 920 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 921 922 dp->rd_offset = sc->sc_fboffset * i; 923 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 924 sc->sc_memh) + dp->rd_offset; 925 dp->rd_curoff = sc->sc_fboffset - 16384; /* 16KB cursor space */ 926 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 927 928 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 929 930 switch (dp->rd_bpp) { 931 case 8: 932 dp->rd_format = 2; 933 break; 934 case 32: 935 dp->rd_format = 6; 936 break; 937 default: 938 aprint_error("%s: bad depth %d\n", XNAME(sc), 939 dp->rd_bpp); 940 goto error; 941 } 942 DPRINTF(("init engine\n")); 943 /* XXX: this seems suspicious - per display engine 944 initialization? */ 945 946 radeonfb_modeswitch(dp); 947 radeonfb_engine_init(dp); 948 949 /* copy the template into place */ 950 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 951 dp->rd_wsscreens = dp->rd_wsscreens_storage; 952 953 /* and make up the list */ 954 dp->rd_wsscreenlist.nscreens = 1; 955 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 956 957 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 958 &radeonfb_accessops); 959 960 dp->rd_vd.init_screen = radeonfb_init_screen; 961 962 dp->rd_console = 0; 963 prop_dictionary_get_bool(device_properties(sc->sc_dev), 964 "is_console", &dp->rd_console); 965 966 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 967 968 969 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 970 dp->rd_console, &defattr); 971 972 ri = &dp->rd_vscreen.scr_ri; 973 974 /* clear the screen */ 975 rasops_unpack_attr(defattr, &fg, &bg, &ul); 976 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 977 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 978 dp->rd_bg); 979 980 dp->rd_wsscreens->textops = &ri->ri_ops; 981 dp->rd_wsscreens->capabilities = ri->ri_caps; 982 dp->rd_wsscreens->nrows = ri->ri_rows; 983 dp->rd_wsscreens->ncols = ri->ri_cols; 984 985 #ifdef SPLASHSCREEN 986 dp->rd_splash.si_depth = ri->ri_depth; 987 dp->rd_splash.si_bits = ri->ri_bits; 988 dp->rd_splash.si_hwbits = ri->ri_hwbits; 989 dp->rd_splash.si_width = ri->ri_width; 990 dp->rd_splash.si_height = ri->ri_height; 991 dp->rd_splash.si_stride = ri->ri_stride; 992 dp->rd_splash.si_fillrect = NULL; 993 #endif 994 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 995 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 996 dp->rd_gc.gc_rop = RADEON_ROP3_S; 997 dp->rd_gc.gc_blitcookie = dp; 998 /* 999 * use memory between framebuffer and cursor area as glyph 1000 * cache, cap at 4096 lines 1001 */ 1002 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 1003 uimin(4096, 1004 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 1005 dp->rd_virtx, 1006 ri->ri_font->fontwidth, 1007 ri->ri_font->fontheight, 1008 defattr); 1009 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 1010 dp->rd_vd.show_screen_cb = glyphcache_adapt; 1011 1012 if (dp->rd_console) { 1013 1014 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 1015 defattr); 1016 #ifdef SPLASHSCREEN 1017 if (splash_render(&dp->rd_splash, 1018 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1019 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1020 else 1021 #endif 1022 vcons_replay_msgbuf(&dp->rd_vscreen); 1023 } else { 1024 1025 /* 1026 * since we're not the console we can postpone 1027 * the rest until someone actually allocates a 1028 * screen for us. but we do clear the screen 1029 * at least. 1030 */ 1031 memset(ri->ri_bits, 0, 1024); 1032 1033 #ifdef SPLASHSCREEN 1034 if (splash_render(&dp->rd_splash, 1035 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1036 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1037 #endif 1038 } 1039 1040 aa.console = dp->rd_console; 1041 aa.scrdata = &dp->rd_wsscreenlist; 1042 aa.accessops = &radeonfb_accessops; 1043 aa.accesscookie = &dp->rd_vd; 1044 1045 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, 1046 CFARGS(.iattr = "wsemuldisplaydev")); 1047 1048 radeonfb_blank(dp, 0); 1049 1050 /* Initialise delayed lvds operations for backlight. */ 1051 callout_init(&dp->rd_bl_lvds_co, 0); 1052 callout_setfunc(&dp->rd_bl_lvds_co, 1053 radeonfb_lvds_callout, dp); 1054 1055 dp->rd_bl_on = 1; 1056 if (sc->sc_flags & RFB_MOB) { 1057 dp->rd_bl_level = radeonfb_get_backlight(dp); 1058 } else 1059 dp->rd_bl_level = 128; 1060 1061 radeonfb_set_backlight(dp, dp->rd_bl_level); 1062 } 1063 for (i = 0; i < RADEON_NDISPLAYS; i++) 1064 radeonfb_init_palette(&sc->sc_displays[i]); 1065 1066 if (HAS_CRTC2(sc) && !IS_AVIVO(sc)) { 1067 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1068 } 1069 1070 if (!IS_AVIVO(sc)) { 1071 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1072 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1073 } 1074 1075 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1076 radeonfb_brightness_up, TRUE); 1077 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1078 radeonfb_brightness_down, TRUE); 1079 1080 /* 1081 * if we attach a DRM we need to unmap registers in 1082 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1083 * screen blanking we only do it if needed 1084 */ 1085 sc->sc_needs_unmap = 1086 (config_found(dev, aux, radeonfb_drm_print, 1087 CFARGS(.iattr = "drm")) != NULL); 1088 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1089 1090 if (!IS_AVIVO(sc)) { 1091 PRINTREG(RADEON_CRTC_EXT_CNTL); 1092 PRINTREG(RADEON_CRTC_GEN_CNTL); 1093 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1094 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1095 PRINTREG(RADEON_DAC_CNTL2); 1096 PRINTREG(RADEON_FP_GEN_CNTL); 1097 PRINTREG(RADEON_FP2_GEN_CNTL); 1098 PRINTREG(RADEON_TMDS_CNTL); 1099 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1100 PRINTREG(RADEON_TMDS_PLL_CNTL); 1101 /* 1102 XXX: We can't print this, as it's not correctly aligned 1103 PRINTREG(RADEON_PIXCLKS_CNTL); 1104 */ 1105 } 1106 return; 1107 1108 error: 1109 if (sc->sc_biossz) 1110 free(sc->sc_bios, M_DEVBUF); 1111 1112 if (sc->sc_regsz) 1113 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1114 1115 if (sc->sc_memsz) 1116 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1117 } 1118 1119 static void 1120 radeonfb_map(struct radeonfb_softc *sc) 1121 { 1122 if (!sc->sc_mapped) { 1123 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1124 &sc->sc_regh) != 0) { 1125 aprint_error_dev(sc->sc_dev, 1126 "unable to map registers!\n"); 1127 return; 1128 } 1129 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1130 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE, 1131 &sc->sc_memh) != 0) { 1132 sc->sc_memsz = 0; 1133 aprint_error_dev(sc->sc_dev, 1134 "Unable to map frame buffer\n"); 1135 return; 1136 } 1137 sc->sc_mapped = TRUE; 1138 } 1139 } 1140 1141 static void 1142 radeonfb_unmap(struct radeonfb_softc *sc) 1143 { 1144 if (!sc->sc_needs_unmap) 1145 return; 1146 1147 if (sc->sc_mapped) { 1148 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1149 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1150 sc->sc_mapped = FALSE; 1151 } 1152 } 1153 1154 static int 1155 radeonfb_drm_print(void *aux, const char *pnp) 1156 { 1157 if (pnp) 1158 aprint_normal("drm at %s", pnp); 1159 return (UNCONF); 1160 } 1161 1162 int 1163 radeonfb_ioctl(void *v, void *vs, 1164 unsigned long cmd, void *d, int flag, struct lwp *l) 1165 { 1166 struct vcons_data *vd; 1167 struct radeonfb_display *dp; 1168 struct radeonfb_softc *sc; 1169 struct wsdisplay_param *param; 1170 struct vcons_screen *ms; 1171 1172 vd = (struct vcons_data *)v; 1173 ms = vd->active; 1174 dp = (struct radeonfb_display *)vd->cookie; 1175 sc = dp->rd_softc; 1176 1177 /* can't do these without registers being mapped */ 1178 if (!sc->sc_mapped) { 1179 switch (cmd) { 1180 case WSDISPLAYIO_GVIDEO: 1181 case WSDISPLAYIO_SVIDEO: 1182 case WSDISPLAYIO_GETCMAP: 1183 case WSDISPLAYIO_PUTCMAP: 1184 case WSDISPLAYIO_SCURSOR: 1185 case WSDISPLAYIO_GCURPOS: 1186 case WSDISPLAYIO_SCURPOS: 1187 case WSDISPLAYIO_SETPARAM: 1188 return EINVAL; 1189 } 1190 } 1191 1192 switch (cmd) { 1193 case WSDISPLAYIO_GTYPE: 1194 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1195 return 0; 1196 1197 case WSDISPLAYIO_GINFO: 1198 if (vd->active != NULL) { 1199 struct wsdisplay_fbinfo *fb; 1200 fb = (struct wsdisplay_fbinfo *)d; 1201 fb->width = dp->rd_virtx; 1202 fb->height = dp->rd_virty; 1203 fb->depth = dp->rd_bpp; 1204 fb->cmsize = 256; 1205 return 0; 1206 } else 1207 return ENODEV; 1208 case WSDISPLAYIO_GVIDEO: 1209 if (radeonfb_isblank(dp)) 1210 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1211 else 1212 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1213 return 0; 1214 1215 case WSDISPLAYIO_SVIDEO: 1216 if (dp->rd_wsmode != WSDISPLAYIO_MODE_MAPPED) { 1217 radeonfb_blank(dp, 1218 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1219 radeonfb_switch_backlight(dp, 1220 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1221 } 1222 pmf_event_inject(NULL, 1223 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ? 1224 PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF); 1225 return 0; 1226 1227 case WSDISPLAYIO_GETCMAP: 1228 if (dp->rd_bpp == 8) 1229 return radeonfb_getcmap(dp, 1230 (struct wsdisplay_cmap *)d); 1231 return EINVAL; 1232 1233 case WSDISPLAYIO_PUTCMAP: 1234 if (dp->rd_bpp == 8) 1235 return radeonfb_putcmap(dp, 1236 (struct wsdisplay_cmap *)d); 1237 return EINVAL; 1238 1239 case WSDISPLAYIO_LINEBYTES: 1240 *(unsigned *)d = dp->rd_stride; 1241 return 0; 1242 1243 case WSDISPLAYIO_SMODE: 1244 if (*(int *)d != dp->rd_wsmode) { 1245 dp->rd_wsmode = *(int *)d; 1246 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1247 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1248 radeonfb_map(sc); 1249 1250 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1251 (dp->rd_vd.active)) { 1252 radeonfb_engine_init(dp); 1253 glyphcache_wipe(&dp->rd_gc); 1254 radeonfb_init_palette(dp); 1255 radeonfb_modeswitch(dp); 1256 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1257 dp->rd_virty, dp->rd_bg); 1258 vcons_redraw_screen(dp->rd_vd.active); 1259 } 1260 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1261 radeonfb_unmap(sc); 1262 } 1263 return 0; 1264 1265 case WSDISPLAYIO_GCURMAX: 1266 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1267 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1268 return 0; 1269 1270 case WSDISPLAYIO_SCURSOR: 1271 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1272 1273 case WSDISPLAYIO_GCURSOR: 1274 return EPASSTHROUGH; 1275 1276 case WSDISPLAYIO_GCURPOS: 1277 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1278 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1279 return 0; 1280 1281 case WSDISPLAYIO_SCURPOS: 1282 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1283 1284 case WSDISPLAYIO_SSPLASH: 1285 #if defined(SPLASHSCREEN) 1286 if (*(int *)d == 1) { 1287 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1288 splash_render(&dp->rd_splash, 1289 SPLASH_F_CENTER|SPLASH_F_FILL); 1290 } else 1291 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1292 return 0; 1293 #else 1294 return ENODEV; 1295 #endif 1296 case WSDISPLAYIO_GETPARAM: 1297 param = (struct wsdisplay_param *)d; 1298 switch (param->param) { 1299 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1300 param->min = 0; 1301 param->max = 255; 1302 param->curval = dp->rd_bl_level; 1303 return 0; 1304 case WSDISPLAYIO_PARAM_BACKLIGHT: 1305 param->min = 0; 1306 param->max = RADEONFB_BACKLIGHT_MAX; 1307 param->curval = dp->rd_bl_on; 1308 return 0; 1309 } 1310 return EPASSTHROUGH; 1311 1312 case WSDISPLAYIO_SETPARAM: 1313 param = (struct wsdisplay_param *)d; 1314 switch (param->param) { 1315 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1316 radeonfb_set_backlight(dp, param->curval); 1317 return 0; 1318 case WSDISPLAYIO_PARAM_BACKLIGHT: 1319 radeonfb_switch_backlight(dp, param->curval); 1320 return 0; 1321 } 1322 return EPASSTHROUGH; 1323 1324 /* PCI config read/write passthrough. */ 1325 case PCI_IOC_CFGREAD: 1326 case PCI_IOC_CFGWRITE: 1327 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1328 1329 case WSDISPLAYIO_GET_BUSID: 1330 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1331 sc->sc_pt, d); 1332 1333 case WSDISPLAYIO_GET_EDID: { 1334 struct wsdisplayio_edid_info *ei = d; 1335 return wsdisplayio_get_edid(sc->sc_dev, ei); 1336 } 1337 1338 case WSDISPLAYIO_GET_FBINFO: { 1339 struct wsdisplayio_fbinfo *fbi = d; 1340 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1341 } 1342 1343 default: 1344 return EPASSTHROUGH; 1345 } 1346 } 1347 1348 paddr_t 1349 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1350 { 1351 struct vcons_data *vd; 1352 struct radeonfb_display *dp; 1353 struct radeonfb_softc *sc; 1354 paddr_t pa; 1355 1356 vd = (struct vcons_data *)v; 1357 dp = (struct radeonfb_display *)vd->cookie; 1358 sc = dp->rd_softc; 1359 1360 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1361 pa = bus_space_mmap(sc->sc_memt, 1362 sc->sc_memaddr, dp->rd_offset + offset, 1363 prot, BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 1364 return pa; 1365 } 1366 1367 /* 1368 * restrict all other mappings to processes with superuser privileges 1369 * or the kernel itself 1370 */ 1371 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1372 NULL, NULL, NULL, NULL) != 0) { 1373 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1374 return -1; 1375 } 1376 1377 if ((offset >= sc->sc_regaddr) && 1378 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1379 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1380 BUS_SPACE_MAP_LINEAR); 1381 } 1382 1383 if ((offset >= sc->sc_memaddr) && 1384 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1385 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1386 BUS_SPACE_MAP_LINEAR); 1387 } 1388 1389 if ((offset >= sc->sc_romaddr) && 1390 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1391 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1392 BUS_SPACE_MAP_LINEAR); 1393 } 1394 1395 #ifdef PCI_MAGIC_IO_RANGE 1396 /* allow mapping of IO space */ 1397 if ((offset >= PCI_MAGIC_IO_RANGE) && 1398 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1399 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1400 0, prot, 0); 1401 return pa; 1402 } 1403 #endif /* PCI_MAGIC_IO_RANGE */ 1404 1405 return -1; 1406 } 1407 1408 static void 1409 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1410 { 1411 bus_space_tag_t romt; 1412 bus_space_handle_t romh, biosh; 1413 bus_size_t romsz; 1414 bus_addr_t ptr; 1415 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1416 int bios_voodoo = 0; 1417 1418 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1419 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1420 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1421 return; 1422 } 1423 1424 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1425 &sc->sc_biossz); 1426 if (sc->sc_biossz != 0) goto foundit; 1427 1428 aprint_verbose("trying to read disabled BIOS...\n"); 1429 1430 bios_voodoo = 1; 1431 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1432 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1433 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1434 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1435 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1436 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1437 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1438 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1439 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1440 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1441 (RADEON_CRTC_DISP_REQ_EN_B | 1442 RADEON_CRTC_EXT_DISP_EN))); 1443 if (HAS_CRTC2(sc)) { 1444 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1445 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1446 (crtc2g & ~RADEON_CRTC2_EN) | 1447 RADEON_CRTC2_DISP_REQ_EN_B); 1448 } 1449 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1450 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1451 (RADEON_CRTC_SYNC_TRISTAT | 1452 RADEON_CRTC_DISPLAY_DIS)); 1453 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1454 &sc->sc_biossz); 1455 1456 foundit: 1457 if (sc->sc_biossz > 0) { 1458 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1459 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, 1460 sc->sc_biossz); 1461 } 1462 1463 if (bios_voodoo != 0) { 1464 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1465 if (HAS_CRTC2(sc)) { 1466 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1467 } 1468 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1469 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1470 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1471 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1472 } 1473 1474 /* unmap the PCI expansion rom */ 1475 bus_space_unmap(romt, romh, romsz); 1476 1477 /* turn off rom decoder now */ 1478 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1479 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1480 ~PCI_MAPREG_ROM_ENABLE); 1481 1482 if (sc->sc_biossz > 0) { 1483 ptr = GETBIOS16(sc, 0x48); 1484 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1485 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1486 sc->sc_flags |= RFB_ATOM; 1487 } 1488 1489 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1490 (unsigned)sc->sc_biossz >> 10, 1491 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1492 } 1493 } 1494 1495 1496 uint32_t 1497 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1498 { 1499 1500 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1501 } 1502 1503 void 1504 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1505 { 1506 1507 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1508 } 1509 1510 void 1511 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1512 { 1513 1514 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1515 } 1516 1517 void 1518 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1519 uint32_t andmask, uint32_t ormask) 1520 { 1521 int s; 1522 uint32_t val; 1523 1524 s = splhigh(); 1525 val = radeonfb_get32(sc, reg); 1526 val = (val & andmask) | ormask; 1527 radeonfb_put32(sc, reg, val); 1528 splx(s); 1529 } 1530 1531 uint32_t 1532 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1533 { 1534 int s; 1535 uint32_t val; 1536 1537 s = splhigh(); 1538 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1539 val = radeonfb_get32(sc, RADEON_MM_DATA); 1540 splx(s); 1541 1542 return (val); 1543 } 1544 1545 void 1546 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1547 { 1548 int s; 1549 1550 s = splhigh(); 1551 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1552 radeonfb_put32(sc, RADEON_MM_DATA, val); 1553 splx(s); 1554 } 1555 1556 void 1557 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1558 uint32_t andmask, uint32_t ormask) 1559 { 1560 int s; 1561 uint32_t val; 1562 1563 s = splhigh(); 1564 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1565 val = radeonfb_get32(sc, RADEON_MM_DATA); 1566 val = (val & andmask) | ormask; 1567 radeonfb_put32(sc, RADEON_MM_DATA, val); 1568 splx(s); 1569 } 1570 1571 uint32_t 1572 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1573 { 1574 int s; 1575 uint32_t val; 1576 1577 s = splhigh(); 1578 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1579 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1580 if (HAS_R300CG(sc)) 1581 radeonfb_r300cg_workaround(sc); 1582 splx(s); 1583 1584 return (val); 1585 } 1586 1587 void 1588 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1589 { 1590 int s; 1591 1592 s = splhigh(); 1593 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1594 RADEON_PLL_WR_EN); 1595 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1596 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1597 splx(s); 1598 } 1599 1600 void 1601 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1602 uint32_t andmask, uint32_t ormask) 1603 { 1604 int s; 1605 uint32_t val; 1606 1607 s = splhigh(); 1608 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1609 RADEON_PLL_WR_EN); 1610 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1611 val = (val & andmask) | ormask; 1612 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1613 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1614 splx(s); 1615 } 1616 1617 int 1618 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1619 { 1620 uint32_t saved; 1621 1622 saved = GET32(sc, reg); 1623 PUT32(sc, reg, v); 1624 if (GET32(sc, reg) != v) { 1625 return -1; 1626 } 1627 PUT32(sc, reg, saved); 1628 return 0; 1629 } 1630 1631 uintmax_t 1632 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1633 uintmax_t defval) 1634 { 1635 prop_number_t pn; 1636 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1637 if (pn == NULL) { 1638 return defval; 1639 } 1640 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1641 return prop_number_unsigned_value(pn); 1642 } 1643 1644 int 1645 radeonfb_getclocks(struct radeonfb_softc *sc) 1646 { 1647 bus_addr_t ptr; 1648 int refclk = 0; 1649 int refdiv = 0; 1650 int minpll = 0; 1651 int maxpll = 0; 1652 1653 /* load initial property values if port/board provides them */ 1654 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1655 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1656 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1657 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1658 1659 PRINTPLL(RADEON_PPLL_REF_DIV); 1660 PRINTPLL(RADEON_PPLL_DIV_0); 1661 PRINTPLL(RADEON_PPLL_DIV_1); 1662 PRINTPLL(RADEON_PPLL_DIV_2); 1663 PRINTPLL(RADEON_PPLL_DIV_3); 1664 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1665 PRINTPLL(RADEON_P2PLL_REF_DIV); 1666 PRINTPLL(RADEON_P2PLL_DIV_0); 1667 1668 if (refclk && refdiv && minpll && maxpll) 1669 goto dontprobe; 1670 1671 if (!sc->sc_biossz) { 1672 /* no BIOS */ 1673 aprint_verbose("%s: No video BIOS, using default clocks\n", 1674 XNAME(sc)); 1675 if (IS_IGP(sc)) 1676 refclk = refclk ? refclk : 1432; 1677 else 1678 refclk = refclk ? refclk : 2700; 1679 refdiv = refdiv ? refdiv : 12; 1680 minpll = minpll ? minpll : 12500; 1681 /* XXX 1682 * Need to check if the firmware or something programmed a 1683 * higher value than this, and if so, bump it. 1684 * The RV280 in my iBook is unhappy if the PLL input is less 1685 * than 360MHz 1686 */ 1687 maxpll = maxpll ? maxpll : 40000/*35000*/; 1688 } else if (IS_ATOM(sc)) { 1689 /* ATOM BIOS */ 1690 ptr = GETBIOS16(sc, 0x48); 1691 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1692 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1693 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1694 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1695 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1696 /* 1697 * ATOM BIOS doesn't supply a reference divider, so we 1698 * have to probe for it. 1699 */ 1700 if (refdiv < 2) 1701 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1702 RADEON_PPLL_REF_DIV_MASK; 1703 /* 1704 * if probe is zero, just assume one that should work 1705 * for most parts 1706 */ 1707 if (refdiv < 2) 1708 refdiv = 12; 1709 1710 } else { 1711 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1712 /* Legacy BIOS */ 1713 ptr = GETBIOS16(sc, 0x48); 1714 ptr = GETBIOS16(sc, ptr + 0x30); 1715 if (IS_R300(sc)) { 1716 refdiv = refdiv ? refdiv : 1717 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1718 R300_PPLL_REF_DIV_ACC_SHIFT; 1719 } else { 1720 refdiv = refdiv ? refdiv : 1721 tmp & RADEON_PPLL_REF_DIV_MASK; 1722 } 1723 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1724 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1725 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1726 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1727 } 1728 1729 1730 dontprobe: 1731 sc->sc_refclk = refclk * 10; 1732 sc->sc_refdiv = refdiv; 1733 sc->sc_minpll = minpll * 10; 1734 sc->sc_maxpll = maxpll * 10; 1735 return 0; 1736 } 1737 1738 int 1739 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1740 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1741 { 1742 int i; 1743 uint32_t outfreq; 1744 int div; 1745 1746 DPRINTF(("dot clock: %u\n", dotclock)); 1747 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1748 1749 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1750 continue; 1751 1752 /* 1753 * XXX 1754 * the rv350 in my last generation 14" iBook G4 produces 1755 * garbage with dividers > 4. No idea if this is a hardware 1756 * limitation or an error in the divider table. 1757 */ 1758 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1759 continue; 1760 1761 outfreq = div * dotclock; 1762 if ((outfreq >= sc->sc_minpll) && 1763 (outfreq <= sc->sc_maxpll)) { 1764 DPRINTF(("outfreq: %u\n", outfreq)); 1765 *postdivbit = 1766 ((uint32_t)radeonfb_dividers[i].mask << 16); 1767 DPRINTF(("post divider: %d (mask %x)\n", div, 1768 *postdivbit)); 1769 break; 1770 } 1771 } 1772 1773 if (div == 0) 1774 return 1; 1775 1776 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1777 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1778 return 0; 1779 } 1780 1781 #if 0 1782 #ifdef RADEONFB_DEBUG 1783 static void 1784 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1785 { 1786 char asc[17]; 1787 unsigned ptr = (unsigned)buffer; 1788 char *start = (char *)(ptr & ~0xf); 1789 char *end = (char *)(ptr + size); 1790 1791 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1792 1793 if (pfx == NULL) { 1794 pfx = ""; 1795 } 1796 1797 while (start < end) { 1798 unsigned offset = (unsigned)start & 0xf; 1799 if (offset == 0) { 1800 printf("%s%x: ", pfx, (unsigned)start); 1801 } 1802 if (((unsigned)start < ptr) || 1803 ((unsigned)start >= (ptr + size))) { 1804 printf(" "); 1805 asc[offset] = ' '; 1806 } else { 1807 printf("%02x", *(unsigned char *)start); 1808 if ((*start >= ' ') && (*start <= '~')) { 1809 asc[offset] = *start; 1810 } else { 1811 asc[offset] = '.'; 1812 } 1813 } 1814 asc[offset + 1] = 0; 1815 if (offset % 2) { 1816 printf(" "); 1817 } 1818 if (offset == 15) { 1819 printf(" %s\n", asc); 1820 } 1821 start++; 1822 } 1823 } 1824 #endif 1825 #endif 1826 1827 int 1828 radeonfb_getconnectors(struct radeonfb_softc *sc) 1829 { 1830 int i; 1831 int found = 0; 1832 1833 for (i = 0; i < 2; i++) { 1834 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1835 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1836 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1837 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1838 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1839 } 1840 1841 /* 1842 * This logic is borrowed from Xorg's radeon driver. 1843 */ 1844 if (!sc->sc_biossz) 1845 goto nobios; 1846 1847 if (IS_ATOM(sc)) { 1848 /* not done yet */ 1849 } else { 1850 uint16_t ptr; 1851 int port = 0; 1852 1853 ptr = GETBIOS16(sc, 0x48); 1854 ptr = GETBIOS16(sc, ptr + 0x50); 1855 for (i = 1; i < 4; i++) { 1856 uint16_t entry; 1857 uint8_t conn, ddc, dac, tmds; 1858 1859 /* 1860 * Parse the connector table. From reading the code, 1861 * it appears to made up of 16-bit entries for each 1862 * connector. The 16-bits are defined as: 1863 * 1864 * bits 12-15 - connector type (0 == end of table) 1865 * bits 8-11 - DDC type 1866 * bits 5-7 - ??? 1867 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1868 * bits 1-3 - ??? 1869 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1870 */ 1871 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1872 break; 1873 entry = GETBIOS16(sc, ptr + i * 2); 1874 1875 conn = (entry >> 12) & 0xf; 1876 ddc = (entry >> 8) & 0xf; 1877 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1878 RADEON_DAC_PRIMARY; 1879 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1880 RADEON_TMDS_INT; 1881 1882 if (conn == RADEON_CONN_NONE) 1883 continue; /* no connector */ 1884 1885 /* 1886 * XXX 1887 * both Mac Mini variants have both outputs wired to 1888 * the same connector and share the DDC lines 1889 */ 1890 if ((found > 0) && 1891 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1892 /* duplicate entry for same connector */ 1893 continue; 1894 } 1895 1896 /* internal DDC_DVI port gets priority */ 1897 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1898 port = 0; 1899 else 1900 port = 1; 1901 1902 sc->sc_ports[port].rp_ddc_type = 1903 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1904 sc->sc_ports[port].rp_dac_type = dac; 1905 sc->sc_ports[port].rp_conn_type = 1906 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1907 1908 sc->sc_ports[port].rp_tmds_type = tmds; 1909 1910 if ((conn != RADEON_CONN_DVI_I) && 1911 (conn != RADEON_CONN_DVI_D) && 1912 (tmds == RADEON_TMDS_INT)) 1913 sc->sc_ports[port].rp_tmds_type = 1914 RADEON_TMDS_UNKNOWN; 1915 sc->sc_ports[port].rp_number = i - 1; 1916 1917 found += (port + 1); 1918 } 1919 } 1920 1921 nobios: 1922 if (!found) { 1923 bool dvi_ext = FALSE, dvi_int = FALSE; 1924 DPRINTF(("No connector info in BIOS!\n")); 1925 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1926 "dvi-internal", &dvi_int); 1927 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1928 "dvi-external", &dvi_ext); 1929 if (dvi_ext) { 1930 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1931 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1932 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1933 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1934 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1935 sc->sc_ports[0].rp_number = 0; 1936 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1937 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1938 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1939 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1940 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1941 sc->sc_ports[1].rp_number = 1; 1942 } else if (dvi_int) { 1943 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1944 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1945 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1946 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1947 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1948 sc->sc_ports[0].rp_number = 0; 1949 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1950 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1951 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1952 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1953 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1954 sc->sc_ports[1].rp_number = 1; 1955 } else if IS_MOBILITY(sc) { 1956 /* default, port 0 = internal TMDS, port 1 = CRT */ 1957 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1958 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1959 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1960 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1961 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1962 sc->sc_ports[0].rp_number = 0; 1963 1964 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1965 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1966 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1967 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1968 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1969 sc->sc_ports[1].rp_number = 1; 1970 } else { 1971 /* default, port 0 = DVI, port 1 = CRT */ 1972 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1973 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1974 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1975 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1976 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1977 sc->sc_ports[0].rp_number = 0; 1978 1979 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1980 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1981 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1982 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1983 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1984 sc->sc_ports[1].rp_number = 1; 1985 } 1986 } 1987 1988 /* 1989 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1990 * these chips should use TVDAC for the VGA port. 1991 */ 1992 if (HAS_SDAC(sc)) { 1993 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1994 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1995 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1996 } else { 1997 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1998 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1999 } 2000 } else if (!HAS_CRTC2(sc)) { 2001 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 2002 } 2003 2004 for (i = 0; i < 2; i++) { 2005 char edid[128], edid_port_str[7] = "EDID:"; 2006 uint8_t ddc; 2007 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 2008 prop_data_t edid_data; 2009 2010 DPRINTF(("Port #%d:\n", i)); 2011 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 2012 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 2013 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 2014 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 2015 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 2016 2017 sc->sc_ports[i].rp_edid_valid = 0; 2018 /* 2019 * First look for static EDID data 2020 * Try "EDID:port" then "EDID" 2021 */ 2022 snprintf(&edid_port_str[5], 2, "%d", i); 2023 edid_data = prop_dictionary_get(device_properties( 2024 sc->sc_dev), edid_port_str); 2025 if (edid_data == NULL) 2026 edid_data = prop_dictionary_get(device_properties( 2027 sc->sc_dev), "EDID"); 2028 if (edid_data != NULL) { 2029 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 2030 memcpy(edid, prop_data_value(edid_data), 128); 2031 if (edid_parse(edid, eip) == 0) { 2032 2033 sc->sc_ports[i].rp_edid_valid = 1; 2034 #ifdef RADEONFB_DEBUG 2035 edid_print(eip); 2036 #endif 2037 } 2038 } 2039 /* if we didn't find any we'll try to talk to the monitor */ 2040 if (sc->sc_ports[i].rp_edid_valid != 1) { 2041 2042 ddc = sc->sc_ports[i].rp_ddc_type; 2043 if (ddc != RADEON_DDC_NONE) { 2044 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 2045 == 0) && (edid_parse(edid, eip) == 0)) { 2046 2047 sc->sc_ports[i].rp_edid_valid = 1; 2048 #ifdef RADEONFB_DEBUG 2049 edid_print(eip); 2050 #endif 2051 } 2052 } 2053 } 2054 } 2055 2056 return found; 2057 } 2058 2059 int 2060 radeonfb_gettmds(struct radeonfb_softc *sc) 2061 { 2062 int i; 2063 2064 if (!sc->sc_biossz) { 2065 goto nobios; 2066 } 2067 2068 if (IS_ATOM(sc)) { 2069 /* XXX: not done yet */ 2070 } else { 2071 uint16_t ptr; 2072 int n; 2073 2074 ptr = GETBIOS16(sc, 0x48); 2075 ptr = GETBIOS16(sc, ptr + 0x34); 2076 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2077 if (GETBIOS8(sc, ptr) == 3) { 2078 /* revision three table */ 2079 n = GETBIOS8(sc, ptr + 5) + 1; 2080 n = uimin(n, 4); 2081 2082 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2083 for (i = 0; i < n; i++) { 2084 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2085 ptr + i * 10 + 8); 2086 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2087 ptr + i * 10 + 0x10); 2088 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2089 sc->sc_tmds_pll[i].rtp_freq, 2090 sc->sc_tmds_pll[i].rtp_pll)); 2091 } 2092 return 0; 2093 } 2094 } 2095 2096 nobios: 2097 DPRINTF(("no suitable DFP table present\n")); 2098 for (i = 0; 2099 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2100 i++) { 2101 int j; 2102 2103 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2104 continue; 2105 2106 for (j = 0; j < 4; j++) { 2107 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2108 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2109 sc->sc_tmds_pll[j].rtp_freq, 2110 sc->sc_tmds_pll[j].rtp_pll)); 2111 } 2112 return 0; 2113 } 2114 2115 return -1; 2116 } 2117 2118 const struct videomode * 2119 radeonfb_modelookup(const char *name) 2120 { 2121 int i; 2122 /* Use a default mode in case we don't find a matching mode */ 2123 const char *vm = "1024x768x60"; 2124 const struct videomode *vmp = NULL; 2125 2126 for (i = 0; i < videomode_count; i++) { 2127 if (!strcmp(name, videomode_list[i].name)) 2128 return &videomode_list[i]; 2129 if (!strcmp(vm, videomode_list[i].name)) 2130 vmp = &videomode_list[i]; 2131 } 2132 return vmp; 2133 } 2134 2135 void 2136 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2137 { 2138 if (crtc) { 2139 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2140 RADEON_P2PLL_ATOMIC_UPDATE_R); 2141 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2142 } else { 2143 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2144 RADEON_PPLL_ATOMIC_UPDATE_R); 2145 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2146 } 2147 } 2148 2149 void 2150 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2151 { 2152 int i; 2153 2154 for (i = 10000; i; i--) { 2155 if (crtc) { 2156 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2157 RADEON_P2PLL_ATOMIC_UPDATE_R) 2158 break; 2159 } else { 2160 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2161 RADEON_PPLL_ATOMIC_UPDATE_R) 2162 break; 2163 } 2164 } 2165 } 2166 2167 void 2168 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2169 { 2170 uint32_t pbit = 0; 2171 uint32_t feed = 0; 2172 uint32_t data, refdiv, div0, r2xxref; 2173 2174 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2175 2176 if (crtc == 0) { 2177 2178 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2179 2180 /* 2181 * XXX 2182 * the RV350 in my last generation iBook G4 behaves like an 2183 * r2xx here - try to detect that and not screw up the reference 2184 * divider. 2185 * xf86-video-radeon just skips PLL programming altogether 2186 * on iBooks, probably for this reason. 2187 */ 2188 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2189 if (IS_R300(sc) && (r2xxref != refdiv)) { 2190 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2191 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2192 } else { 2193 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2194 sc->sc_refdiv; 2195 } 2196 DPRINTF(("refdiv %08x\n", refdiv)); 2197 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2198 DPRINTF(("div0 %08x\n", div0)); 2199 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2200 RADEON_PPLL_POST3_DIV_MASK); 2201 div0 |= pbit; 2202 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2203 DPRINTF(("div0 %08x\n", div0)); 2204 2205 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2206 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2207 /* 2208 * nothing to do here, the PLL is already where we 2209 * want it 2210 */ 2211 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2212 ~RADEON_PLL_DIV_SEL); 2213 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2214 return; 2215 } 2216 2217 /* alright, we do need to reprogram stuff */ 2218 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2219 RADEON_VCLK_SRC_SEL_CPUCLK, 2220 ~RADEON_VCLK_SRC_SEL_MASK); 2221 2222 /* put vclk into reset, use atomic updates */ 2223 SETPLL(sc, RADEON_PPLL_CNTL, 2224 RADEON_PPLL_REFCLK_SEL | 2225 RADEON_PPLL_FBCLK_SEL | 2226 RADEON_PPLL_RESET | 2227 RADEON_PPLL_ATOMIC_UPDATE_EN | 2228 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2229 2230 /* select clock 0 */ 2231 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2232 ~RADEON_PLL_DIV_SEL); 2233 2234 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2235 2236 /* xf86-video-radeon does this, not sure why */ 2237 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2238 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2239 2240 /* use the atomic update */ 2241 radeonfb_pllwriteupdate(sc, crtc); 2242 2243 /* and wait for it to complete */ 2244 radeonfb_pllwaitatomicread(sc, crtc); 2245 2246 /* program HTOTAL (why?) */ 2247 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2248 2249 /* drop reset */ 2250 CLRPLL(sc, RADEON_PPLL_CNTL, 2251 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2252 RADEON_PPLL_ATOMIC_UPDATE_EN | 2253 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2254 2255 PRINTPLL(RADEON_PPLL_CNTL); 2256 PRINTPLL(RADEON_PPLL_REF_DIV); 2257 PRINTPLL(RADEON_PPLL_DIV_3); 2258 2259 /* give clock time to lock */ 2260 delay(50000); 2261 2262 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2263 RADEON_VCLK_SRC_SEL_PPLLCLK, 2264 ~RADEON_VCLK_SRC_SEL_MASK); 2265 2266 /* 2267 * Ungate the CRTC1 pixel clocks 2268 */ 2269 SETPLL(sc, RADEON_VCLK_ECP_CNTL, 2270 RADEON_PIXCLK_ALWAYS_ONb | 2271 RADEON_PIXCLK_DAC_ALWAYS_ONb); 2272 PRINTPLL(RADEON_VCLK_ECP_CNTL); 2273 2274 } else { 2275 2276 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2277 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2278 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2279 2280 /* put vclk into reset, use atomic updates */ 2281 SETPLL(sc, RADEON_P2PLL_CNTL, 2282 RADEON_P2PLL_RESET | 2283 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2284 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2285 2286 /* program reference divider */ 2287 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2288 ~RADEON_P2PLL_REF_DIV_MASK); 2289 2290 /* program feedback and post dividers */ 2291 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2292 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2293 RADEON_P2PLL_POST0_DIV_MASK); 2294 data |= pbit; 2295 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2296 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2297 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2298 2299 PRINTPLL(RADEON_P2PLL_REF_DIV); 2300 PRINTPLL(RADEON_P2PLL_DIV_0); 2301 2302 /* use the atomic update */ 2303 radeonfb_pllwriteupdate(sc, crtc); 2304 2305 /* and wait for it to complete */ 2306 radeonfb_pllwaitatomicread(sc, crtc); 2307 2308 /* program HTOTAL (why?) */ 2309 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2310 2311 /* drop reset */ 2312 CLRPLL(sc, RADEON_P2PLL_CNTL, 2313 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2314 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2315 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2316 2317 /* allow time for clock to lock */ 2318 delay(50000); 2319 2320 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2321 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2322 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2323 2324 /* 2325 * Ungate the CRTC2 and digital-output pixel clocks 2326 */ 2327 SETPLL(sc, RADEON_PIXCLKS_CNTL, 2328 RADEON_PIX2CLK_ALWAYS_ONb | 2329 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 2330 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 2331 RADEON_PIXCLK_GV_ALWAYS_ONb | 2332 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 2333 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 2334 PRINTPLL(RADEON_PIXCLKS_CNTL); 2335 } 2336 PRINTREG(RADEON_CRTC_MORE_CNTL); 2337 } 2338 2339 void 2340 radeonfb_modeswitch(struct radeonfb_display *dp) 2341 { 2342 struct radeonfb_softc *sc = dp->rd_softc; 2343 int i; 2344 2345 if (IS_AVIVO(sc)) { 2346 /* 2347 * no actual mode setting yet, we just make sure the CRTCs 2348 * point at the right memory ranges and use the same pitch 2349 * for the drawing engine 2350 */ 2351 if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) { 2352 CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2353 dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH); 2354 PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2355 } 2356 if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) { 2357 CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2358 dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH); 2359 PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2360 } 2361 return; 2362 } 2363 2364 /* blank the display while we switch modes */ 2365 //radeonfb_blank(dp, 1); 2366 2367 #if 0 2368 SET32(sc, RADEON_CRTC_EXT_CNTL, 2369 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2370 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2371 #endif 2372 2373 /* these registers might get in the way... */ 2374 PUT32(sc, RADEON_OVR_CLR, 0); 2375 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2376 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2377 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2378 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2379 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2380 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2381 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2382 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2383 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2384 2385 for (i = 0; i < dp->rd_ncrtcs; i++) 2386 radeonfb_setcrtc(dp, i); 2387 2388 #if 0 2389 /* 2390 * DVO chip voodoo from xf86-video-radeon 2391 * apparently this is needed for some powerbooks with DVI outputs 2392 */ 2393 2394 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2395 int n = 0; 2396 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2397 for (i = 0; i < 5; i++) 2398 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2399 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2400 printf("n = %d\n", n); 2401 #endif 2402 2403 /* activate the display */ 2404 radeonfb_blank(dp, 0); 2405 } 2406 2407 void 2408 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2409 { 2410 int crtc, flags = 0; 2411 struct videomode *mode; 2412 struct radeonfb_softc *sc; 2413 struct radeonfb_crtc *cp; 2414 uint32_t v, hd, vd; 2415 uint32_t gencntl; 2416 uint32_t htotaldisp; 2417 uint32_t hsyncstrt; 2418 uint32_t vtotaldisp; 2419 uint32_t vsyncstrt; 2420 uint32_t fphsyncstrt; 2421 uint32_t fpvsyncstrt; 2422 uint32_t fphtotaldisp; 2423 uint32_t fpvtotaldisp; 2424 uint32_t pitch; 2425 2426 sc = dp->rd_softc; 2427 2428 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2429 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2430 flags |= NO_ODD_FBDIV; 2431 } 2432 2433 cp = &dp->rd_crtcs[index]; 2434 crtc = cp->rc_number; 2435 mode = &cp->rc_videomode; 2436 2437 #if 1 2438 pitch = dp->rd_stride / dp->rd_bpp; 2439 #else 2440 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2441 (sc->sc_maxbpp * 8)); 2442 #endif 2443 switch (crtc) { 2444 case 0: 2445 gencntl = RADEON_CRTC_GEN_CNTL; 2446 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2447 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2448 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2449 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2450 /* should probably leave those alone on non-LVDS */ 2451 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2452 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2453 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2454 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2455 break; 2456 case 1: 2457 gencntl = RADEON_CRTC2_GEN_CNTL; 2458 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2459 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2460 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2461 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2462 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2463 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2464 /* XXX these registers don't seem to exist */ 2465 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2466 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2467 break; 2468 default: 2469 panic("Bad CRTC!"); 2470 break; 2471 } 2472 2473 /* 2474 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2475 */ 2476 /* only bother with 32bpp and 8bpp */ 2477 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2478 2479 if (crtc == 1) { 2480 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2481 } else { 2482 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2483 } 2484 2485 if (mode->flags & VID_DBLSCAN) 2486 v |= RADEON_CRTC2_DBL_SCAN_EN; 2487 2488 if (mode->flags & VID_INTERLACE) 2489 v |= RADEON_CRTC2_INTERLACE_EN; 2490 2491 if (mode->flags & VID_CSYNC) { 2492 v |= RADEON_CRTC2_CSYNC_EN; 2493 if (crtc == 1) 2494 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2495 } 2496 2497 PUT32(sc, gencntl, v); 2498 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2499 2500 /* 2501 * CRTC_EXT_CNTL - set ATI linear and EXT_CNT. Do NOT preserve 2502 * HSYNC_DIS/VSYNC_DIS: on cards not POSTed by system firmware 2503 * (RADEONFB_BIOS_INIT) the BIOS init tables may leave the syncs 2504 * disabled, and nothing else along the modeswitch path would 2505 * re-enable them... (Would result in black screen) 2506 */ 2507 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2508 if (crtc == 0) { 2509 v &= RADEON_CRTC_DISPLAY_DIS; 2510 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2511 if (mode->flags & VID_CSYNC) 2512 v |= RADEON_CRTC_VSYNC_TRISTAT; 2513 } 2514 /* unconditional turn on CRT, in case first CRTC is DFP */ 2515 v |= RADEON_CRTC_CRT_ON; 2516 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2517 PRINTREG(RADEON_CRTC_EXT_CNTL); 2518 2519 hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8; 2520 vd = (GET32(sc, vtotaldisp) >> 16) + 1; 2521 DPRINTF(("res %d x %d\n", hd, vd)); 2522 2523 if ((hd != mode->hdisplay) || (vd != mode->vdisplay)) { 2524 2525 /* 2526 * H_TOTAL_DISP 2527 */ 2528 v = ((mode->hdisplay / 8) - 1) << 16; 2529 v |= (mode->htotal / 8) - 1; 2530 PRINTREG(RADEON_CRTC_H_TOTAL_DISP); 2531 PUT32(sc, htotaldisp, v); 2532 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2533 if (fphtotaldisp) { 2534 PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP); 2535 PUT32(sc, fphtotaldisp, v); 2536 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2537 } 2538 /* 2539 * H_SYNC_STRT_WID 2540 */ 2541 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2542 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2543 if (mode->flags & VID_NHSYNC) 2544 v |= RADEON_CRTC_H_SYNC_POL; 2545 PUT32(sc, hsyncstrt, v); 2546 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2547 if (fphsyncstrt) { 2548 PUT32(sc, fphsyncstrt, v); 2549 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2550 } 2551 2552 /* 2553 * V_TOTAL_DISP 2554 */ 2555 v = ((mode->vdisplay - 1) << 16); 2556 v |= (mode->vtotal - 1); 2557 PUT32(sc, vtotaldisp, v); 2558 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2559 if (fpvtotaldisp) { 2560 PUT32(sc, fpvtotaldisp, v); 2561 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2562 } 2563 2564 /* 2565 * V_SYNC_STRT_WID 2566 */ 2567 v = ((mode->vsync_end - mode->vsync_start) << 16); 2568 v |= (mode->vsync_start - 1); 2569 if (mode->flags & VID_NVSYNC) 2570 v |= RADEON_CRTC_V_SYNC_POL; 2571 PUT32(sc, vsyncstrt, v); 2572 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2573 if (fpvsyncstrt) { 2574 PUT32(sc, fpvsyncstrt, v); 2575 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2576 } 2577 } 2578 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2579 2580 switch (crtc) { 2581 case 0: 2582 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2583 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2584 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2585 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2586 2587 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2588 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2589 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2590 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2591 PRINTREG(RADEON_CRTC_EXT_CNTL); 2592 PRINTREG(RADEON_CRTC_GEN_CNTL); 2593 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2594 break; 2595 2596 case 1: 2597 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2598 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2599 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2600 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2601 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2602 RADEON_CRTC2_VSYNC_DIS | 2603 RADEON_CRTC2_HSYNC_DIS | 2604 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2605 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2606 break; 2607 } 2608 2609 /* 2610 * Program the TMDS PLL for this dot clock - handle cards that 2611 * never POSTed. 2612 */ 2613 if (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) { 2614 int i; 2615 2616 for (i = 0; i < 4; i++) { 2617 if ((uint32_t)(mode->dot_clock / 10) <= 2618 sc->sc_tmds_pll[i].rtp_freq) { 2619 uint32_t tpll = sc->sc_tmds_pll[i].rtp_pll; 2620 2621 /* 2622 * RV280 wants bit 22 set here, the bit 2623 * reads back inverted, DON'T trust the 2624 * readback! 2625 */ 2626 if (sc->sc_family == RADEON_RV280) 2627 tpll |= (1 << 22); 2628 PUT32(sc, RADEON_TMDS_PLL_CNTL, tpll); 2629 PRINTREG(RADEON_TMDS_PLL_CNTL); 2630 break; 2631 } 2632 } 2633 } 2634 } 2635 2636 int 2637 radeonfb_isblank(struct radeonfb_display *dp) 2638 { 2639 struct radeonfb_softc *sc = dp->rd_softc; 2640 uint32_t reg, mask; 2641 2642 if(!dp->rd_softc->sc_mapped) 2643 return 1; 2644 2645 if (IS_AVIVO(sc)) { 2646 reg = GET32(sc, AVIVO_D1CRTC_CONTROL); 2647 return ((reg & AVIVO_CRTC_EN) == 0); 2648 } 2649 2650 if (dp->rd_crtcs[0].rc_number) { 2651 reg = RADEON_CRTC2_GEN_CNTL; 2652 mask = RADEON_CRTC2_DISP_DIS; 2653 } else { 2654 reg = RADEON_CRTC_EXT_CNTL; 2655 mask = RADEON_CRTC_DISPLAY_DIS; 2656 } 2657 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2658 } 2659 2660 void 2661 radeonfb_blank(struct radeonfb_display *dp, int blank) 2662 { 2663 struct radeonfb_softc *sc = dp->rd_softc; 2664 uint32_t reg, mask; 2665 uint32_t fpreg, fpval; 2666 int i; 2667 2668 2669 if (!sc->sc_mapped) 2670 return; 2671 2672 if(IS_AVIVO(sc)) { 2673 2674 /* 2675 * XXX 2676 * I don't know how to turn the sync outputs off for DPMS 2677 * power control, so for now just turn the entire CRTC off 2678 */ 2679 if (blank) { 2680 CLR32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN); 2681 CLR32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN); 2682 } else { 2683 SET32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN); 2684 SET32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN); 2685 } 2686 return; 2687 } 2688 /* non-AVIVO case */ 2689 for (i = 0; i < dp->rd_ncrtcs; i++) { 2690 2691 if (dp->rd_crtcs[i].rc_number) { 2692 reg = RADEON_CRTC2_GEN_CNTL; 2693 mask = RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS | 2694 RADEON_CRTC2_VSYNC_DIS; 2695 fpreg = RADEON_FP2_GEN_CNTL; 2696 fpval = RADEON_FP2_ON; 2697 } else { 2698 reg = RADEON_CRTC_EXT_CNTL; 2699 mask = RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | 2700 RADEON_CRTC_VSYNC_DIS; 2701 fpreg = RADEON_FP_GEN_CNTL; 2702 fpval = RADEON_FP_FPON; 2703 } 2704 2705 if (blank) { 2706 SET32(sc, reg, mask); 2707 CLR32(sc, fpreg, fpval); 2708 } else { 2709 CLR32(sc, reg, mask); 2710 SET32(sc, fpreg, fpval); 2711 } 2712 } 2713 PRINTREG(RADEON_FP_GEN_CNTL); 2714 PRINTREG(RADEON_FP2_GEN_CNTL); 2715 } 2716 2717 void 2718 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2719 long *defattr) 2720 { 2721 struct radeonfb_display *dp = cookie; 2722 struct rasops_info *ri = &scr->scr_ri; 2723 2724 /* initialize font subsystem */ 2725 wsfont_init(); 2726 2727 scr->scr_flags |= VCONS_LOADFONT; 2728 2729 DPRINTF(("init screen called, existing %d\n", existing)); 2730 2731 ri->ri_depth = dp->rd_bpp; 2732 ri->ri_width = dp->rd_virtx; 2733 ri->ri_height = dp->rd_virty; 2734 ri->ri_stride = dp->rd_stride; 2735 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 2736 switch (ri->ri_depth) { 2737 case 8: 2738 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2739 break; 2740 case 32: 2741 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2742 /* we run radeons in RGB even on SPARC hardware */ 2743 ri->ri_rnum = 8; 2744 ri->ri_gnum = 8; 2745 ri->ri_bnum = 8; 2746 ri->ri_rpos = 16; 2747 ri->ri_gpos = 8; 2748 ri->ri_bpos = 0; 2749 break; 2750 } 2751 2752 ri->ri_bits = (void *)dp->rd_fbptr; 2753 2754 #ifdef VCONS_DRAW_INTR 2755 scr->scr_flags |= VCONS_DONT_READ; 2756 #endif 2757 2758 if (existing) { 2759 ri->ri_flg |= RI_CLEAR; 2760 2761 /* start a modeswitch now */ 2762 //radeonfb_modeswitch(dp); 2763 } 2764 2765 /* 2766 * XXX: font selection should be based on properties, with some 2767 * normal/reasonable default. 2768 */ 2769 2770 /* initialize and look for an initial font */ 2771 rasops_init(ri, 0, 0); 2772 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2773 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2774 2775 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2776 dp->rd_virtx / ri->ri_font->fontwidth); 2777 2778 /* enable acceleration */ 2779 dp->rd_putchar = ri->ri_ops.putchar; 2780 ri->ri_ops.copyrows = radeonfb_copyrows; 2781 ri->ri_ops.copycols = radeonfb_copycols; 2782 ri->ri_ops.eraserows = radeonfb_eraserows; 2783 ri->ri_ops.erasecols = radeonfb_erasecols; 2784 ri->ri_ops.allocattr = radeonfb_allocattr; 2785 /* pick a putchar method based on font and Radeon model */ 2786 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2787 /* got a bitmap font */ 2788 #if !defined(RADEONFB_ALWAYS_ACCEL_PUTCHAR) 2789 if (IS_R300(dp->rd_softc) && 0) { 2790 /* 2791 * radeonfb_putchar() doesn't work right on some R3xx 2792 * so we use software drawing here, the wrapper just 2793 * makes sure the engine is idle before scribbling 2794 * into vram 2795 */ 2796 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2797 } else 2798 #endif 2799 ri->ri_ops.putchar = radeonfb_putchar; 2800 } else { 2801 /* got an alpha font */ 2802 switch(ri->ri_depth) { 2803 case 32: 2804 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2805 break; 2806 case 8: 2807 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2808 break; 2809 default: 2810 /* XXX this should never happen */ 2811 panic("%s: depth is not 8 or 32 but we got an" \ 2812 " alpha font?!", __func__); 2813 } 2814 } 2815 ri->ri_ops.cursor = radeonfb_cursor; 2816 } 2817 2818 static uint32_t 2819 radeonfb_avivo_INMC(struct radeonfb_softc *sc, uint32_t addr) 2820 { 2821 uint32_t data; 2822 2823 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2824 (void)GET32(sc, AVIVO_MC_INDEX); 2825 data = GET32(sc, AVIVO_MC_DATA); 2826 PUT32(sc, AVIVO_MC_INDEX, 0); 2827 (void)GET32(sc, AVIVO_MC_INDEX); 2828 return data; 2829 } 2830 2831 static void 2832 radeonfb_avivo_OUTMC(struct radeonfb_softc *sc, uint32_t addr, uint32_t data) 2833 { 2834 2835 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2836 (void)GET32(sc, AVIVO_MC_INDEX); 2837 PUT32(sc, AVIVO_MC_DATA, data); 2838 PUT32(sc, AVIVO_MC_INDEX, 0); 2839 (void)GET32(sc, AVIVO_MC_INDEX); 2840 } 2841 2842 void 2843 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2844 { 2845 uint32_t gen = 0, ext = 0, gen2 = 0; 2846 uint32_t agploc, aperbase, apersize, mcfbloc; 2847 2848 2849 if (IS_AVIVO(sc)) { 2850 agploc = radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION); 2851 } else { 2852 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2853 /* XXX */ 2854 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2855 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2856 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2857 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2858 #if 0 2859 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2860 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2861 #endif 2862 2863 if (HAS_CRTC2(sc)) { 2864 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2865 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2866 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2867 } 2868 2869 delay(100000); 2870 } 2871 2872 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2873 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2874 2875 2876 mcfbloc = (aperbase >> 16) | 2877 ((aperbase + (apersize - 1)) & 0xffff0000); 2878 2879 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2880 sc->sc_memsz = apersize; 2881 DPRINTF(("aperbase = %08x\n", aperbase)); 2882 2883 if (((agploc & 0xffff) << 16) != 2884 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2885 agploc = mcfbloc & 0xffff0000U; 2886 agploc |= ((agploc + 0x10000) >> 16); 2887 } 2888 2889 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2890 2891 if (IS_AVIVO(sc)) { 2892 radeonfb_avivo_OUTMC(sc, R520_MC_FB_LOCATION, mcfbloc); 2893 radeonfb_avivo_OUTMC(sc, R520_MC_AGP_LOCATION, agploc); 2894 PRINTREG(AVIVO_HDP_FB_LOCATION); 2895 DPRINTF((" FB loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_FB_LOCATION))); 2896 DPRINTF(("AGP loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION))); 2897 } else { 2898 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2899 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2900 PRINTREG(RADEON_MC_FB_LOCATION); 2901 PRINTREG(RADEON_MC_AGP_LOCATION); 2902 2903 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2904 2905 if (HAS_CRTC2(sc)) 2906 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2907 2908 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2909 delay(100000); 2910 2911 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2912 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2913 2914 if (HAS_CRTC2(sc)) 2915 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2916 } 2917 #if 0 2918 /* XXX: what is this AGP garbage? :-) */ 2919 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2920 #endif 2921 } 2922 2923 void 2924 radeonfb_init_misc(struct radeonfb_softc *sc) 2925 { 2926 PUT32(sc, RADEON_BUS_CNTL, 2927 RADEON_BUS_MASTER_DIS | 2928 RADEON_BUS_PREFETCH_MODE_ACT | 2929 RADEON_BUS_PCI_READ_RETRY_EN | 2930 RADEON_BUS_PCI_WRT_RETRY_EN | 2931 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2932 RADEON_BUS_MSTR_RD_MULT | 2933 RADEON_BUS_MSTR_RD_LINE | 2934 RADEON_BUS_RD_DISCARD_EN | 2935 RADEON_BUS_MSTR_DISCONNECT_EN | 2936 RADEON_BUS_READ_BURST); 2937 2938 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2939 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2940 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2941 PUT32(sc, RADEON_RBBM_CNTL, 2942 (3 << RADEON_RB_SETTLE_SHIFT) | 2943 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2944 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2945 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2946 2947 /* XXX: figure out what these mean! */ 2948 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2949 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2950 #if 0 2951 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2952 #endif 2953 2954 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2955 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2956 } 2957 2958 static void 2959 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2960 { 2961 struct radeonfb_softc *sc = dp->rd_softc; 2962 int crtc, cc; 2963 uint32_t vclk; 2964 2965 if (IS_AVIVO(sc)) { 2966 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2967 crtc = dp->rd_crtcs[cc].rc_number; 2968 2969 if (crtc) 2970 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1); 2971 else 2972 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0); 2973 2974 PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx); 2975 PUT32(sc, AVIVO_DC_LUT_30_COLOR, 2976 (r << 22) | (g << 12) | (b << 2)); 2977 } 2978 } else { 2979 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2980 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, 2981 vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2982 2983 /* init the palette for every CRTC used by this display */ 2984 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2985 crtc = dp->rd_crtcs[cc].rc_number; 2986 2987 if (crtc) 2988 SET32(sc, RADEON_DAC_CNTL2, 2989 RADEON_DAC2_PALETTE_ACC_CTL); 2990 else 2991 CLR32(sc, RADEON_DAC_CNTL2, 2992 RADEON_DAC2_PALETTE_ACC_CTL); 2993 2994 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2995 PUT32(sc, RADEON_PALETTE_30_DATA, 2996 (r << 22) | (g << 12) | (b << 2)); 2997 } 2998 2999 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 3000 } 3001 } 3002 3003 /* 3004 * This loads a linear color map for true color. 3005 */ 3006 void 3007 radeonfb_init_palette(struct radeonfb_display *dp) 3008 { 3009 int i; 3010 3011 #define DAC_WIDTH ((1 << 10) - 1) 3012 #define CLUT_WIDTH ((1 << 8) - 1) 3013 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 3014 3015 if (dp->rd_bpp == 8) { 3016 3017 /* R3G3B2 palette */ 3018 uint32_t tmp, r, g, b; 3019 3020 for (i = 0; i <= CLUT_WIDTH; ++i) { 3021 tmp = i & 0xe0; 3022 3023 /* 3024 * replicate bits so 0xe0 maps to a red value of 0xff 3025 * in order to make white look actually white 3026 */ 3027 tmp |= (tmp >> 3) | (tmp >> 6); 3028 r = tmp; 3029 3030 tmp = (i & 0x1c) << 3; 3031 tmp |= (tmp >> 3) | (tmp >> 6); 3032 g = tmp; 3033 3034 tmp = (i & 0x03) << 6; 3035 tmp |= tmp >> 2; 3036 tmp |= tmp >> 4; 3037 b = tmp; 3038 3039 dp->rd_cmap_red[i] = r; 3040 dp->rd_cmap_green[i] = g; 3041 dp->rd_cmap_blue[i] = b; 3042 radeonfb_putpal(dp, i, r, g, b); 3043 } 3044 } else { 3045 /* linear ramp */ 3046 for (i = 0; i <= CLUT_WIDTH; ++i) { 3047 radeonfb_putpal(dp, i, i, i, i); 3048 } 3049 } 3050 } 3051 3052 static int 3053 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 3054 { 3055 u_char *r, *g, *b; 3056 u_int index = cm->index; 3057 u_int count = cm->count; 3058 int i, error; 3059 u_char rbuf[256], gbuf[256], bbuf[256]; 3060 3061 #ifdef GENFB_DEBUG 3062 aprint_debug("putcmap: %d %d\n",index, count); 3063 #endif 3064 if (index >= 256 || count > 256 - index) 3065 return EINVAL; 3066 error = copyin(cm->red, &rbuf[index], count); 3067 if (error) 3068 return error; 3069 error = copyin(cm->green, &gbuf[index], count); 3070 if (error) 3071 return error; 3072 error = copyin(cm->blue, &bbuf[index], count); 3073 if (error) 3074 return error; 3075 3076 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 3077 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 3078 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 3079 3080 r = &dp->rd_cmap_red[index]; 3081 g = &dp->rd_cmap_green[index]; 3082 b = &dp->rd_cmap_blue[index]; 3083 3084 for (i = 0; i < count; i++) { 3085 radeonfb_putpal(dp, index, *r, *g, *b); 3086 index++; 3087 r++, g++, b++; 3088 } 3089 return 0; 3090 } 3091 3092 static int 3093 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 3094 { 3095 u_int index = cm->index; 3096 u_int count = cm->count; 3097 int error; 3098 3099 if (index >= 256 || count > 256 - index) 3100 return EINVAL; 3101 3102 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 3103 if (error) 3104 return error; 3105 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 3106 if (error) 3107 return error; 3108 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 3109 if (error) 3110 return error; 3111 3112 return 0; 3113 } 3114 3115 /* 3116 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 3117 */ 3118 void 3119 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 3120 { 3121 uint32_t tmp, save; 3122 3123 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3124 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 3125 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 3126 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 3127 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 3128 } 3129 3130 /* 3131 * Acceleration entry points. 3132 */ 3133 3134 /* this one draws characters using bitmap fonts */ 3135 static void 3136 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 3137 { 3138 struct rasops_info *ri = cookie; 3139 struct vcons_screen *scr = ri->ri_hw; 3140 struct radeonfb_display *dp = scr->scr_cookie; 3141 struct radeonfb_softc *sc = dp->rd_softc; 3142 struct wsdisplay_font *font = PICK_FONT(ri, c); 3143 uint32_t w, h; 3144 int xd, yd, offset, i; 3145 uint32_t bg, fg, gmc; 3146 uint32_t reg; 3147 uint8_t *data8; 3148 uint16_t *data16; 3149 uint32_t *data32; 3150 void *data; 3151 3152 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3153 return; 3154 3155 if (!CHAR_IN_FONT(c, font)) 3156 return; 3157 3158 w = font->fontwidth; 3159 h = font->fontheight; 3160 3161 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3162 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3163 3164 xd = ri->ri_xorigin + col * w; 3165 yd = ri->ri_yorigin + row * h; 3166 3167 if (c == 0x20) { 3168 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3169 if (attr & WSATTR_UNDERLINE) 3170 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3171 return; 3172 } 3173 data = WSFONT_GLYPH(c, font); 3174 3175 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3176 3177 radeonfb_wait_fifo(sc, 9); 3178 3179 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3180 RADEON_GMC_BRUSH_NONE | 3181 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 3182 RADEON_GMC_DST_CLIPPING | 3183 RADEON_ROP3_S | 3184 RADEON_DP_SRC_SOURCE_HOST_DATA | 3185 RADEON_GMC_CLR_CMP_CNTL_DIS | 3186 RADEON_GMC_WR_MSK_DIS | 3187 gmc); 3188 3189 PUT32(sc, RADEON_SC_LEFT, xd); 3190 PUT32(sc, RADEON_SC_RIGHT, xd + w); 3191 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 3192 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 3193 PUT32(sc, RADEON_DP_CNTL, 3194 RADEON_DST_X_LEFT_TO_RIGHT | 3195 RADEON_DST_Y_TOP_TO_BOTTOM); 3196 3197 PUT32(sc, RADEON_SRC_X_Y, 0); 3198 offset = 32 - (font->stride << 3); 3199 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 3200 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 3201 3202 radeonfb_wait_fifo(sc, h); 3203 if (attr & WSATTR_HILIT) { 3204 switch (font->stride) { 3205 case 1: { 3206 data8 = data; 3207 for (i = 0; i < h; i++) { 3208 reg = *data8; 3209 reg |= reg >> 1; 3210 #if BYTE_ORDER == LITTLE_ENDIAN 3211 reg = reg << 24; 3212 #endif 3213 bus_space_write_stream_4(sc->sc_regt, 3214 sc->sc_regh, RADEON_HOST_DATA0, reg); 3215 data8++; 3216 } 3217 break; 3218 } 3219 case 2: { 3220 data16 = data; 3221 for (i = 0; i < h; i++) { 3222 reg = *data16; 3223 reg |= reg >> 1; 3224 #if BYTE_ORDER == LITTLE_ENDIAN 3225 reg = reg << 16; 3226 #endif 3227 bus_space_write_stream_4(sc->sc_regt, 3228 sc->sc_regh, RADEON_HOST_DATA0, reg); 3229 data16++; 3230 } 3231 break; 3232 } 3233 case 4: { 3234 data32 = data; 3235 for (i = 0; i < h; i++) { 3236 reg = *data32; 3237 reg |= reg >> 1; 3238 bus_space_write_stream_4(sc->sc_regt, 3239 sc->sc_regh, RADEON_HOST_DATA0, reg); 3240 data32++; 3241 } 3242 break; 3243 } 3244 } 3245 } else { 3246 switch (font->stride) { 3247 case 1: { 3248 data8 = data; 3249 for (i = 0; i < h; i++) { 3250 reg = *data8; 3251 #if BYTE_ORDER == LITTLE_ENDIAN 3252 reg = reg << 24; 3253 #endif 3254 bus_space_write_stream_4(sc->sc_regt, 3255 sc->sc_regh, RADEON_HOST_DATA0, reg); 3256 data8++; 3257 } 3258 break; 3259 } 3260 case 2: { 3261 data16 = data; 3262 for (i = 0; i < h; i++) { 3263 reg = *data16; 3264 #if BYTE_ORDER == LITTLE_ENDIAN 3265 reg = reg << 16; 3266 #endif 3267 bus_space_write_stream_4(sc->sc_regt, 3268 sc->sc_regh, RADEON_HOST_DATA0, reg); 3269 data16++; 3270 } 3271 break; 3272 } 3273 case 4: { 3274 data32 = data; 3275 for (i = 0; i < h; i++) { 3276 reg = *data32; 3277 bus_space_write_stream_4(sc->sc_regt, 3278 sc->sc_regh, RADEON_HOST_DATA0, reg); 3279 data32++; 3280 } 3281 break; 3282 } 3283 } 3284 } 3285 if (attr & WSATTR_UNDERLINE) 3286 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3287 } 3288 3289 /* ... while this one is for anti-aliased ones */ 3290 static void 3291 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3292 { 3293 struct rasops_info *ri = cookie; 3294 struct vcons_screen *scr = ri->ri_hw; 3295 struct radeonfb_display *dp = scr->scr_cookie; 3296 struct radeonfb_softc *sc = dp->rd_softc; 3297 struct wsdisplay_font *font = PICK_FONT(ri, c); 3298 uint32_t bg, fg, gmc; 3299 uint8_t *data; 3300 int w, h, xd, yd; 3301 int i, r, g, b, aval; 3302 int rf, gf, bf, rb, gb, bb; 3303 uint32_t pixel; 3304 int rv; 3305 3306 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3307 return; 3308 3309 if (!CHAR_IN_FONT(c, font)) 3310 return; 3311 3312 w = font->fontwidth; 3313 h = font->fontheight; 3314 3315 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3316 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3317 3318 xd = ri->ri_xorigin + col * w; 3319 yd = ri->ri_yorigin + row * h; 3320 3321 if (c == 0x20) { 3322 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3323 if (attr & WSATTR_UNDERLINE) 3324 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3325 return; 3326 } 3327 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3328 if (rv == GC_OK) 3329 return; 3330 3331 data = WSFONT_GLYPH(c, font); 3332 3333 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3334 3335 radeonfb_wait_fifo(sc, 5); 3336 3337 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3338 RADEON_GMC_BRUSH_NONE | 3339 RADEON_GMC_SRC_DATATYPE_COLOR | 3340 RADEON_ROP3_S | 3341 RADEON_DP_SRC_SOURCE_HOST_DATA | 3342 RADEON_GMC_CLR_CMP_CNTL_DIS | 3343 RADEON_GMC_WR_MSK_DIS | 3344 gmc); 3345 3346 PUT32(sc, RADEON_DP_CNTL, 3347 RADEON_DST_X_LEFT_TO_RIGHT | 3348 RADEON_DST_Y_TOP_TO_BOTTOM); 3349 3350 PUT32(sc, RADEON_SRC_X_Y, 0); 3351 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3352 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3353 3354 rf = (fg >> 16) & 0xff; 3355 rb = (bg >> 16) & 0xff; 3356 gf = (fg >> 8) & 0xff; 3357 gb = (bg >> 8) & 0xff; 3358 bf = fg & 0xff; 3359 bb = bg & 0xff; 3360 3361 /* 3362 * I doubt we can upload data faster than even the slowest Radeon 3363 * could process them, especially when doing the alpha blending stuff 3364 * along the way, so just make sure there's some room in the FIFO and 3365 * then hammer away 3366 * As it turns out we can, so make periodic stops to let the FIFO 3367 * drain. 3368 */ 3369 radeonfb_wait_fifo(sc, 20); 3370 for (i = 0; i < ri->ri_fontscale; i++) { 3371 aval = *data; 3372 data++; 3373 if (aval == 0) { 3374 pixel = bg; 3375 } else if (aval == 255) { 3376 pixel = fg; 3377 } else { 3378 r = aval * rf + (255 - aval) * rb; 3379 g = aval * gf + (255 - aval) * gb; 3380 b = aval * bf + (255 - aval) * bb; 3381 pixel = (r & 0xff00) << 8 | 3382 (g & 0xff00) | 3383 (b & 0xff00) >> 8; 3384 } 3385 if (i & 16) 3386 radeonfb_wait_fifo(sc, 20); 3387 PUT32(sc, RADEON_HOST_DATA0, pixel); 3388 } 3389 if (rv == GC_ADD) { 3390 glyphcache_add(&dp->rd_gc, c, xd, yd); 3391 } else if (attr & WSATTR_UNDERLINE) 3392 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3393 } 3394 3395 static void 3396 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3397 { 3398 struct rasops_info *ri = cookie; 3399 struct vcons_screen *scr = ri->ri_hw; 3400 struct radeonfb_display *dp = scr->scr_cookie; 3401 struct radeonfb_softc *sc = dp->rd_softc; 3402 struct wsdisplay_font *font = PICK_FONT(ri, c); 3403 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3404 int i, x, y, wi, he, r, g, b, aval; 3405 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3406 uint8_t *data8; 3407 int rv, cnt; 3408 3409 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3410 return; 3411 3412 if (!CHAR_IN_FONT(c, font)) 3413 return; 3414 3415 wi = font->fontwidth; 3416 he = font->fontheight; 3417 3418 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3419 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3420 3421 x = ri->ri_xorigin + col * wi; 3422 y = ri->ri_yorigin + row * he; 3423 3424 if (c == 0x20) { 3425 radeonfb_rectfill(dp, x, y, wi, he, bg); 3426 if (attr & WSATTR_UNDERLINE) 3427 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3428 return; 3429 } 3430 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3431 if (rv == GC_OK) 3432 return; 3433 3434 data8 = WSFONT_GLYPH(c, font); 3435 3436 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3437 3438 radeonfb_wait_fifo(sc, 5); 3439 3440 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3441 RADEON_GMC_BRUSH_NONE | 3442 RADEON_GMC_SRC_DATATYPE_COLOR | 3443 RADEON_ROP3_S | 3444 RADEON_DP_SRC_SOURCE_HOST_DATA | 3445 RADEON_GMC_CLR_CMP_CNTL_DIS | 3446 RADEON_GMC_WR_MSK_DIS | 3447 gmc); 3448 3449 PUT32(sc, RADEON_DP_CNTL, 3450 RADEON_DST_X_LEFT_TO_RIGHT | 3451 RADEON_DST_Y_TOP_TO_BOTTOM); 3452 3453 PUT32(sc, RADEON_SRC_X_Y, 0); 3454 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3455 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3456 3457 /* 3458 * we need the RGB colours here, so get offsets into rasops_cmap 3459 */ 3460 fgo = ((attr >> 24) & 0xf) * 3; 3461 bgo = ((attr >> 16) & 0xf) * 3; 3462 3463 r0 = rasops_cmap[bgo]; 3464 r1 = rasops_cmap[fgo]; 3465 g0 = rasops_cmap[bgo + 1]; 3466 g1 = rasops_cmap[fgo + 1]; 3467 b0 = rasops_cmap[bgo + 2]; 3468 b1 = rasops_cmap[fgo + 2]; 3469 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3470 bg8 = R3G3B2(r0, g0, b0); 3471 fg8 = R3G3B2(r1, g1, b1); 3472 3473 radeonfb_wait_fifo(sc, 20); 3474 cnt = 0; 3475 for (i = 0; i < ri->ri_fontscale; i++) { 3476 aval = *data8; 3477 if (aval == 0) { 3478 pixel = bg8; 3479 } else if (aval == 255) { 3480 pixel = fg8; 3481 } else { 3482 r = aval * r1 + (255 - aval) * r0; 3483 g = aval * g1 + (255 - aval) * g0; 3484 b = aval * b1 + (255 - aval) * b0; 3485 pixel = ((r & 0xe000) >> 8) | 3486 ((g & 0xe000) >> 11) | 3487 ((b & 0xc000) >> 14); 3488 } 3489 latch |= pixel << (8 * (i & 3)); 3490 /* write in 32bit chunks */ 3491 if ((i & 3) == 3) { 3492 PUT32(sc, RADEON_HOST_DATA0, latch); 3493 /* 3494 * not strictly necessary, old data should be shifted 3495 * out 3496 */ 3497 latch = 0; 3498 cnt++; 3499 if (cnt > 16) { 3500 cnt = 0; 3501 radeonfb_wait_fifo(sc, 20); 3502 } 3503 } 3504 data8++; 3505 } 3506 /* if we have pixels left in latch write them out */ 3507 if ((i & 3) != 0) { 3508 /* 3509 * radeon is weird - apparently leftover pixels are written 3510 * from the middle, not from the left as everything else 3511 */ 3512 PUT32(sc, RADEON_HOST_DATA0, latch); 3513 } 3514 3515 if (rv == GC_ADD) { 3516 glyphcache_add(&dp->rd_gc, c, x, y); 3517 } else 3518 if (attr & WSATTR_UNDERLINE) 3519 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3520 } 3521 3522 /* 3523 * wrapper for software character drawing 3524 * just sync the engine and call rasops*_putchar() 3525 */ 3526 3527 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3528 static void 3529 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3530 { 3531 struct rasops_info *ri = cookie; 3532 struct vcons_screen *scr = ri->ri_hw; 3533 struct radeonfb_display *dp = scr->scr_cookie; 3534 3535 radeonfb_engine_idle(dp->rd_softc); 3536 dp->rd_putchar(ri, row, col, c, attr); 3537 } 3538 #endif 3539 3540 static int 3541 radeonfb_allocattr(void *cookie, int fg0, int bg0, int flg, long *attr) 3542 { 3543 struct rasops_info *ri = cookie; 3544 int fg = fg0, bg = bg0; 3545 3546 if ((flg & WSATTR_BLINK) != 0) 3547 return EINVAL; 3548 3549 if ((flg & WSATTR_REVERSE) != 0) { 3550 fg = bg0; 3551 bg = fg0; 3552 } 3553 3554 if (FONT_IS_ALPHA(ri->ri_font) && ((flg & WSATTR_HILIT) != 0)) { 3555 fg = fg0 < 8 ? fg0 + 8 : fg0; 3556 } 3557 3558 *attr = (bg << 16) | (fg << 24) | flg; 3559 return 0; 3560 } 3561 3562 static void 3563 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3564 { 3565 struct rasops_info *ri = cookie; 3566 struct vcons_screen *scr = ri->ri_hw; 3567 struct radeonfb_display *dp = scr->scr_cookie; 3568 uint32_t x, y, w, h, fg, bg, ul; 3569 3570 /* XXX: check for full emulation mode? */ 3571 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3572 if (row == 0 && nrows == ri->ri_rows) { 3573 x = y = 0; 3574 w = dp->rd_virtx; 3575 h = dp->rd_virty; 3576 } else { 3577 x = ri->ri_xorigin; 3578 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3579 w = ri->ri_emuwidth; 3580 h = ri->ri_font->fontheight * nrows; 3581 } 3582 3583 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3584 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3585 } 3586 } 3587 3588 static void 3589 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3590 { 3591 struct rasops_info *ri = cookie; 3592 struct vcons_screen *scr = ri->ri_hw; 3593 struct radeonfb_display *dp = scr->scr_cookie; 3594 uint32_t x, ys, yd, w, h; 3595 3596 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3597 x = ri->ri_xorigin; 3598 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3599 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3600 w = ri->ri_emuwidth; 3601 h = ri->ri_font->fontheight * nrows; 3602 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3603 RADEON_ROP3_S); 3604 } 3605 } 3606 3607 static void 3608 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3609 { 3610 struct rasops_info *ri = cookie; 3611 struct vcons_screen *scr = ri->ri_hw; 3612 struct radeonfb_display *dp = scr->scr_cookie; 3613 uint32_t xs, xd, y, w, h; 3614 3615 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3616 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3617 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3618 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3619 w = ri->ri_font->fontwidth * ncols; 3620 h = ri->ri_font->fontheight; 3621 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3622 RADEON_ROP3_S); 3623 } 3624 } 3625 3626 static void 3627 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3628 long fillattr) 3629 { 3630 struct rasops_info *ri = cookie; 3631 struct vcons_screen *scr = ri->ri_hw; 3632 struct radeonfb_display *dp = scr->scr_cookie; 3633 uint32_t x, y, w, h, fg, bg, ul; 3634 3635 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3636 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3637 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3638 w = ri->ri_font->fontwidth * ncols; 3639 h = ri->ri_font->fontheight; 3640 3641 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3642 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3643 } 3644 } 3645 3646 static void 3647 radeonfb_cursor(void *cookie, int on, int row, int col) 3648 { 3649 struct rasops_info *ri = cookie; 3650 struct vcons_screen *scr = ri->ri_hw; 3651 struct radeonfb_display *dp = scr->scr_cookie; 3652 int x, y, wi, he; 3653 3654 wi = ri->ri_font->fontwidth; 3655 he = ri->ri_font->fontheight; 3656 3657 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3658 x = ri->ri_ccol * wi + ri->ri_xorigin; 3659 y = ri->ri_crow * he + ri->ri_yorigin; 3660 /* first turn off the old cursor */ 3661 if (ri->ri_flg & RI_CURSOR) { 3662 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3663 RADEON_ROP3_Dn); 3664 ri->ri_flg &= ~RI_CURSOR; 3665 } 3666 ri->ri_crow = row; 3667 ri->ri_ccol = col; 3668 /* then (possibly) turn on the new one */ 3669 if (on) { 3670 x = ri->ri_ccol * wi + ri->ri_xorigin; 3671 y = ri->ri_crow * he + ri->ri_yorigin; 3672 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3673 RADEON_ROP3_Dn); 3674 ri->ri_flg |= RI_CURSOR; 3675 } 3676 } else { 3677 scr->scr_ri.ri_crow = row; 3678 scr->scr_ri.ri_ccol = col; 3679 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3680 } 3681 } 3682 3683 /* 3684 * Underlying acceleration support. 3685 */ 3686 3687 static void 3688 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3689 int width, int height, uint32_t color) 3690 { 3691 struct radeonfb_softc *sc = dp->rd_softc; 3692 uint32_t gmc; 3693 3694 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3695 3696 radeonfb_wait_fifo(sc, 6); 3697 3698 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3699 RADEON_GMC_BRUSH_SOLID_COLOR | 3700 RADEON_GMC_SRC_DATATYPE_COLOR | 3701 RADEON_GMC_CLR_CMP_CNTL_DIS | 3702 RADEON_ROP3_P | gmc); 3703 3704 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3705 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3706 PUT32(sc, RADEON_DP_CNTL, 3707 RADEON_DST_X_LEFT_TO_RIGHT | 3708 RADEON_DST_Y_TOP_TO_BOTTOM); 3709 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3710 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3711 } 3712 3713 static void 3714 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3715 int width, int height, long attr) 3716 { 3717 struct radeonfb_display *dp = cookie; 3718 3719 radeonfb_rectfill(dp, dstx, dsty, width, height, 3720 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3721 } 3722 3723 static void 3724 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3725 int dstx, int dsty, int width, int height, int rop) 3726 { 3727 struct radeonfb_display *dp = cookie; 3728 struct radeonfb_softc *sc = dp->rd_softc; 3729 uint32_t gmc; 3730 uint32_t dir; 3731 3732 if (dsty < srcy) { 3733 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3734 } else { 3735 srcy += height - 1; 3736 dsty += height - 1; 3737 dir = 0; 3738 } 3739 if (dstx < srcx) { 3740 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3741 } else { 3742 srcx += width - 1; 3743 dstx += width - 1; 3744 } 3745 3746 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3747 3748 radeonfb_wait_fifo(sc, 6); 3749 3750 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3751 RADEON_GMC_BRUSH_NONE | 3752 RADEON_GMC_SRC_DATATYPE_COLOR | 3753 RADEON_GMC_CLR_CMP_CNTL_DIS | 3754 RADEON_DP_SRC_SOURCE_MEMORY | 3755 rop | gmc); 3756 3757 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3758 PUT32(sc, RADEON_DP_CNTL, dir); 3759 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3760 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3761 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3762 } 3763 3764 static void 3765 radeonfb_engine_idle(struct radeonfb_softc *sc) 3766 { 3767 3768 radeonfb_wait_fifo(sc, 64); 3769 while ((GET32(sc, RADEON_RBBM_STATUS) & 3770 RADEON_RBBM_ACTIVE) != 0); 3771 radeonfb_engine_flush(sc); 3772 } 3773 3774 static inline void 3775 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3776 { 3777 int i; 3778 3779 for (i = RADEON_TIMEOUT; i; i--) { 3780 if ((GET32(sc, RADEON_RBBM_STATUS) & 3781 RADEON_RBBM_FIFOCNT_MASK) >= n) 3782 return; 3783 } 3784 #ifdef RADEONFB_DEBUG 3785 if (!i) 3786 printf("%s: timed out waiting for fifo (%x)\n", 3787 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3788 #endif 3789 } 3790 3791 static void 3792 radeonfb_engine_flush(struct radeonfb_softc *sc) 3793 { 3794 int i = 0; 3795 3796 if (IS_R300(sc) || IS_AVIVO(sc)) { 3797 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3798 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3799 i++; 3800 } 3801 } else { 3802 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3803 RADEON_RB2D_DC_FLUSH_ALL); 3804 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3805 RADEON_RB2D_DC_BUSY) { 3806 i++; 3807 } 3808 } 3809 #ifdef DIAGNOSTIC 3810 if (i > RADEON_TIMEOUT) 3811 printf("%s: engine flush timed out!\n", XNAME(sc)); 3812 #endif 3813 } 3814 3815 static inline void 3816 radeonfb_unclip(struct radeonfb_softc *sc) 3817 { 3818 3819 radeonfb_wait_fifo(sc, 2); 3820 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3821 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3822 } 3823 3824 static void 3825 radeonfb_engine_init(struct radeonfb_display *dp) 3826 { 3827 struct radeonfb_softc *sc = dp->rd_softc; 3828 uint32_t pitch; 3829 3830 /* no 3D */ 3831 PUT32(sc, RADEON_RB3D_CNTL, 0); 3832 3833 if (IS_AVIVO(sc)) { 3834 3835 #if 0 3836 /* XXX the xf86-video-radeon does this, causes lockups here */ 3837 psel = GET32(sc, R400_GB_PIPE_SELECT); 3838 PRINTREG(R400_GB_PIPE_SELECT); 3839 DPRINTF(("PLL %08x %08x\n", GETPLL(sc, R500_DYN_SCLK_PWMEM_PIPE), 3840 (1 | ((psel >> 8) & 0xf) << 4))); 3841 PUTPLL(sc, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((psel >> 8) & 0xf) << 4)); 3842 #endif 3843 SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 3844 SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); 3845 SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE | 3846 R300_DC_DC_DISABLE_IGNORE_PE); 3847 } 3848 3849 PRINTREG(RADEON_RB3D_CNTL); 3850 PRINTREG(RADEON_DP_GUI_MASTER_CNTL); 3851 PRINTREG(RADEON_RBBM_STATUS); 3852 3853 radeonfb_engine_reset(sc); 3854 PRINTREG(RADEON_RBBM_STATUS); 3855 3856 /* 3857 * Apple OF hands us some radeons with tiling enabled - explicitly 3858 * disable it here 3859 */ 3860 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 3861 3862 radeonfb_wait_fifo(sc, 1); 3863 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3864 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3865 3866 radeonfb_wait_fifo(sc, 3); 3867 3868 /* 3869 * XXX 3870 * I strongly suspect this works mostly by accident on !AVIVO 3871 * AVIVO uses all 22 bits for the framebuffer offset, so it can 3872 * address up to 4GB. Older chips probably use bits 20-22 for other 3873 * things and we just so happen to set the right ones by having our 3874 * PCI/AGP space above 0x80000000. 3875 * Either way, r5xx does not work if we set these bits, while older 3876 * chips don't work without. 3877 */ 3878 pitch = (dp->rd_stride + 0x3f) >> 6; 3879 if (IS_AVIVO(sc)) { 3880 pitch = pitch << 22; 3881 } else 3882 pitch = (pitch << 22) | (sc->sc_aperbase >> 10); 3883 3884 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch); 3885 PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch); 3886 PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch); 3887 3888 (void)GET32(sc, RADEON_DP_DATATYPE); 3889 3890 /* default scissors -- no clipping */ 3891 radeonfb_wait_fifo(sc, 1); 3892 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3893 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3894 3895 radeonfb_wait_fifo(sc, 1); 3896 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3897 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3898 RADEON_GMC_CLR_CMP_CNTL_DIS | 3899 RADEON_GMC_BRUSH_SOLID_COLOR | 3900 RADEON_GMC_SRC_DATATYPE_COLOR); 3901 3902 radeonfb_wait_fifo(sc, 10); 3903 PUT32(sc, RADEON_DST_LINE_START, 0); 3904 PUT32(sc, RADEON_DST_LINE_END, 0); 3905 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3906 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3907 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3908 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3909 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3910 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3911 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3912 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3913 radeonfb_engine_idle(sc); 3914 } 3915 3916 static void 3917 radeonfb_engine_reset(struct radeonfb_softc *sc) 3918 { 3919 uint32_t hpc, rbbm, mclkcntl, clkindex; 3920 3921 radeonfb_engine_flush(sc); 3922 3923 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3924 if (HAS_R300CG(sc)) 3925 radeonfb_r300cg_workaround(sc); 3926 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3927 3928 /* 3929 * According to comments in XFree code, resetting the HDP via 3930 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3931 * So we use HOST_PATH_CNTL instead. 3932 */ 3933 3934 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3935 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3936 if (IS_R300(sc) || IS_AVIVO(sc)) { 3937 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3938 RADEON_SOFT_RESET_CP | 3939 RADEON_SOFT_RESET_HI | 3940 RADEON_SOFT_RESET_E2); 3941 GET32(sc, RADEON_RBBM_SOFT_RESET); 3942 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3943 /* 3944 * XXX: this bit is not defined in any ATI docs I have, 3945 * nor in the XFree code, but XFree does it. Why? 3946 */ 3947 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE); 3948 } else { 3949 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3950 RADEON_SOFT_RESET_CP | 3951 RADEON_SOFT_RESET_SE | 3952 RADEON_SOFT_RESET_RE | 3953 RADEON_SOFT_RESET_PP | 3954 RADEON_SOFT_RESET_E2 | 3955 RADEON_SOFT_RESET_RB); 3956 GET32(sc, RADEON_RBBM_SOFT_RESET); 3957 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3958 ~(RADEON_SOFT_RESET_CP | 3959 RADEON_SOFT_RESET_SE | 3960 RADEON_SOFT_RESET_RE | 3961 RADEON_SOFT_RESET_PP | 3962 RADEON_SOFT_RESET_E2 | 3963 RADEON_SOFT_RESET_RB)); 3964 GET32(sc, RADEON_RBBM_SOFT_RESET); 3965 } 3966 3967 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3968 GET32(sc, RADEON_HOST_PATH_CNTL); 3969 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3970 3971 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3972 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3973 3974 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3975 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3976 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3977 3978 if (HAS_R300CG(sc)) 3979 radeonfb_r300cg_workaround(sc); 3980 } 3981 3982 static int 3983 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3984 { 3985 int x, y; 3986 3987 x = pos->x; 3988 y = pos->y; 3989 3990 /* 3991 * This doesn't let a cursor move off the screen. I'm not 3992 * sure if this will have negative effects for e.g. Xinerama. 3993 * I'd guess Xinerama handles it by changing the cursor shape, 3994 * but that needs verification. 3995 */ 3996 if (x >= dp->rd_virtx) 3997 x = dp->rd_virtx - 1; 3998 if (x < 0) 3999 x = 0; 4000 if (y >= dp->rd_virty) 4001 y = dp->rd_virty - 1; 4002 if (y < 0) 4003 y = 0; 4004 4005 dp->rd_cursor.rc_pos.x = x; 4006 dp->rd_cursor.rc_pos.y = y; 4007 4008 radeonfb_cursor_position(dp); 4009 return 0; 4010 } 4011 4012 static int 4013 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 4014 { 4015 unsigned flags; 4016 4017 uint8_t r[2], g[2], b[2]; 4018 unsigned index, count; 4019 int i, err; 4020 int pitch, size; 4021 struct radeonfb_cursor *nc = &dp->rd_tempcursor; 4022 4023 flags = wc->which; 4024 4025 /* copy old values */ 4026 memcpy(nc, &dp->rd_cursor, sizeof(struct radeonfb_cursor)); 4027 4028 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 4029 index = wc->cmap.index; 4030 count = wc->cmap.count; 4031 4032 if (index >= 2 || count > 2 - index) 4033 return EINVAL; 4034 4035 err = copyin(wc->cmap.red, &r[index], count); 4036 if (err) 4037 return err; 4038 err = copyin(wc->cmap.green, &g[index], count); 4039 if (err) 4040 return err; 4041 err = copyin(wc->cmap.blue, &b[index], count); 4042 if (err) 4043 return err; 4044 4045 for (i = index; i < index + count; i++) { 4046 nc->rc_cmap[i] = 4047 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 4048 } 4049 } 4050 4051 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 4052 if ((wc->size.x > RADEON_CURSORMAXX) || 4053 (wc->size.y > RADEON_CURSORMAXY)) 4054 return EINVAL; 4055 4056 /* figure bytes per line */ 4057 pitch = (wc->size.x + 7) / 8; 4058 size = pitch * wc->size.y; 4059 4060 /* clear the old cursor and mask */ 4061 memset(nc->rc_image, 0, 512); 4062 memset(nc->rc_mask, 0, 512); 4063 4064 nc->rc_size = wc->size; 4065 4066 if ((err = copyin(wc->image, nc->rc_image, size)) != 0) 4067 return err; 4068 4069 if ((err = copyin(wc->mask, nc->rc_mask, size)) != 0) 4070 return err; 4071 } 4072 4073 if (flags & WSDISPLAY_CURSOR_DOHOT) { 4074 nc->rc_hot = wc->hot; 4075 if (nc->rc_hot.x >= nc->rc_size.x) 4076 nc->rc_hot.x = nc->rc_size.x - 1; 4077 if (nc->rc_hot.y >= nc->rc_size.y) 4078 nc->rc_hot.y = nc->rc_size.y - 1; 4079 } 4080 4081 if (flags & WSDISPLAY_CURSOR_DOPOS) { 4082 nc->rc_pos = wc->pos; 4083 if (nc->rc_pos.x >= dp->rd_virtx) 4084 nc->rc_pos.x = dp->rd_virtx - 1; 4085 #if 0 4086 if (nc->rc_pos.x < 0) 4087 nc->rc_pos.x = 0; 4088 #endif 4089 if (nc->rc_pos.y >= dp->rd_virty) 4090 nc->rc_pos.y = dp->rd_virty - 1; 4091 #if 0 4092 if (nc->rc_pos.y < 0) 4093 nc->rc_pos.y = 0; 4094 #endif 4095 } 4096 if (flags & WSDISPLAY_CURSOR_DOCUR) { 4097 nc->rc_visible = wc->enable; 4098 } 4099 4100 memcpy(&dp->rd_cursor, nc, sizeof(struct radeonfb_cursor)); 4101 radeonfb_cursor_update(dp, wc->which); 4102 4103 return 0; 4104 } 4105 4106 static uint8_t 4107 radeonfb_backwards(uint8_t d) 4108 { 4109 uint8_t l; 4110 4111 l = d << 7; 4112 l |= ((d & 0x02) << 5); 4113 l |= ((d & 0x04) << 3); 4114 l |= ((d & 0x08) << 1); 4115 l |= ((d & 0x10) >> 1); 4116 l |= ((d & 0x20) >> 3); 4117 l |= ((d & 0x40) >> 5); 4118 l |= ((d & 0x80) >> 7); 4119 return l; 4120 } 4121 4122 /* 4123 * Change the cursor shape. Call this with the cursor locked to avoid 4124 * flickering/tearing. 4125 */ 4126 static void 4127 radeonfb_cursor_shape(struct radeonfb_display *dp) 4128 { 4129 uint8_t and[512], xor[512]; 4130 int i, j, src, dst /* , pitch */; 4131 const uint8_t *msk = dp->rd_cursor.rc_mask; 4132 const uint8_t *img = dp->rd_cursor.rc_image; 4133 4134 /* 4135 * Radeon cursor data interleaves one line of AND data followed 4136 * by a line of XOR data. (Each line corresponds to a whole hardware 4137 * pitch - i.e. 64 pixels or 8 bytes.) 4138 * 4139 * The cursor is displayed using the following table: 4140 * 4141 * AND XOR Result 4142 * ---------------------- 4143 * 0 0 Cursor color 0 4144 * 0 1 Cursor color 1 4145 * 1 0 Transparent 4146 * 1 1 Complement of background 4147 * 4148 * Our masks are therefore different from what we were passed. 4149 * Passed in, I'm assuming the data represents either color 0 or 1, 4150 * and a mask, so the passed in table looks like: 4151 * 4152 * IMG Mask Result 4153 * ----------------------- 4154 * 0 0 Transparent 4155 * 0 1 Cursor color 0 4156 * 1 0 Transparent 4157 * 1 1 Cursor color 1 4158 * 4159 * IF mask bit == 1, AND = 0, XOR = color. 4160 * IF mask bit == 0, AND = 1, XOR = 0. 4161 * 4162 * hence: AND = ~(mask); XOR = color & ~(mask); 4163 */ 4164 4165 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 4166 4167 /* start by assuming all bits are transparent */ 4168 memset(and, 0xff, 512); 4169 memset(xor, 0x00, 512); 4170 4171 src = 0; 4172 dst = 0; 4173 for (i = 0; i < 64; i++) { 4174 for (j = 0; j < 64; j += 8) { 4175 if ((i < dp->rd_cursor.rc_size.y) && 4176 (j < dp->rd_cursor.rc_size.x)) { 4177 4178 /* take care to leave odd bits alone */ 4179 and[dst] &= ~(msk[src]); 4180 xor[dst] = img[src] & msk[src]; 4181 src++; 4182 } 4183 dst++; 4184 } 4185 } 4186 4187 for (i = 0; i < 512; i++) { 4188 and[i] = radeonfb_backwards(and[i]); 4189 xor[i] = radeonfb_backwards(xor[i]); 4190 } 4191 4192 /* copy the image into place */ 4193 for (i = 0; i < 64; i++) { 4194 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 4195 &and[i * 8], 8); 4196 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 4197 &xor[i * 8], 8); 4198 } 4199 } 4200 4201 /* 4202 * We use the cursor in 24bit mode on avivo, much simpler than the above. 4203 * Should probably do the same on older radeons 4204 */ 4205 static void 4206 radeonfb_avivo_cursor_shape(struct radeonfb_display *dp) 4207 { 4208 const uint8_t *msk = dp->rd_cursor.rc_mask; 4209 const uint8_t *img = dp->rd_cursor.rc_image; 4210 uint32_t *out = (uint32_t *)dp->rd_curptr; 4211 uint8_t bit; 4212 int i, j, px; 4213 4214 for (i = 0; i < 64 * 8; i++) { 4215 bit = 0x01; 4216 for (j = 0; j < 8; j++) { 4217 px = ((*msk & bit) ? 2 : 0) | ((*img & bit) ? 1 : 0); 4218 switch (px) { 4219 case 0: 4220 case 1: 4221 *out = htole32(0x00000000); 4222 break; 4223 case 2: 4224 *out = htole32(0xff000000 | 4225 dp->rd_cursor.rc_cmap[0]); 4226 break; 4227 case 3: 4228 *out = htole32(0xff000000 | 4229 dp->rd_cursor.rc_cmap[1]); 4230 break; 4231 } 4232 out++; 4233 bit = bit << 1; 4234 } 4235 msk++; 4236 img++; 4237 } 4238 } 4239 4240 static void 4241 radeonfb_cursor_position(struct radeonfb_display *dp) 4242 { 4243 struct radeonfb_softc *sc = dp->rd_softc; 4244 uint32_t offset, hvoff, hvpos; /* registers */ 4245 uint32_t coff; /* cursor offset */ 4246 int i, x, y, xoff, yoff, crtcoff, lock; 4247 4248 /* 4249 * XXX: this also needs to handle pan/scan 4250 */ 4251 for (i = 0; i < dp->rd_ncrtcs; i++) { 4252 4253 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 4254 4255 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4256 PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f); 4257 if (IS_AVIVO(sc)) { 4258 if (rcp->rc_number) { 4259 offset = AVIVO_D2CUR_SURFACE_ADDRESS; 4260 hvoff = AVIVO_D2CUR_HOT_SPOT; 4261 hvpos = AVIVO_D2CUR_POSITION; 4262 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4263 } else { 4264 offset = AVIVO_D1CUR_SURFACE_ADDRESS; 4265 hvoff = AVIVO_D1CUR_HOT_SPOT; 4266 hvpos = AVIVO_D1CUR_POSITION; 4267 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4268 } 4269 lock = 0; 4270 } else { 4271 if (rcp->rc_number) { 4272 offset = RADEON_CUR2_OFFSET; 4273 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 4274 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 4275 crtcoff = RADEON_CRTC2_OFFSET; 4276 } else { 4277 offset = RADEON_CUR_OFFSET; 4278 hvoff = RADEON_CUR_HORZ_VERT_OFF; 4279 hvpos = RADEON_CUR_HORZ_VERT_POSN; 4280 crtcoff = RADEON_CRTC_OFFSET; 4281 } 4282 lock = RADEON_CUR_LOCK; 4283 } 4284 4285 x = dp->rd_cursor.rc_pos.x; 4286 y = dp->rd_cursor.rc_pos.y; 4287 4288 while (y < rcp->rc_yoffset) { 4289 rcp->rc_yoffset -= RADEON_PANINCREMENT; 4290 } 4291 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 4292 rcp->rc_yoffset += RADEON_PANINCREMENT; 4293 } 4294 while (x < rcp->rc_xoffset) { 4295 rcp->rc_xoffset -= RADEON_PANINCREMENT; 4296 } 4297 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 4298 rcp->rc_xoffset += RADEON_PANINCREMENT; 4299 } 4300 4301 /* adjust for the cursor's hotspot */ 4302 x -= dp->rd_cursor.rc_hot.x; 4303 y -= dp->rd_cursor.rc_hot.y; 4304 xoff = yoff = 0; 4305 4306 if (x >= dp->rd_virtx) 4307 x = dp->rd_virtx - 1; 4308 if (y >= dp->rd_virty) 4309 y = dp->rd_virty - 1; 4310 4311 /* now adjust cursor so it is relative to viewport */ 4312 x -= rcp->rc_xoffset; 4313 y -= rcp->rc_yoffset; 4314 4315 /* 4316 * no need to check for fall off, because we should 4317 * never move off the screen entirely! 4318 */ 4319 coff = 0; 4320 if (x < 0) { 4321 xoff = -x; 4322 x = 0; 4323 } 4324 if (y < 0) { 4325 yoff = -y; 4326 y = 0; 4327 coff = (yoff * 2) * 8; 4328 } 4329 4330 /* pan the display */ 4331 if (crtcoff != 0) 4332 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 4333 rcp->rc_xoffset); 4334 4335 PUT32(sc, offset, (dp->rd_curoff + coff) | lock); 4336 PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock); 4337 /* NB: this unlocks the cursor */ 4338 PUT32(sc, hvpos, (x << 16) | y); 4339 if (IS_AVIVO(sc)) 4340 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4341 } 4342 } 4343 4344 static void 4345 radeonfb_cursor_visible(struct radeonfb_display *dp) 4346 { 4347 struct radeonfb_softc *sc = dp->rd_softc; 4348 int i; 4349 uint32_t gencntl, bit; 4350 4351 for (i = 0; i < dp->rd_ncrtcs; i++) { 4352 if (IS_AVIVO(sc)) { 4353 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4354 if (dp->rd_crtcs[i].rc_number) { 4355 gencntl = AVIVO_D2CUR_CONTROL; 4356 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4357 } else { 4358 gencntl = AVIVO_D1CUR_CONTROL; 4359 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4360 } 4361 } else { 4362 if (dp->rd_crtcs[i].rc_number) { 4363 gencntl = RADEON_CRTC2_GEN_CNTL; 4364 bit = RADEON_CRTC2_CUR_EN; 4365 } else { 4366 gencntl = RADEON_CRTC_GEN_CNTL; 4367 bit = RADEON_CRTC_CUR_EN; 4368 } 4369 } 4370 if (dp->rd_cursor.rc_visible) 4371 SET32(dp->rd_softc, gencntl, bit); 4372 else 4373 CLR32(dp->rd_softc, gencntl, bit); 4374 if (IS_AVIVO(sc)) 4375 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4376 } 4377 } 4378 4379 static void 4380 radeonfb_cursor_cmap(struct radeonfb_display *dp) 4381 { 4382 int i; 4383 uint32_t c0reg, c1reg; 4384 struct radeonfb_softc *sc = dp->rd_softc; 4385 4386 for (i = 0; i < dp->rd_ncrtcs; i++) { 4387 if (dp->rd_crtcs[i].rc_number) { 4388 c0reg = RADEON_CUR2_CLR0; 4389 c1reg = RADEON_CUR2_CLR1; 4390 } else { 4391 c0reg = RADEON_CUR_CLR0; 4392 c1reg = RADEON_CUR_CLR1; 4393 } 4394 4395 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 4396 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 4397 } 4398 } 4399 4400 static void 4401 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 4402 { 4403 struct radeonfb_softc *sc; 4404 int i; 4405 4406 sc = dp->rd_softc; 4407 4408 for (i = 0; i < dp->rd_ncrtcs; i++) { 4409 if (dp->rd_crtcs[i].rc_number) { 4410 if (IS_AVIVO(sc)) { 4411 SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4412 } else 4413 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 4414 } else { 4415 if (IS_AVIVO(sc)) { 4416 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4417 } else 4418 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 4419 } 4420 } 4421 4422 if (which & WSDISPLAY_CURSOR_DOCMAP) { 4423 if (IS_AVIVO(sc)) { 4424 /* 4425 * we use an ARGB cursor here, so we need to rebuild 4426 * the cursor image every time the palette changes 4427 */ 4428 radeonfb_avivo_cursor_shape(dp); 4429 } else 4430 radeonfb_cursor_cmap(dp); 4431 } 4432 4433 if (which & WSDISPLAY_CURSOR_DOSHAPE) { 4434 if (IS_AVIVO(sc)) { 4435 radeonfb_avivo_cursor_shape(dp); 4436 } else 4437 radeonfb_cursor_shape(dp); 4438 } 4439 4440 if (which & WSDISPLAY_CURSOR_DOCUR) 4441 radeonfb_cursor_visible(dp); 4442 4443 /* this one is unconditional, because it updates other stuff */ 4444 radeonfb_cursor_position(dp); 4445 } 4446 4447 static struct videomode * 4448 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4449 { 4450 int r1, r2; 4451 4452 /* otherwise pick the higher refresh rate */ 4453 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4454 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4455 4456 return (r1 < r2 ? m2 : m1); 4457 } 4458 4459 static const struct videomode * 4460 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4461 int x, int y) 4462 { 4463 struct edid_info *ep = &rp->rp_edid; 4464 struct videomode *vmp = NULL; 4465 int i; 4466 4467 if (!rp->rp_edid_valid) { 4468 /* fallback to safe mode */ 4469 return radeonfb_modelookup(sc->sc_defaultmode); 4470 } 4471 4472 /* always choose the preferred mode first! */ 4473 if (ep->edid_preferred_mode) { 4474 4475 /* XXX: add auto-stretching support for native mode */ 4476 4477 /* this may want panning to occur, btw */ 4478 if ((ep->edid_preferred_mode->hdisplay <= x) && 4479 (ep->edid_preferred_mode->vdisplay <= y)) 4480 return ep->edid_preferred_mode; 4481 } 4482 4483 for (i = 0; i < ep->edid_nmodes; i++) { 4484 /* 4485 * We elect to pick a resolution that is too large for 4486 * the monitor than one that is too small. This means 4487 * that we will prefer to pan rather than to try to 4488 * center a smaller display on a larger screen. In 4489 * practice, this shouldn't matter because if a 4490 * monitor can support a larger resolution, it can 4491 * probably also support the smaller. A specific 4492 * exception is fixed format panels, but hopefully 4493 * they are properly dealt with by the "autostretch" 4494 * logic above. 4495 */ 4496 if ((ep->edid_modes[i].hdisplay > x) || 4497 (ep->edid_modes[i].vdisplay > y)) { 4498 continue; 4499 } 4500 4501 /* 4502 * at this point, the display mode is no larger than 4503 * what we've requested. 4504 */ 4505 if (vmp == NULL) 4506 vmp = &ep->edid_modes[i]; 4507 4508 /* eliminate smaller modes */ 4509 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4510 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4511 continue; 4512 4513 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4514 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4515 vmp = &ep->edid_modes[i]; 4516 continue; 4517 } 4518 4519 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4520 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4521 4522 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4523 } 4524 4525 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4526 } 4527 4528 static int 4529 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4530 { 4531 int i; 4532 4533 for (i = 0; i < nlist; i++) { 4534 if ((x == list[i].hdisplay) && 4535 (y == list[i].vdisplay)) { 4536 return 1; 4537 } 4538 } 4539 return 0; 4540 } 4541 4542 static void 4543 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4544 int pan) 4545 { 4546 struct radeonfb_port *rp; 4547 struct edid_info *ep; 4548 int i, j; 4549 4550 *x = 0; 4551 *y = 0; 4552 4553 if (pan) { 4554 for (i = 0; i < dp->rd_ncrtcs; i++) { 4555 rp = dp->rd_crtcs[i].rc_port; 4556 ep = &rp->rp_edid; 4557 if (!rp->rp_edid_valid) { 4558 /* monitor not present */ 4559 continue; 4560 } 4561 4562 /* 4563 * For now we are ignoring "conflict" that 4564 * could occur when mixing some modes like 4565 * 1280x1024 and 1400x800. It isn't clear 4566 * which is better, so the first one wins. 4567 */ 4568 for (j = 0; j < ep->edid_nmodes; j++) { 4569 /* 4570 * ignore resolutions that are too big for 4571 * the radeon 4572 */ 4573 if (ep->edid_modes[j].hdisplay > 4574 dp->rd_softc->sc_maxx) 4575 continue; 4576 if (ep->edid_modes[j].vdisplay > 4577 dp->rd_softc->sc_maxy) 4578 continue; 4579 4580 /* 4581 * pick largest resolution, the 4582 * smaller monitor will pan 4583 */ 4584 if ((ep->edid_modes[j].hdisplay >= *x) && 4585 (ep->edid_modes[j].vdisplay >= *y)) { 4586 *x = ep->edid_modes[j].hdisplay; 4587 *y = ep->edid_modes[j].vdisplay; 4588 } 4589 } 4590 } 4591 4592 } else { 4593 struct videomode *modes; 4594 size_t smodes; 4595 int nmodes = 0; 4596 int valid = 0; 4597 4598 smodes = sizeof(struct videomode) * 64; 4599 modes = kmem_alloc(smodes, KM_SLEEP); 4600 4601 for (i = 0; i < dp->rd_ncrtcs; i++) { 4602 /* 4603 * pick the largest resolution in common. 4604 */ 4605 rp = dp->rd_crtcs[i].rc_port; 4606 ep = &rp->rp_edid; 4607 4608 if (!rp->rp_edid_valid) 4609 continue; 4610 4611 if (!valid) { 4612 /* 4613 * Pick the preferred mode for this port 4614 * if available. 4615 */ 4616 if (ep->edid_preferred_mode) { 4617 struct videomode *vmp = 4618 ep->edid_preferred_mode; 4619 4620 if ((vmp->hdisplay <= 4621 dp->rd_softc->sc_maxx) && 4622 (vmp->vdisplay <= 4623 dp->rd_softc->sc_maxy)) 4624 modes[nmodes++] = *vmp; 4625 } else { 4626 4627 /* initialize starting list */ 4628 for (j = 0; j < ep->edid_nmodes; j++) { 4629 /* 4630 * ignore resolutions that are 4631 * too big for the radeon 4632 */ 4633 if (ep->edid_modes[j].hdisplay > 4634 dp->rd_softc->sc_maxx) 4635 continue; 4636 if (ep->edid_modes[j].vdisplay > 4637 dp->rd_softc->sc_maxy) 4638 continue; 4639 4640 modes[nmodes] = 4641 ep->edid_modes[j]; 4642 nmodes++; 4643 } 4644 } 4645 valid = 1; 4646 } else { 4647 /* merge into preexisting list */ 4648 for (j = 0; j < nmodes; j++) { 4649 if (!radeonfb_hasres(ep->edid_modes, 4650 ep->edid_nmodes, 4651 modes[j].hdisplay, 4652 modes[j].vdisplay)) { 4653 modes[j] = modes[nmodes]; 4654 j--; 4655 nmodes--; 4656 } 4657 } 4658 } 4659 } 4660 4661 /* now we have to pick from the merged list */ 4662 for (i = 0; i < nmodes; i++) { 4663 if ((modes[i].hdisplay >= *x) && 4664 (modes[i].vdisplay >= *y)) { 4665 *x = modes[i].hdisplay; 4666 *y = modes[i].vdisplay; 4667 } 4668 } 4669 kmem_free(modes, smodes); 4670 4671 } 4672 4673 if ((*x == 0) || (*y == 0)) { 4674 /* fallback to safe mode */ 4675 *x = 640; 4676 *y = 480; 4677 } 4678 } 4679 4680 /* 4681 * backlight levels are linear on: 4682 * - RV200, RV250, RV280, RV350 4683 * - but NOT on PowerBook4,3 6,3 6,5 4684 * according to Linux' radeonfb 4685 */ 4686 4687 /* Get the current backlight level for the display. */ 4688 4689 static int 4690 radeonfb_get_backlight(struct radeonfb_display *dp) 4691 { 4692 int s; 4693 uint32_t level; 4694 4695 s = spltty(); 4696 4697 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4698 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4699 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4700 4701 /* 4702 * On some chips, we should negate the backlight level. 4703 * XXX Find out on which chips. 4704 */ 4705 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4706 level = RADEONFB_BACKLIGHT_MAX - level; 4707 4708 splx(s); 4709 4710 return level; 4711 } 4712 4713 /* Set the backlight to the given level for the display. */ 4714 static void 4715 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4716 { 4717 if (dp->rd_bl_on == on) 4718 return; 4719 dp->rd_bl_on = on; 4720 radeonfb_set_backlight(dp, dp->rd_bl_level); 4721 } 4722 4723 static int 4724 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4725 { 4726 struct radeonfb_softc *sc = dp->rd_softc; 4727 int rlevel, s; 4728 uint32_t lvds; 4729 4730 if(!sc->sc_mapped) 4731 return 0; 4732 4733 s = spltty(); 4734 4735 dp->rd_bl_level = level; 4736 if (dp->rd_bl_on == 0) 4737 level = 0; 4738 4739 if (level < 0) 4740 level = 0; 4741 else if (level >= RADEONFB_BACKLIGHT_MAX) 4742 level = RADEONFB_BACKLIGHT_MAX; 4743 4744 /* On some chips, we should negate the backlight level. */ 4745 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4746 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4747 } else 4748 rlevel = level; 4749 4750 callout_stop(&dp->rd_bl_lvds_co); 4751 //radeonfb_engine_idle(sc); 4752 4753 /* 4754 * Turn off the display if the backlight is set to 0, since the 4755 * display is useless without backlight anyway. 4756 */ 4757 if (level == 0) 4758 radeonfb_blank(dp, 1); 4759 else if (radeonfb_get_backlight(dp) == 0) 4760 radeonfb_blank(dp, 0); 4761 4762 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4763 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4764 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4765 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4766 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4767 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4768 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4769 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4770 lvds |= RADEON_LVDS_ON; 4771 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4772 } else { 4773 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4774 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4775 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4776 } 4777 4778 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4779 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4780 /* XXX What is the correct delay? */ 4781 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4782 4783 splx(s); 4784 4785 return 0; 4786 } 4787 4788 /* 4789 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4790 * Set the delayed bits in the register, and clear the stored delayed 4791 * value. 4792 */ 4793 4794 static void radeonfb_lvds_callout(void *arg) 4795 { 4796 struct radeonfb_display *dp = arg; 4797 int s; 4798 4799 s = splhigh(); 4800 4801 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4802 dp->rd_bl_lvds_val); 4803 dp->rd_bl_lvds_val = 0; 4804 4805 splx(s); 4806 } 4807 4808 static void 4809 radeonfb_brightness_up(device_t dev) 4810 { 4811 struct radeonfb_softc *sc = device_private(dev); 4812 struct radeonfb_display *dp = &sc->sc_displays[0]; 4813 int level; 4814 4815 /* we assume the main display is the first one - need a better way */ 4816 if (sc->sc_ndisplays < 1) return; 4817 /* make sure pushing the hotkeys always has an effect */ 4818 dp->rd_bl_on = 1; 4819 level = dp->rd_bl_level; 4820 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4821 radeonfb_set_backlight(dp, level); 4822 } 4823 4824 static void 4825 radeonfb_brightness_down(device_t dev) 4826 { 4827 struct radeonfb_softc *sc = device_private(dev); 4828 struct radeonfb_display *dp = &sc->sc_displays[0]; 4829 int level; 4830 4831 /* we assume the main display is the first one - need a better way */ 4832 if (sc->sc_ndisplays < 1) return; 4833 /* make sure pushing the hotkeys always has an effect */ 4834 dp->rd_bl_on = 1; 4835 level = dp->rd_bl_level; 4836 level = uimax(0, level - 5); 4837 radeonfb_set_backlight(dp, level); 4838 } 4839
Indexes created Sun Sep 13 00:25:22 UTC 2026