Home | History | Annotate | Line # | Download | only in podulebus
      1 /*	$NetBSD: rapide_io_asm.S,v 1.1 2001/10/05 22:27:58 reinoud Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997 Mark Brinicombe.
      5  * Copyright (c) 1997 Causality Limited.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Mark Brinicombe
     19  *	for the NetBSD Project.
     20  * 4. The name of the company nor the name of the author may be used to
     21  *    endorse or promote products derived from this software without specific
     22  *    prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     27  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  */
     36 
     37 #include <machine/asm.h>
     38 
     39 /*
     40  * bus_space I/O functions for Yellowstone RapIDE podule
     41  *
     42  * These are optimised 32 bit transfer routines
     43  */
     44 
     45 ENTRY(rapide_bs_rm_4)
     46 	add	r0, r1, r2
     47 	mov	r1, r3
     48 
     49 	/* Test length */
     50 	ldr	r2, [sp, #0]
     51 	tst	r2, #0x7f
     52 	beq	rapide_rm_4_m128
     53 	tst	r2, #0x07
     54 	beq	rapide_rm_4_m8
     55 
     56 	/* xfer 4 bytes at a time */
     57 rapide_rm_4_loop:
     58 	ldr	r3, [r0]
     59 	str	r3, [r1], #0x0004
     60 	subs	r2, r2, #1
     61 	bne	rapide_rm_4_loop
     62 
     63 	mov	pc, lr
     64 
     65 rapide_rm_4_m8:
     66 	/* xfer 32 bytes at a time */
     67 	stmfd	sp!, {r4-r10}
     68 
     69 rapide_rm_4_m8_loop:
     70 	ldmia	r0, {r3-r10}
     71 	stmia	r1!, {r3-r10}
     72 	subs	r2, r2, #8
     73 	bne	rapide_rm_4_m8_loop
     74 
     75 	ldmfd	sp!, {r4-r10}
     76 	mov	pc, lr
     77 
     78 rapide_rm_4_m128:
     79 	/* xfer 512 bytes at a time */
     80 	stmfd	sp!, {r4-r12, r14}
     81 
     82 rapide_rm_4_m128_loop:
     83 	ldmia	r0, {r3-r12, r14}
     84 	stmia	r1!, {r3-r12, r14}
     85 	ldmia	r0, {r3-r12, r14}
     86 	stmia	r1!, {r3-r12, r14}
     87 	ldmia	r0, {r3-r12, r14}
     88 	stmia	r1!, {r3-r12, r14}
     89 	ldmia	r0, {r3-r12, r14}
     90 	stmia	r1!, {r3-r12, r14}
     91 	ldmia	r0, {r3-r12, r14}
     92 	stmia	r1!, {r3-r12, r14}
     93 	ldmia	r0, {r3-r12, r14}
     94 	stmia	r1!, {r3-r12, r14}
     95 	ldmia	r0, {r3-r12, r14}
     96 	stmia	r1!, {r3-r12, r14}
     97 	ldmia	r0, {r3-r12, r14}
     98 	stmia	r1!, {r3-r12, r14}
     99 	ldmia	r0, {r3-r12, r14}
    100 	stmia	r1!, {r3-r12, r14}
    101 	ldmia	r0, {r3-r12, r14}
    102 	stmia	r1!, {r3-r12, r14}
    103 	ldmia	r0, {r3-r12, r14}
    104 	stmia	r1!, {r3-r12, r14}
    105 	ldmia	r0, {r3-r9}
    106 	stmia	r1!, {r3-r9}
    107 	subs	r2, r2, #128
    108 	bne	rapide_rm_4_m128_loop
    109 
    110 	ldmfd	sp!, {r4-r12, pc}
    111 
    112 ENTRY(rapide_bs_wm_4)
    113 	add	r0, r1, r2
    114 	mov	r1, r3
    115 	ldr	r2, [sp, #0]
    116 	tst	r2, #0x7f
    117 	beq	rapide_wm_4_m128
    118 	tst	r2, #0x07
    119 	beq	rapide_wm_4_m8
    120 
    121 	/* xfer 4 bytes at a time */
    122 rapide_wm_4_loop:
    123 	ldr	r3, [r1], #0x0004
    124 	str	r3, [r0]
    125 	subs	r2, r2, #1
    126 	bne	rapide_wm_4_loop
    127 
    128 	mov	pc, lr
    129 
    130 rapide_wm_4_m8:
    131 	/* xfer 32 bytes at a time */
    132 	stmfd	sp!, {r4-r10}
    133 
    134 rapide_wm_4_m8_loop:
    135 	ldmia	r1!, {r3-r10}
    136 	stmia	r0, {r3-r10}
    137 	subs	r2, r2, #8
    138 	bne	rapide_wm_4_m8_loop
    139 
    140 	ldmfd	sp!, {r4-r10}
    141 	mov	pc, lr
    142 
    143 rapide_wm_4_m128:
    144 	/* xfer 512 bytes at a time */
    145 	stmfd	sp!, {r4-r12}
    146 
    147 rapide_wm_4_m128_loop:
    148 	ldmia	r1!, {r3-r12}
    149 	stmia	r0, {r3-r12}
    150 	ldmia	r1!, {r3-r12}
    151 	stmia	r0, {r3-r12}
    152 	ldmia	r1!, {r3-r12}
    153 	stmia	r0, {r3-r12}
    154 	ldmia	r1!, {r3-r12}
    155 	stmia	r0, {r3-r12}
    156 	ldmia	r1!, {r3-r12}
    157 	stmia	r0, {r3-r12}
    158 	ldmia	r1!, {r3-r12}
    159 	stmia	r0, {r3-r12}
    160 	ldmia	r1!, {r3-r12}
    161 	stmia	r0, {r3-r12}
    162 	ldmia	r1!, {r3-r12}
    163 	stmia	r0, {r3-r12}
    164 	ldmia	r1!, {r3-r12}
    165 	stmia	r0, {r3-r12}
    166 	ldmia	r1!, {r3-r12}
    167 	stmia	r0, {r3-r12}
    168 	ldmia	r1!, {r3-r12}
    169 	stmia	r0, {r3-r12}
    170 	ldmia	r1!, {r3-r12}
    171 	stmia	r0, {r3-r12}
    172 	ldmia	r1!, {r3-r10}
    173 	stmia	r0, {r3-r10}
    174 	subs	r2, r2, #128
    175 	bne	rapide_wm_4_m128_loop
    176 
    177 	ldmfd	sp!, {r4-r12}
    178 	mov	pc, lr
    179