1 /* $NetBSD: rtl8169.c,v 1.179 2024/08/12 21:27:34 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.179 2024/08/12 21:27:34 christos Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul (at) windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168 and the RTL8111. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/kernel.h> 121 #include <sys/socket.h> 122 #include <sys/device.h> 123 124 #include <net/if.h> 125 #include <net/if_arp.h> 126 #include <net/if_dl.h> 127 #include <net/if_ether.h> 128 #include <net/if_media.h> 129 #include <net/if_vlanvar.h> 130 131 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 132 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 134 135 #include <net/bpf.h> 136 #include <sys/rndsource.h> 137 138 #include <sys/bus.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/ic/rtl81x9reg.h> 144 #include <dev/ic/rtl81x9var.h> 145 146 #include <dev/ic/rtl8169var.h> 147 148 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 149 150 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 151 static int re_rx_list_init(struct rtk_softc *); 152 static int re_tx_list_init(struct rtk_softc *); 153 static void re_rxeof(struct rtk_softc *); 154 static void re_txeof(struct rtk_softc *); 155 static void re_tick(void *); 156 static void re_start(struct ifnet *); 157 static int re_ioctl(struct ifnet *, u_long, void *); 158 static int re_init(struct ifnet *); 159 static void re_stop(struct ifnet *, int); 160 static void re_watchdog(struct ifnet *); 161 162 static int re_enable(struct rtk_softc *); 163 static void re_disable(struct rtk_softc *); 164 165 static int re_gmii_readreg(device_t, int, int, uint16_t *); 166 static int re_gmii_writereg(device_t, int, int, uint16_t); 167 168 static int re_miibus_readreg(device_t, int, int, uint16_t *); 169 static int re_miibus_writereg(device_t, int, int, uint16_t); 170 static void re_miibus_statchg(struct ifnet *); 171 172 static void re_reset(struct rtk_softc *); 173 174 static const struct re_revision { 175 uint32_t re_chipid; 176 const char *re_name; 177 } re_revisions[] = { 178 { RTK_HWREV_8100, "RTL8100" }, 179 { RTK_HWREV_8100E, "RTL8100E" }, 180 { RTK_HWREV_8100E_SPIN2, "RTL8100E 2" }, 181 { RTK_HWREV_8101, "RTL8101" }, 182 { RTK_HWREV_8101E, "RTL8101E" }, 183 { RTK_HWREV_8102E, "RTL8102E" }, 184 { RTK_HWREV_8106E, "RTL8106E" }, 185 { RTK_HWREV_8401E, "RTL8401E" }, 186 { RTK_HWREV_8402, "RTL8402" }, 187 { RTK_HWREV_8411, "RTL8411" }, 188 { RTK_HWREV_8411B, "RTL8411B" }, 189 { RTK_HWREV_8102EL, "RTL8102EL" }, 190 { RTK_HWREV_8102EL_SPIN1, "RTL8102EL 1" }, 191 { RTK_HWREV_8103E, "RTL8103E" }, 192 { RTK_HWREV_8110S, "RTL8110S" }, 193 { RTK_HWREV_8139CPLUS, "RTL8139C+" }, 194 { RTK_HWREV_8168B_SPIN1, "RTL8168 1" }, 195 { RTK_HWREV_8168B_SPIN2, "RTL8168 2" }, 196 { RTK_HWREV_8168B_SPIN3, "RTL8168 3" }, 197 { RTK_HWREV_8168C, "RTL8168C/8111C" }, 198 { RTK_HWREV_8168C_SPIN2, "RTL8168C/8111C" }, 199 { RTK_HWREV_8168CP, "RTL8168CP/8111CP" }, 200 { RTK_HWREV_8168F, "RTL8168F/8111F" }, 201 { RTK_HWREV_8168G, "RTL8168G/8111G" }, 202 { RTK_HWREV_8168GU, "RTL8168GU/8111GU" }, 203 { RTK_HWREV_8168H, "RTL8168H/8111H" }, 204 { RTK_HWREV_8105E, "RTL8105E" }, 205 { RTK_HWREV_8105E_SPIN1, "RTL8105E" }, 206 { RTK_HWREV_8168D, "RTL8168D/8111D" }, 207 { RTK_HWREV_8168DP, "RTL8168DP/8111DP" }, 208 { RTK_HWREV_8168E, "RTL8168E/8111E" }, 209 { RTK_HWREV_8168E_VL, "RTL8168E/8111E-VL" }, 210 { RTK_HWREV_8168EP, "RTL8168EP/8111EP" }, 211 { RTK_HWREV_8168FP, "RTL8168FP/8117" }, 212 { RTK_HWREV_8169, "RTL8169" }, 213 { RTK_HWREV_8169_8110SB, "RTL8169/8110SB" }, 214 { RTK_HWREV_8169_8110SBL, "RTL8169SBL" }, 215 { RTK_HWREV_8169_8110SC, "RTL8169/8110SCd" }, 216 { RTK_HWREV_8169_8110SCE, "RTL8169/8110SCe" }, 217 { RTK_HWREV_8169S, "RTL8169S" }, 218 219 { 0, NULL } 220 }; 221 222 static inline void 223 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 224 { 225 226 d->re_bufaddr_lo = htole32(RE_ADDR_LO(addr)); 227 d->re_bufaddr_hi = htole32(RE_ADDR_HI(addr)); 228 } 229 230 static int 231 re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val) 232 { 233 struct rtk_softc *sc = device_private(dev); 234 uint32_t data; 235 int i; 236 237 if (phy != 7) 238 return -1; 239 240 /* Let the rgephy driver read the GMEDIASTAT register */ 241 242 if (reg == RTK_GMEDIASTAT) { 243 *val = CSR_READ_1(sc, RTK_GMEDIASTAT); 244 return 0; 245 } 246 247 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 248 DELAY(1000); 249 250 for (i = 0; i < RTK_TIMEOUT; i++) { 251 data = CSR_READ_4(sc, RTK_PHYAR); 252 if (data & RTK_PHYAR_BUSY) 253 break; 254 DELAY(100); 255 } 256 257 if (i == RTK_TIMEOUT) { 258 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 259 return ETIMEDOUT; 260 } 261 262 *val = data & RTK_PHYAR_PHYDATA; 263 return 0; 264 } 265 266 static int 267 re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val) 268 { 269 struct rtk_softc *sc = device_private(dev); 270 uint32_t data; 271 int i; 272 273 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 274 (val & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 275 DELAY(1000); 276 277 for (i = 0; i < RTK_TIMEOUT; i++) { 278 data = CSR_READ_4(sc, RTK_PHYAR); 279 if (!(data & RTK_PHYAR_BUSY)) 280 break; 281 DELAY(100); 282 } 283 284 if (i == RTK_TIMEOUT) { 285 printf("%s: PHY write reg %x <- %hx failed\n", 286 device_xname(sc->sc_dev), reg, val); 287 return ETIMEDOUT; 288 } 289 290 return 0; 291 } 292 293 static int 294 re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 295 { 296 struct rtk_softc *sc = device_private(dev); 297 uint16_t re8139_reg = 0; 298 int s, rv = 0; 299 300 s = splnet(); 301 302 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 303 rv = re_gmii_readreg(dev, phy, reg, val); 304 splx(s); 305 return rv; 306 } 307 308 /* Pretend the internal PHY is only at address 0 */ 309 if (phy) { 310 splx(s); 311 return -1; 312 } 313 switch (reg) { 314 case MII_BMCR: 315 re8139_reg = RTK_BMCR; 316 break; 317 case MII_BMSR: 318 re8139_reg = RTK_BMSR; 319 break; 320 case MII_ANAR: 321 re8139_reg = RTK_ANAR; 322 break; 323 case MII_ANER: 324 re8139_reg = RTK_ANER; 325 break; 326 case MII_ANLPAR: 327 re8139_reg = RTK_LPAR; 328 break; 329 case MII_PHYIDR1: 330 case MII_PHYIDR2: 331 *val = 0; 332 splx(s); 333 return 0; 334 /* 335 * Allow the rlphy driver to read the media status 336 * register. If we have a link partner which does not 337 * support NWAY, this is the register which will tell 338 * us the results of parallel detection. 339 */ 340 case RTK_MEDIASTAT: 341 *val = CSR_READ_1(sc, RTK_MEDIASTAT); 342 splx(s); 343 return 0; 344 default: 345 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 346 splx(s); 347 return -1; 348 } 349 *val = CSR_READ_2(sc, re8139_reg); 350 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 351 /* 8139C+ has different bit layout. */ 352 *val &= ~(BMCR_LOOP | BMCR_ISO); 353 } 354 splx(s); 355 return 0; 356 } 357 358 static int 359 re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 360 { 361 struct rtk_softc *sc = device_private(dev); 362 uint16_t re8139_reg = 0; 363 int s, rv; 364 365 s = splnet(); 366 367 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 368 rv = re_gmii_writereg(dev, phy, reg, val); 369 splx(s); 370 return rv; 371 } 372 373 /* Pretend the internal PHY is only at address 0 */ 374 if (phy) { 375 splx(s); 376 return -1; 377 } 378 switch (reg) { 379 case MII_BMCR: 380 re8139_reg = RTK_BMCR; 381 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 382 /* 8139C+ has different bit layout. */ 383 val &= ~(BMCR_LOOP | BMCR_ISO); 384 } 385 break; 386 case MII_BMSR: 387 re8139_reg = RTK_BMSR; 388 break; 389 case MII_ANAR: 390 re8139_reg = RTK_ANAR; 391 break; 392 case MII_ANER: 393 re8139_reg = RTK_ANER; 394 break; 395 case MII_ANLPAR: 396 re8139_reg = RTK_LPAR; 397 break; 398 case MII_PHYIDR1: 399 case MII_PHYIDR2: 400 splx(s); 401 return 0; 402 break; 403 default: 404 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 405 splx(s); 406 return -1; 407 } 408 CSR_WRITE_2(sc, re8139_reg, val); 409 splx(s); 410 return 0; 411 } 412 413 static void 414 re_miibus_statchg(struct ifnet *ifp) 415 { 416 417 return; 418 } 419 420 static void 421 re_reset(struct rtk_softc *sc) 422 { 423 int i; 424 425 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 426 427 for (i = 0; i < RTK_TIMEOUT; i++) { 428 DELAY(10); 429 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 430 break; 431 } 432 if (i == RTK_TIMEOUT) 433 printf("%s: reset never completed!\n", 434 device_xname(sc->sc_dev)); 435 436 /* 437 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 438 * but also says "Rtl8169s sigle chip detected". 439 */ 440 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 441 CSR_WRITE_1(sc, RTK_LDPS, 1); 442 443 } 444 445 /* 446 * The following routine is designed to test for a defect on some 447 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 448 * lines connected to the bus, however for a 32-bit only card, they 449 * should be pulled high. The result of this defect is that the 450 * NIC will not work right if you plug it into a 64-bit slot: DMA 451 * operations will be done with 64-bit transfers, which will fail 452 * because the 64-bit data lines aren't connected. 453 * 454 * There's no way to work around this (short of talking a soldering 455 * iron to the board), however we can detect it. The method we use 456 * here is to put the NIC into digital loopback mode, set the receiver 457 * to promiscuous mode, and then try to send a frame. We then compare 458 * the frame data we sent to what was received. If the data matches, 459 * then the NIC is working correctly, otherwise we know the user has 460 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 461 * slot. In the latter case, there's no way the NIC can work correctly, 462 * so we print out a message on the console and abort the device attach. 463 */ 464 465 int 466 re_diag(struct rtk_softc *sc) 467 { 468 struct ifnet *ifp = &sc->ethercom.ec_if; 469 struct mbuf *m0; 470 struct ether_header *eh; 471 struct re_rxsoft *rxs; 472 struct re_desc *cur_rx; 473 bus_dmamap_t dmamap; 474 uint16_t status; 475 uint32_t rxstat; 476 int total_len, i, s, error = 0; 477 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 478 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 479 480 /* Allocate a single mbuf */ 481 482 MGETHDR(m0, M_DONTWAIT, MT_DATA); 483 if (m0 == NULL) 484 return ENOBUFS; 485 486 /* 487 * Initialize the NIC in test mode. This sets the chip up 488 * so that it can send and receive frames, but performs the 489 * following special functions: 490 * - Puts receiver in promiscuous mode 491 * - Enables digital loopback mode 492 * - Leaves interrupts turned off 493 */ 494 495 ifp->if_flags |= IFF_PROMISC; 496 sc->re_testmode = 1; 497 re_init(ifp); 498 re_stop(ifp, 0); 499 DELAY(100000); 500 re_init(ifp); 501 502 /* Put some data in the mbuf */ 503 504 eh = mtod(m0, struct ether_header *); 505 memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN); 506 memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN); 507 eh->ether_type = htons(ETHERTYPE_IP); 508 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 509 510 /* 511 * Queue the packet, start transmission. 512 */ 513 514 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 515 s = splnet(); 516 IF_ENQUEUE(&ifp->if_snd, m0); 517 re_start(ifp); 518 splx(s); 519 m0 = NULL; 520 521 /* Wait for it to propagate through the chip */ 522 523 DELAY(100000); 524 for (i = 0; i < RTK_TIMEOUT; i++) { 525 status = CSR_READ_2(sc, RTK_ISR); 526 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 527 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 528 break; 529 DELAY(10); 530 } 531 if (i == RTK_TIMEOUT) { 532 aprint_error_dev(sc->sc_dev, 533 "diagnostic failed, failed to receive packet " 534 "in loopback mode\n"); 535 error = EIO; 536 goto done; 537 } 538 539 /* 540 * The packet should have been dumped into the first 541 * entry in the RX DMA ring. Grab it from there. 542 */ 543 544 rxs = &sc->re_ldata.re_rxsoft[0]; 545 dmamap = rxs->rxs_dmamap; 546 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 547 BUS_DMASYNC_POSTREAD); 548 bus_dmamap_unload(sc->sc_dmat, dmamap); 549 550 m0 = rxs->rxs_mbuf; 551 rxs->rxs_mbuf = NULL; 552 eh = mtod(m0, struct ether_header *); 553 554 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 555 cur_rx = &sc->re_ldata.re_rx_list[0]; 556 rxstat = le32toh(cur_rx->re_cmdstat); 557 total_len = rxstat & sc->re_rxlenmask; 558 559 if (total_len != ETHER_MIN_LEN) { 560 aprint_error_dev(sc->sc_dev, 561 "diagnostic failed, received short packet\n"); 562 error = EIO; 563 goto done; 564 } 565 566 /* Test that the received packet data matches what we sent. */ 567 568 if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) || 569 memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) || 570 ntohs(eh->ether_type) != ETHERTYPE_IP) { 571 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 572 "expected TX data: %s/%s/0x%x\n" 573 "received RX data: %s/%s/0x%x\n" 574 "You may have a defective 32-bit NIC plugged " 575 "into a 64-bit PCI slot.\n" 576 "Please re-install the NIC in a 32-bit slot " 577 "for proper operation.\n" 578 "Read the re(4) man page for more details.\n" , 579 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 580 ether_sprintf(eh->ether_dhost), 581 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 582 error = EIO; 583 } 584 585 done: 586 /* Turn interface off, release resources */ 587 588 sc->re_testmode = 0; 589 ifp->if_flags &= ~IFF_PROMISC; 590 re_stop(ifp, 0); 591 m_freem(m0); 592 593 return error; 594 } 595 596 597 /* 598 * Attach the interface. Allocate softc structures, do ifmedia 599 * setup and ethernet/BPF attach. 600 */ 601 void 602 re_attach(struct rtk_softc *sc) 603 { 604 uint8_t eaddr[ETHER_ADDR_LEN]; 605 struct ifnet *ifp; 606 struct mii_data *mii = &sc->mii; 607 int error = 0, i; 608 const struct re_revision *rr; 609 const char *re_name = NULL; 610 611 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 612 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 613 sc->sc_hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 614 615 for (rr = re_revisions; rr->re_name != NULL; rr++) { 616 if (rr->re_chipid == sc->sc_hwrev) 617 re_name = rr->re_name; 618 } 619 620 if (re_name == NULL) 621 aprint_normal_dev(sc->sc_dev, 622 "unknown ASIC (0x%04x)\n", sc->sc_hwrev >> 16); 623 else 624 aprint_normal_dev(sc->sc_dev, 625 "%s (0x%04x)\n", re_name, sc->sc_hwrev >> 16); 626 627 switch (sc->sc_hwrev) { 628 case RTK_HWREV_8169: 629 sc->sc_quirk |= RTKQ_8169NONS; 630 break; 631 case RTK_HWREV_8169S: 632 case RTK_HWREV_8110S: 633 case RTK_HWREV_8169_8110SB: 634 case RTK_HWREV_8169_8110SBL: 635 case RTK_HWREV_8169_8110SC: 636 sc->sc_quirk |= RTKQ_MACLDPS; 637 break; 638 case RTK_HWREV_8168B_SPIN1: 639 case RTK_HWREV_8168B_SPIN2: 640 case RTK_HWREV_8168B_SPIN3: 641 sc->sc_quirk |= RTKQ_MACSTAT; 642 break; 643 case RTK_HWREV_8168C: 644 case RTK_HWREV_8168C_SPIN2: 645 case RTK_HWREV_8168CP: 646 case RTK_HWREV_8168D: 647 case RTK_HWREV_8168DP: 648 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 649 RTKQ_MACSTAT | RTKQ_CMDSTOP; 650 /* 651 * From FreeBSD driver: 652 * 653 * These (8168/8111) controllers support jumbo frame 654 * but it seems that enabling it requires touching 655 * additional magic registers. Depending on MAC 656 * revisions some controllers need to disable 657 * checksum offload. So disable jumbo frame until 658 * I have better idea what it really requires to 659 * make it support. 660 * RTL8168C/CP : supports up to 6KB jumbo frame. 661 * RTL8111C/CP : supports up to 9KB jumbo frame. 662 */ 663 sc->sc_quirk |= RTKQ_NOJUMBO; 664 break; 665 case RTK_HWREV_8168E: 666 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 667 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 668 RTKQ_NOJUMBO; 669 break; 670 case RTK_HWREV_8168E_VL: 671 case RTK_HWREV_8168F: 672 sc->sc_quirk |= RTKQ_EARLYOFF; 673 /*FALLTHROUGH*/ 674 case RTK_HWREV_8411: 675 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 676 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 677 break; 678 case RTK_HWREV_8168EP: 679 case RTK_HWREV_8168FP: 680 case RTK_HWREV_8168G: 681 case RTK_HWREV_8168GU: 682 case RTK_HWREV_8168H: 683 case RTK_HWREV_8411B: 684 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 685 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO | 686 RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER; 687 break; 688 case RTK_HWREV_8100E: 689 case RTK_HWREV_8100E_SPIN2: 690 case RTK_HWREV_8101E: 691 sc->sc_quirk |= RTKQ_NOJUMBO; 692 break; 693 case RTK_HWREV_8102E: 694 case RTK_HWREV_8102EL: 695 case RTK_HWREV_8102EL_SPIN1: 696 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 697 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 698 break; 699 case RTK_HWREV_8103E: 700 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 701 RTKQ_MACSTAT | RTKQ_CMDSTOP; 702 break; 703 case RTK_HWREV_8401E: 704 case RTK_HWREV_8105E: 705 case RTK_HWREV_8105E_SPIN1: /* XXX */ 706 case RTK_HWREV_8106E: 707 sc->sc_quirk |= RTKQ_PHYWAKE_PM | 708 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT | 709 RTKQ_CMDSTOP; 710 break; 711 case RTK_HWREV_8402: 712 sc->sc_quirk |= RTKQ_PHYWAKE_PM | 713 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT | 714 RTKQ_CMDSTOP; /* CMDSTOP_WAIT_TXQ */ 715 break; 716 default: 717 /* assume the latest features */ 718 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 719 sc->sc_quirk |= RTKQ_NOJUMBO; 720 } 721 722 /* Set RX length mask */ 723 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 724 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 725 } else { 726 sc->sc_quirk |= RTKQ_NOJUMBO; 727 728 /* Set RX length mask */ 729 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 730 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 731 } 732 733 /* Reset the adapter. */ 734 re_reset(sc); 735 736 /* 737 * RTL81x9 chips automatically read EEPROM to init MAC address, 738 * and some NAS override its MAC address per own configuration, 739 * so no need to explicitly read EEPROM and set ID registers. 740 */ 741 #ifdef RE_USE_EECMD 742 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 743 /* 744 * Get station address from ID registers. 745 */ 746 for (i = 0; i < ETHER_ADDR_LEN; i++) 747 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 748 } else { 749 uint16_t val; 750 int addr_len; 751 752 /* 753 * Get station address from the EEPROM. 754 */ 755 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 756 addr_len = RTK_EEADDR_LEN1; 757 else 758 addr_len = RTK_EEADDR_LEN0; 759 760 /* 761 * Get station address from the EEPROM. 762 */ 763 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 764 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 765 eaddr[(i * 2) + 0] = val & 0xff; 766 eaddr[(i * 2) + 1] = val >> 8; 767 } 768 } 769 #else 770 /* 771 * Get station address from ID registers. 772 */ 773 for (i = 0; i < ETHER_ADDR_LEN; i++) 774 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 775 #endif 776 777 /* Take PHY out of power down mode. */ 778 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 779 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 780 781 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 782 ether_sprintf(eaddr)); 783 784 if (sc->re_ldata.re_tx_desc_cnt > 785 PAGE_SIZE / sizeof(struct re_desc)) { 786 sc->re_ldata.re_tx_desc_cnt = 787 PAGE_SIZE / sizeof(struct re_desc); 788 } 789 790 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 791 sc->re_ldata.re_tx_desc_cnt); 792 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 793 794 /* Allocate DMA'able memory for the TX ring */ 795 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 796 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 797 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 798 aprint_error_dev(sc->sc_dev, 799 "can't allocate tx listseg, error = %d\n", error); 800 goto fail_0; 801 } 802 803 /* Load the map for the TX ring. */ 804 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 805 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 806 (void **)&sc->re_ldata.re_tx_list, 807 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 808 aprint_error_dev(sc->sc_dev, 809 "can't map tx list, error = %d\n", error); 810 goto fail_1; 811 } 812 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 813 814 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 815 RE_TX_LIST_SZ(sc), 0, 0, 816 &sc->re_ldata.re_tx_list_map)) != 0) { 817 aprint_error_dev(sc->sc_dev, 818 "can't create tx list map, error = %d\n", error); 819 goto fail_2; 820 } 821 822 823 if ((error = bus_dmamap_load(sc->sc_dmat, 824 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 825 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 826 aprint_error_dev(sc->sc_dev, 827 "can't load tx list, error = %d\n", error); 828 goto fail_3; 829 } 830 831 /* Create DMA maps for TX buffers */ 832 for (i = 0; i < RE_TX_QLEN; i++) { 833 error = bus_dmamap_create(sc->sc_dmat, 834 round_page(IP_MAXPACKET), 835 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 836 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 837 if (error) { 838 aprint_error_dev(sc->sc_dev, 839 "can't create DMA map for TX\n"); 840 goto fail_4; 841 } 842 } 843 844 /* Allocate DMA'able memory for the RX ring */ 845 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 846 if ((error = bus_dmamem_alloc(sc->sc_dmat, 847 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 848 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 849 aprint_error_dev(sc->sc_dev, 850 "can't allocate rx listseg, error = %d\n", error); 851 goto fail_4; 852 } 853 854 /* Load the map for the RX ring. */ 855 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 856 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 857 (void **)&sc->re_ldata.re_rx_list, 858 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 859 aprint_error_dev(sc->sc_dev, 860 "can't map rx list, error = %d\n", error); 861 goto fail_5; 862 } 863 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 864 865 if ((error = bus_dmamap_create(sc->sc_dmat, 866 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 867 &sc->re_ldata.re_rx_list_map)) != 0) { 868 aprint_error_dev(sc->sc_dev, 869 "can't create rx list map, error = %d\n", error); 870 goto fail_6; 871 } 872 873 if ((error = bus_dmamap_load(sc->sc_dmat, 874 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 875 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 876 aprint_error_dev(sc->sc_dev, 877 "can't load rx list, error = %d\n", error); 878 goto fail_7; 879 } 880 881 /* Create DMA maps for RX buffers */ 882 for (i = 0; i < RE_RX_DESC_CNT; i++) { 883 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 884 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 885 if (error) { 886 aprint_error_dev(sc->sc_dev, 887 "can't create DMA map for RX\n"); 888 goto fail_8; 889 } 890 } 891 892 /* 893 * Record interface as attached. From here, we should not fail. 894 */ 895 sc->sc_flags |= RTK_ATTACHED; 896 897 ifp = &sc->ethercom.ec_if; 898 ifp->if_softc = sc; 899 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 900 ifp->if_mtu = ETHERMTU; 901 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 902 ifp->if_ioctl = re_ioctl; 903 sc->ethercom.ec_capabilities |= 904 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 905 ifp->if_start = re_start; 906 ifp->if_stop = re_stop; 907 908 /* 909 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 910 * so we have a workaround to handle the bug by padding 911 * such packets manually. 912 */ 913 ifp->if_capabilities |= 914 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 915 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 916 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 917 IFCAP_TSOv4; 918 919 ifp->if_watchdog = re_watchdog; 920 ifp->if_init = re_init; 921 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 922 ifp->if_capenable = ifp->if_capabilities; 923 IFQ_SET_READY(&ifp->if_snd); 924 925 callout_init(&sc->rtk_tick_ch, 0); 926 callout_setfunc(&sc->rtk_tick_ch, re_tick, sc); 927 928 /* Do MII setup */ 929 mii->mii_ifp = ifp; 930 mii->mii_readreg = re_miibus_readreg; 931 mii->mii_writereg = re_miibus_writereg; 932 mii->mii_statchg = re_miibus_statchg; 933 sc->ethercom.ec_mii = mii; 934 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 935 ether_mediastatus); 936 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 937 MII_OFFSET_ANY, 0); 938 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 939 940 /* 941 * Call MI attach routine. 942 */ 943 if_attach(ifp); 944 if_deferred_start_init(ifp, NULL); 945 ether_ifattach(ifp, eaddr); 946 947 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 948 RND_TYPE_NET, RND_FLAG_DEFAULT); 949 950 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 951 pmf_class_network_register(sc->sc_dev, ifp); 952 else 953 aprint_error_dev(sc->sc_dev, 954 "couldn't establish power handler\n"); 955 956 return; 957 958 fail_8: 959 /* Destroy DMA maps for RX buffers. */ 960 for (i = 0; i < RE_RX_DESC_CNT; i++) 961 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 962 bus_dmamap_destroy(sc->sc_dmat, 963 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 964 965 /* Free DMA'able memory for the RX ring. */ 966 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 967 fail_7: 968 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 969 fail_6: 970 bus_dmamem_unmap(sc->sc_dmat, 971 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 972 fail_5: 973 bus_dmamem_free(sc->sc_dmat, 974 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 975 976 fail_4: 977 /* Destroy DMA maps for TX buffers. */ 978 for (i = 0; i < RE_TX_QLEN; i++) 979 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 980 bus_dmamap_destroy(sc->sc_dmat, 981 sc->re_ldata.re_txq[i].txq_dmamap); 982 983 /* Free DMA'able memory for the TX ring. */ 984 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 985 fail_3: 986 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 987 fail_2: 988 bus_dmamem_unmap(sc->sc_dmat, 989 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 990 fail_1: 991 bus_dmamem_free(sc->sc_dmat, 992 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 993 fail_0: 994 return; 995 } 996 997 998 /* 999 * re_activate: 1000 * Handle device activation/deactivation requests. 1001 */ 1002 int 1003 re_activate(device_t self, enum devact act) 1004 { 1005 struct rtk_softc *sc = device_private(self); 1006 1007 switch (act) { 1008 case DVACT_DEACTIVATE: 1009 if_deactivate(&sc->ethercom.ec_if); 1010 return 0; 1011 default: 1012 return EOPNOTSUPP; 1013 } 1014 } 1015 1016 /* 1017 * re_detach: 1018 * Detach a rtk interface. 1019 */ 1020 int 1021 re_detach(struct rtk_softc *sc) 1022 { 1023 struct ifnet *ifp = &sc->ethercom.ec_if; 1024 int i; 1025 1026 /* 1027 * Succeed now if there isn't any work to do. 1028 */ 1029 if ((sc->sc_flags & RTK_ATTACHED) == 0) 1030 return 0; 1031 1032 /* Unhook our tick handler. */ 1033 callout_stop(&sc->rtk_tick_ch); 1034 1035 /* Detach all PHYs. */ 1036 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 1037 1038 rnd_detach_source(&sc->rnd_source); 1039 ether_ifdetach(ifp); 1040 if_detach(ifp); 1041 1042 /* Delete all remaining media. */ 1043 ifmedia_fini(&sc->mii.mii_media); 1044 1045 /* Destroy DMA maps for RX buffers. */ 1046 for (i = 0; i < RE_RX_DESC_CNT; i++) 1047 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 1048 bus_dmamap_destroy(sc->sc_dmat, 1049 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 1050 1051 /* Free DMA'able memory for the RX ring. */ 1052 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 1053 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 1054 bus_dmamem_unmap(sc->sc_dmat, 1055 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 1056 bus_dmamem_free(sc->sc_dmat, 1057 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 1058 1059 /* Destroy DMA maps for TX buffers. */ 1060 for (i = 0; i < RE_TX_QLEN; i++) 1061 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 1062 bus_dmamap_destroy(sc->sc_dmat, 1063 sc->re_ldata.re_txq[i].txq_dmamap); 1064 1065 /* Free DMA'able memory for the TX ring. */ 1066 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1067 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1068 bus_dmamem_unmap(sc->sc_dmat, 1069 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1070 bus_dmamem_free(sc->sc_dmat, 1071 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 1072 1073 pmf_device_deregister(sc->sc_dev); 1074 1075 /* we don't want to run again */ 1076 sc->sc_flags &= ~RTK_ATTACHED; 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * re_enable: 1083 * Enable the RTL81X9 chip. 1084 */ 1085 static int 1086 re_enable(struct rtk_softc *sc) 1087 { 1088 1089 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 1090 if ((*sc->sc_enable)(sc) != 0) { 1091 printf("%s: device enable failed\n", 1092 device_xname(sc->sc_dev)); 1093 return EIO; 1094 } 1095 sc->sc_flags |= RTK_ENABLED; 1096 } 1097 return 0; 1098 } 1099 1100 /* 1101 * re_disable: 1102 * Disable the RTL81X9 chip. 1103 */ 1104 static void 1105 re_disable(struct rtk_softc *sc) 1106 { 1107 1108 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1109 (*sc->sc_disable)(sc); 1110 sc->sc_flags &= ~RTK_ENABLED; 1111 } 1112 } 1113 1114 static int 1115 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1116 { 1117 struct mbuf *n = NULL; 1118 bus_dmamap_t map; 1119 struct re_desc *d; 1120 struct re_rxsoft *rxs; 1121 uint32_t cmdstat; 1122 int error; 1123 1124 if (m == NULL) { 1125 MGETHDR(n, M_DONTWAIT, MT_DATA); 1126 if (n == NULL) 1127 return ENOBUFS; 1128 1129 MCLAIM(n, &sc->ethercom.ec_rx_mowner); 1130 MCLGET(n, M_DONTWAIT); 1131 if ((n->m_flags & M_EXT) == 0) { 1132 m_freem(n); 1133 return ENOBUFS; 1134 } 1135 m = n; 1136 } else 1137 m->m_data = m->m_ext.ext_buf; 1138 1139 /* 1140 * Initialize mbuf length fields and fixup 1141 * alignment so that the frame payload is 1142 * longword aligned. 1143 */ 1144 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1145 m->m_data += RE_ETHER_ALIGN; 1146 1147 rxs = &sc->re_ldata.re_rxsoft[idx]; 1148 map = rxs->rxs_dmamap; 1149 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1150 BUS_DMA_READ|BUS_DMA_NOWAIT); 1151 1152 if (error) 1153 goto out; 1154 1155 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1156 BUS_DMASYNC_PREREAD); 1157 1158 d = &sc->re_ldata.re_rx_list[idx]; 1159 #ifdef DIAGNOSTIC 1160 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1161 cmdstat = le32toh(d->re_cmdstat); 1162 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1163 if (cmdstat & RE_RDESC_STAT_OWN) { 1164 panic("%s: tried to map busy RX descriptor", 1165 device_xname(sc->sc_dev)); 1166 } 1167 #endif 1168 1169 rxs->rxs_mbuf = m; 1170 1171 d->re_vlanctl = 0; 1172 cmdstat = map->dm_segs[0].ds_len; 1173 if (idx == (RE_RX_DESC_CNT - 1)) 1174 cmdstat |= RE_RDESC_CMD_EOR; 1175 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1176 d->re_cmdstat = htole32(cmdstat); 1177 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1178 cmdstat |= RE_RDESC_CMD_OWN; 1179 d->re_cmdstat = htole32(cmdstat); 1180 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1181 1182 return 0; 1183 out: 1184 m_freem(n); 1185 return ENOMEM; 1186 } 1187 1188 static int 1189 re_tx_list_init(struct rtk_softc *sc) 1190 { 1191 int i; 1192 1193 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1194 for (i = 0; i < RE_TX_QLEN; i++) { 1195 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1196 } 1197 1198 bus_dmamap_sync(sc->sc_dmat, 1199 sc->re_ldata.re_tx_list_map, 0, 1200 sc->re_ldata.re_tx_list_map->dm_mapsize, 1201 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1202 sc->re_ldata.re_txq_prodidx = 0; 1203 sc->re_ldata.re_txq_considx = 0; 1204 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1205 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1206 sc->re_ldata.re_tx_nextfree = 0; 1207 1208 return 0; 1209 } 1210 1211 static int 1212 re_rx_list_init(struct rtk_softc *sc) 1213 { 1214 int i; 1215 1216 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1217 1218 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1219 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1220 return ENOBUFS; 1221 } 1222 1223 sc->re_ldata.re_rx_prodidx = 0; 1224 sc->re_head = sc->re_tail = NULL; 1225 1226 return 0; 1227 } 1228 1229 /* 1230 * RX handler for C+ and 8169. For the gigE chips, we support 1231 * the reception of jumbo frames that have been fragmented 1232 * across multiple 2K mbuf cluster buffers. 1233 */ 1234 static void 1235 re_rxeof(struct rtk_softc *sc) 1236 { 1237 struct mbuf *m; 1238 struct ifnet *ifp; 1239 int i, total_len; 1240 struct re_desc *cur_rx; 1241 struct re_rxsoft *rxs; 1242 uint32_t rxstat, rxvlan; 1243 1244 ifp = &sc->ethercom.ec_if; 1245 1246 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1247 cur_rx = &sc->re_ldata.re_rx_list[i]; 1248 RE_RXDESCSYNC(sc, i, 1249 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1250 rxstat = le32toh(cur_rx->re_cmdstat); 1251 rxvlan = le32toh(cur_rx->re_vlanctl); 1252 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1253 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1254 break; 1255 } 1256 total_len = rxstat & sc->re_rxlenmask; 1257 rxs = &sc->re_ldata.re_rxsoft[i]; 1258 m = rxs->rxs_mbuf; 1259 1260 /* Invalidate the RX mbuf and unload its map */ 1261 1262 bus_dmamap_sync(sc->sc_dmat, 1263 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1264 BUS_DMASYNC_POSTREAD); 1265 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1266 1267 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1268 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1269 if (sc->re_head == NULL) 1270 sc->re_head = sc->re_tail = m; 1271 else { 1272 m_remove_pkthdr(m); 1273 sc->re_tail->m_next = m; 1274 sc->re_tail = m; 1275 } 1276 re_newbuf(sc, i, NULL); 1277 continue; 1278 } 1279 1280 /* 1281 * NOTE: for the 8139C+, the frame length field 1282 * is always 12 bits in size, but for the gigE chips, 1283 * it is 13 bits (since the max RX frame length is 16K). 1284 * Unfortunately, all 32 bits in the status word 1285 * were already used, so to make room for the extra 1286 * length bit, RealTek took out the 'frame alignment 1287 * error' bit and shifted the other status bits 1288 * over one slot. The OWN, EOR, FS and LS bits are 1289 * still in the same places. We have already extracted 1290 * the frame length and checked the OWN bit, so rather 1291 * than using an alternate bit mapping, we shift the 1292 * status bits one space to the right so we can evaluate 1293 * them using the 8169 status as though it was in the 1294 * same format as that of the 8139C+. 1295 */ 1296 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1297 rxstat >>= 1; 1298 1299 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1300 #ifdef RE_DEBUG 1301 printf("%s: RX error (rxstat = 0x%08x)", 1302 device_xname(sc->sc_dev), rxstat); 1303 if (rxstat & RE_RDESC_STAT_FRALIGN) 1304 printf(", frame alignment error"); 1305 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1306 printf(", out of buffer space"); 1307 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1308 printf(", FIFO overrun"); 1309 if (rxstat & RE_RDESC_STAT_GIANT) 1310 printf(", giant packet"); 1311 if (rxstat & RE_RDESC_STAT_RUNT) 1312 printf(", runt packet"); 1313 if (rxstat & RE_RDESC_STAT_CRCERR) 1314 printf(", CRC error"); 1315 printf("\n"); 1316 #endif 1317 if_statinc(ifp, if_ierrors); 1318 /* 1319 * If this is part of a multi-fragment packet, 1320 * discard all the pieces. 1321 */ 1322 if (sc->re_head != NULL) { 1323 m_freem(sc->re_head); 1324 sc->re_head = sc->re_tail = NULL; 1325 } 1326 re_newbuf(sc, i, m); 1327 continue; 1328 } 1329 1330 /* 1331 * If allocating a replacement mbuf fails, 1332 * reload the current one. 1333 */ 1334 1335 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1336 if_statinc(ifp, if_ierrors); 1337 if (sc->re_head != NULL) { 1338 m_freem(sc->re_head); 1339 sc->re_head = sc->re_tail = NULL; 1340 } 1341 re_newbuf(sc, i, m); 1342 continue; 1343 } 1344 1345 if (sc->re_head != NULL) { 1346 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1347 /* 1348 * Special case: if there's 4 bytes or less 1349 * in this buffer, the mbuf can be discarded: 1350 * the last 4 bytes is the CRC, which we don't 1351 * care about anyway. 1352 */ 1353 if (m->m_len <= ETHER_CRC_LEN) { 1354 sc->re_tail->m_len -= 1355 (ETHER_CRC_LEN - m->m_len); 1356 m_freem(m); 1357 } else { 1358 m->m_len -= ETHER_CRC_LEN; 1359 m_remove_pkthdr(m); 1360 sc->re_tail->m_next = m; 1361 } 1362 m = sc->re_head; 1363 sc->re_head = sc->re_tail = NULL; 1364 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1365 } else 1366 m->m_pkthdr.len = m->m_len = 1367 (total_len - ETHER_CRC_LEN); 1368 1369 m_set_rcvif(m, ifp); 1370 1371 /* Do RX checksumming */ 1372 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1373 /* Check IP header checksum */ 1374 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1375 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1376 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1377 m->m_pkthdr.csum_flags |= 1378 M_CSUM_IPv4_BAD; 1379 1380 /* Check TCP/UDP checksum */ 1381 if (RE_TCPPKT(rxstat)) { 1382 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1383 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1384 m->m_pkthdr.csum_flags |= 1385 M_CSUM_TCP_UDP_BAD; 1386 } else if (RE_UDPPKT(rxstat)) { 1387 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1388 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) { 1389 /* 1390 * XXX: 8139C+ thinks UDP csum 1391 * 0xFFFF is bad, force software 1392 * calculation. 1393 */ 1394 if (sc->sc_quirk & RTKQ_8139CPLUS) 1395 m->m_pkthdr.csum_flags 1396 &= ~M_CSUM_UDPv4; 1397 else 1398 m->m_pkthdr.csum_flags 1399 |= M_CSUM_TCP_UDP_BAD; 1400 } 1401 } 1402 } 1403 } else { 1404 /* Check IPv4 header checksum */ 1405 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1406 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1407 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1408 m->m_pkthdr.csum_flags |= 1409 M_CSUM_IPv4_BAD; 1410 1411 /* Check TCPv4/UDPv4 checksum */ 1412 if (RE_TCPPKT(rxstat)) { 1413 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1414 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1415 m->m_pkthdr.csum_flags |= 1416 M_CSUM_TCP_UDP_BAD; 1417 } else if (RE_UDPPKT(rxstat)) { 1418 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1419 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1420 m->m_pkthdr.csum_flags |= 1421 M_CSUM_TCP_UDP_BAD; 1422 } 1423 } 1424 /* XXX Check TCPv6/UDPv6 checksum? */ 1425 } 1426 1427 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1428 vlan_set_tag(m, 1429 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA)); 1430 } 1431 if_percpuq_enqueue(ifp->if_percpuq, m); 1432 } 1433 1434 sc->re_ldata.re_rx_prodidx = i; 1435 } 1436 1437 static void 1438 re_txeof(struct rtk_softc *sc) 1439 { 1440 struct ifnet *ifp; 1441 struct re_txq *txq; 1442 uint32_t txstat; 1443 int idx, descidx; 1444 1445 ifp = &sc->ethercom.ec_if; 1446 1447 for (idx = sc->re_ldata.re_txq_considx; 1448 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1449 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1450 txq = &sc->re_ldata.re_txq[idx]; 1451 KASSERT(txq->txq_mbuf != NULL); 1452 1453 descidx = txq->txq_descidx; 1454 RE_TXDESCSYNC(sc, descidx, 1455 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1456 txstat = 1457 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1458 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1459 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1460 if (txstat & RE_TDESC_CMD_OWN) { 1461 break; 1462 } 1463 1464 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1465 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1466 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1467 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1468 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1469 m_freem(txq->txq_mbuf); 1470 txq->txq_mbuf = NULL; 1471 1472 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1473 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1474 if_statinc_ref(ifp, nsr, if_collisions); 1475 if (txstat & RE_TDESC_STAT_TXERRSUM) 1476 if_statinc_ref(ifp, nsr, if_oerrors); 1477 else 1478 if_statinc_ref(ifp, nsr, if_opackets); 1479 IF_STAT_PUTREF(ifp); 1480 } 1481 1482 sc->re_ldata.re_txq_considx = idx; 1483 1484 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1485 ifp->if_flags &= ~IFF_OACTIVE; 1486 1487 /* 1488 * If not all descriptors have been released reaped yet, 1489 * reload the timer so that we will eventually get another 1490 * interrupt that will cause us to re-enter this routine. 1491 * This is done in case the transmitter has gone idle. 1492 */ 1493 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1494 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) 1495 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1496 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1497 /* 1498 * Some chips will ignore a second TX request 1499 * issued while an existing transmission is in 1500 * progress. If the transmitter goes idle but 1501 * there are still packets waiting to be sent, 1502 * we need to restart the channel here to flush 1503 * them out. This only seems to be required with 1504 * the PCIe devices. 1505 */ 1506 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1507 } 1508 } else 1509 ifp->if_timer = 0; 1510 } 1511 1512 static void 1513 re_tick(void *arg) 1514 { 1515 struct rtk_softc *sc = arg; 1516 int s; 1517 1518 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1519 s = splnet(); 1520 1521 mii_tick(&sc->mii); 1522 splx(s); 1523 1524 callout_schedule(&sc->rtk_tick_ch, hz); 1525 } 1526 1527 int 1528 re_intr(void *arg) 1529 { 1530 struct rtk_softc *sc = arg; 1531 struct ifnet *ifp; 1532 uint16_t status, rndstatus = 0; 1533 int handled = 0; 1534 1535 if (!device_has_power(sc->sc_dev)) 1536 return 0; 1537 1538 ifp = &sc->ethercom.ec_if; 1539 1540 if ((ifp->if_flags & IFF_UP) == 0) 1541 return 0; 1542 1543 const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ? 1544 RTK_INTRS_IM_HW : RTK_INTRS_CPLUS; 1545 1546 for (;;) { 1547 1548 status = CSR_READ_2(sc, RTK_ISR); 1549 /* If the card has gone away the read returns 0xffff. */ 1550 if (status == 0xffff) 1551 break; 1552 if (status != 0) { 1553 handled = 1; 1554 CSR_WRITE_2(sc, RTK_ISR, status); 1555 rndstatus = status; 1556 } 1557 1558 if ((status & status_mask) == 0) 1559 break; 1560 1561 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1562 re_rxeof(sc); 1563 1564 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1565 RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK)) 1566 re_txeof(sc); 1567 1568 if (status & RTK_ISR_SYSTEM_ERR) { 1569 re_init(ifp); 1570 } 1571 1572 if (status & RTK_ISR_LINKCHG) { 1573 callout_stop(&sc->rtk_tick_ch); 1574 re_tick(sc); 1575 } 1576 } 1577 1578 if (handled) 1579 if_schedule_deferred_start(ifp); 1580 1581 rnd_add_uint32(&sc->rnd_source, rndstatus); 1582 1583 return handled; 1584 } 1585 1586 1587 1588 /* 1589 * Main transmit routine for C+ and gigE NICs. 1590 */ 1591 1592 static void 1593 re_start(struct ifnet *ifp) 1594 { 1595 struct rtk_softc *sc; 1596 struct mbuf *m; 1597 bus_dmamap_t map; 1598 struct re_txq *txq; 1599 struct re_desc *d; 1600 uint32_t cmdstat, re_flags, vlanctl; 1601 int ofree, idx, error, nsegs, seg; 1602 int startdesc, curdesc, lastdesc; 1603 bool pad; 1604 1605 sc = ifp->if_softc; 1606 ofree = sc->re_ldata.re_txq_free; 1607 1608 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1609 1610 IFQ_POLL(&ifp->if_snd, m); 1611 if (m == NULL) 1612 break; 1613 1614 if (sc->re_ldata.re_txq_free == 0 || 1615 sc->re_ldata.re_tx_free == 0) { 1616 /* no more free slots left */ 1617 ifp->if_flags |= IFF_OACTIVE; 1618 break; 1619 } 1620 1621 /* 1622 * Set up checksum offload. Note: checksum offload bits must 1623 * appear in all descriptors of a multi-descriptor transmit 1624 * attempt. (This is according to testing done with an 8169 1625 * chip. I'm not sure if this is a requirement or a bug.) 1626 */ 1627 1628 vlanctl = 0; 1629 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1630 uint32_t segsz = m->m_pkthdr.segsz; 1631 1632 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1633 re_flags = RE_TDESC_CMD_LGSEND | 1634 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1635 } else { 1636 re_flags = RE_TDESC_CMD_LGSEND_V4; 1637 vlanctl |= 1638 (segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT); 1639 } 1640 } else { 1641 /* 1642 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1643 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1644 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1645 */ 1646 re_flags = 0; 1647 if ((m->m_pkthdr.csum_flags & 1648 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1649 != 0) { 1650 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1651 re_flags |= RE_TDESC_CMD_IPCSUM; 1652 if (m->m_pkthdr.csum_flags & 1653 M_CSUM_TCPv4) { 1654 re_flags |= 1655 RE_TDESC_CMD_TCPCSUM; 1656 } else if (m->m_pkthdr.csum_flags & 1657 M_CSUM_UDPv4) { 1658 re_flags |= 1659 RE_TDESC_CMD_UDPCSUM; 1660 } 1661 } else { 1662 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1663 if (m->m_pkthdr.csum_flags & 1664 M_CSUM_TCPv4) { 1665 vlanctl |= 1666 RE_TDESC_VLANCTL_TCPCSUM; 1667 } else if (m->m_pkthdr.csum_flags & 1668 M_CSUM_UDPv4) { 1669 vlanctl |= 1670 RE_TDESC_VLANCTL_UDPCSUM; 1671 } 1672 } 1673 } 1674 } 1675 1676 txq = &sc->re_ldata.re_txq[idx]; 1677 map = txq->txq_dmamap; 1678 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1679 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1680 1681 if (__predict_false(error)) { 1682 /* XXX try to defrag if EFBIG? */ 1683 printf("%s: can't map mbuf (error %d)\n", 1684 device_xname(sc->sc_dev), error); 1685 1686 IFQ_DEQUEUE(&ifp->if_snd, m); 1687 m_freem(m); 1688 if_statinc(ifp, if_oerrors); 1689 continue; 1690 } 1691 1692 nsegs = map->dm_nsegs; 1693 pad = false; 1694 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1695 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1696 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1697 pad = true; 1698 nsegs++; 1699 } 1700 1701 if (nsegs > sc->re_ldata.re_tx_free) { 1702 /* 1703 * Not enough free descriptors to transmit this packet. 1704 */ 1705 ifp->if_flags |= IFF_OACTIVE; 1706 bus_dmamap_unload(sc->sc_dmat, map); 1707 break; 1708 } 1709 1710 IFQ_DEQUEUE(&ifp->if_snd, m); 1711 1712 /* 1713 * Make sure that the caches are synchronized before we 1714 * ask the chip to start DMA for the packet data. 1715 */ 1716 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1717 BUS_DMASYNC_PREWRITE); 1718 1719 /* 1720 * Set up hardware VLAN tagging. Note: vlan tag info must 1721 * appear in all descriptors of a multi-descriptor 1722 * transmission attempt. 1723 */ 1724 if (vlan_has_tag(m)) 1725 vlanctl |= bswap16(vlan_get_tag(m)) | 1726 RE_TDESC_VLANCTL_TAG; 1727 1728 /* 1729 * Map the segment array into descriptors. 1730 * Note that we set the start-of-frame and 1731 * end-of-frame markers for either TX or RX, 1732 * but they really only have meaning in the TX case. 1733 * (In the RX case, it's the chip that tells us 1734 * where packets begin and end.) 1735 * We also keep track of the end of the ring 1736 * and set the end-of-ring bits as needed, 1737 * and we set the ownership bits in all except 1738 * the very first descriptor. (The caller will 1739 * set this descriptor later when it start 1740 * transmission or reception.) 1741 */ 1742 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1743 lastdesc = -1; 1744 for (seg = 0; seg < map->dm_nsegs; 1745 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1746 d = &sc->re_ldata.re_tx_list[curdesc]; 1747 #ifdef DIAGNOSTIC 1748 RE_TXDESCSYNC(sc, curdesc, 1749 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1750 cmdstat = le32toh(d->re_cmdstat); 1751 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1752 if (cmdstat & RE_TDESC_STAT_OWN) { 1753 panic("%s: tried to map busy TX descriptor", 1754 device_xname(sc->sc_dev)); 1755 } 1756 #endif 1757 1758 d->re_vlanctl = htole32(vlanctl); 1759 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1760 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1761 if (seg == 0) 1762 cmdstat |= RE_TDESC_CMD_SOF; 1763 else 1764 cmdstat |= RE_TDESC_CMD_OWN; 1765 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1766 cmdstat |= RE_TDESC_CMD_EOR; 1767 if (seg == nsegs - 1) { 1768 cmdstat |= RE_TDESC_CMD_EOF; 1769 lastdesc = curdesc; 1770 } 1771 d->re_cmdstat = htole32(cmdstat); 1772 RE_TXDESCSYNC(sc, curdesc, 1773 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1774 } 1775 if (__predict_false(pad)) { 1776 d = &sc->re_ldata.re_tx_list[curdesc]; 1777 d->re_vlanctl = htole32(vlanctl); 1778 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1779 cmdstat = re_flags | 1780 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1781 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1782 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1783 cmdstat |= RE_TDESC_CMD_EOR; 1784 d->re_cmdstat = htole32(cmdstat); 1785 RE_TXDESCSYNC(sc, curdesc, 1786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1787 lastdesc = curdesc; 1788 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1789 } 1790 KASSERT(lastdesc != -1); 1791 1792 /* Transfer ownership of packet to the chip. */ 1793 1794 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1795 htole32(RE_TDESC_CMD_OWN); 1796 RE_TXDESCSYNC(sc, startdesc, 1797 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1798 1799 /* update info of TX queue and descriptors */ 1800 txq->txq_mbuf = m; 1801 txq->txq_descidx = lastdesc; 1802 txq->txq_nsegs = nsegs; 1803 1804 sc->re_ldata.re_txq_free--; 1805 sc->re_ldata.re_tx_free -= nsegs; 1806 sc->re_ldata.re_tx_nextfree = curdesc; 1807 1808 /* 1809 * If there's a BPF listener, bounce a copy of this frame 1810 * to him. 1811 */ 1812 bpf_mtap(ifp, m, BPF_D_OUT); 1813 } 1814 1815 if (sc->re_ldata.re_txq_free < ofree) { 1816 /* 1817 * TX packets are enqueued. 1818 */ 1819 sc->re_ldata.re_txq_prodidx = idx; 1820 1821 /* 1822 * Start the transmitter to poll. 1823 * 1824 * RealTek put the TX poll request register in a different 1825 * location on the 8169 gigE chip. I don't know why. 1826 */ 1827 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1828 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1829 else 1830 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1831 1832 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1833 /* 1834 * Use the countdown timer for interrupt moderation. 1835 * 'TX done' interrupts are disabled. Instead, we reset 1836 * the countdown timer, which will begin counting until 1837 * it hits the value in the TIMERINT register, and then 1838 * trigger an interrupt. Each time we write to the 1839 * TIMERCNT register, the timer count is reset to 0. 1840 */ 1841 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1842 } 1843 1844 /* 1845 * Set a timeout in case the chip goes out to lunch. 1846 */ 1847 ifp->if_timer = 5; 1848 } 1849 } 1850 1851 static int 1852 re_init(struct ifnet *ifp) 1853 { 1854 struct rtk_softc *sc = ifp->if_softc; 1855 uint32_t rxcfg = 0; 1856 uint16_t cfg; 1857 int error; 1858 #ifdef RE_USE_EECMD 1859 const uint8_t *enaddr; 1860 uint32_t reg; 1861 #endif 1862 1863 if ((error = re_enable(sc)) != 0) 1864 goto out; 1865 1866 /* 1867 * Cancel pending I/O and free all RX/TX buffers. 1868 */ 1869 re_stop(ifp, 0); 1870 1871 re_reset(sc); 1872 1873 /* 1874 * Enable C+ RX and TX mode, as well as VLAN stripping and 1875 * RX checksum offload. We must configure the C+ register 1876 * before all others. 1877 */ 1878 cfg = RE_CPLUSCMD_PCI_MRW; 1879 1880 /* 1881 * XXX: For old 8169 set bit 14. 1882 * For 8169S/8110S and above, do not set bit 14. 1883 */ 1884 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1885 cfg |= (0x1 << 14); 1886 1887 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1888 cfg |= RE_CPLUSCMD_VLANSTRIP; 1889 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1890 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1891 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1892 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1893 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1894 cfg |= RE_CPLUSCMD_TXENB; 1895 } else 1896 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1897 1898 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1899 1900 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1901 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 1902 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1903 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1904 } else { 1905 CSR_WRITE_2(sc, RTK_IM, 0x5151); 1906 } 1907 } 1908 1909 DELAY(10000); 1910 1911 #ifdef RE_USE_EECMD 1912 /* 1913 * Init our MAC address. Even though the chipset 1914 * documentation doesn't mention it, we need to enter "Config 1915 * register write enable" mode to modify the ID registers. 1916 */ 1917 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1918 enaddr = CLLADDR(ifp->if_sadl); 1919 reg = enaddr[0] | (enaddr[1] << 8) | 1920 (enaddr[2] << 16) | (enaddr[3] << 24); 1921 CSR_WRITE_4(sc, RTK_IDR0, reg); 1922 reg = enaddr[4] | (enaddr[5] << 8); 1923 CSR_WRITE_4(sc, RTK_IDR4, reg); 1924 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1925 #endif 1926 1927 /* 1928 * For C+ mode, initialize the RX descriptors and mbufs. 1929 */ 1930 re_rx_list_init(sc); 1931 re_tx_list_init(sc); 1932 1933 /* 1934 * Load the addresses of the RX and TX lists into the chip. 1935 */ 1936 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1937 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1938 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1939 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1940 1941 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1942 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1943 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1944 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1945 1946 if (sc->sc_quirk & RTKQ_RXDV_GATED) { 1947 CSR_WRITE_4(sc, RTK_MISC, 1948 CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN); 1949 } 1950 1951 /* 1952 * Enable transmit and receive. 1953 */ 1954 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0) 1955 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1956 1957 /* 1958 * Set the initial TX and RX configuration. 1959 */ 1960 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1961 /* test mode is needed only for old 8169 */ 1962 CSR_WRITE_4(sc, RTK_TXCFG, 1963 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1964 } else 1965 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1966 1967 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1968 1969 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1970 1971 /* Set the individual bit to receive frames for this host only. */ 1972 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1973 rxcfg |= RTK_RXCFG_RX_INDIV; 1974 if (sc->sc_quirk & RTKQ_EARLYOFF) 1975 rxcfg |= RTK_RXCFG_EARLYOFF; 1976 else if (sc->sc_quirk & RTKQ_RXDV_GATED) 1977 rxcfg |= RTK_RXCFG_EARLYOFFV2; 1978 1979 /* If we want promiscuous mode, set the allframes bit. */ 1980 if (ifp->if_flags & IFF_PROMISC) 1981 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1982 else 1983 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1984 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1985 1986 /* 1987 * Set capture broadcast bit to capture broadcast frames. 1988 */ 1989 if (ifp->if_flags & IFF_BROADCAST) 1990 rxcfg |= RTK_RXCFG_RX_BROAD; 1991 else 1992 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1993 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1994 1995 /* 1996 * Program the multicast filter, if necessary. 1997 */ 1998 rtk_setmulti(sc); 1999 2000 /* 2001 * some chips require to enable TX/RX *AFTER* TX/RX configuration 2002 */ 2003 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0) 2004 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 2005 2006 /* 2007 * Enable interrupts. 2008 */ 2009 if (sc->re_testmode) 2010 CSR_WRITE_2(sc, RTK_IMR, 0); 2011 else if ((sc->sc_quirk & RTKQ_IM_HW) != 0) 2012 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW); 2013 else 2014 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 2015 2016 /* Start RX/TX process. */ 2017 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 2018 #ifdef notdef 2019 /* Enable receiver and transmitter. */ 2020 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 2021 #endif 2022 2023 /* 2024 * Initialize the timer interrupt register so that 2025 * a timer interrupt will be generated once the timer 2026 * reaches a certain number of ticks. The timer is 2027 * reloaded on each transmit. This gives us TX interrupt 2028 * moderation, which dramatically improves TX frame rate. 2029 */ 2030 2031 unsigned defer; /* timer interval / ns */ 2032 unsigned period; /* busclock period / ns */ 2033 2034 /* 2035 * Maximum frame rate 2036 * 1500 byte PDU -> 81274 Hz 2037 * 46 byte PDU -> 1488096 Hz 2038 * 2039 * Deferring interrupts by up to 128us needs descriptors for 2040 * 1500 byte PDU -> 10.4 frames 2041 * 46 byte PDU -> 190.4 frames 2042 * 2043 */ 2044 defer = 128000; 2045 2046 if ((sc->sc_quirk & RTKQ_IM_HW) != 0) { 2047 period = 1; 2048 defer = 0; 2049 } else if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 2050 period = 8; 2051 } else { 2052 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) { 2053 case RTK_BUSFREQ_33MHZ: 2054 period = 30; 2055 break; 2056 case RTK_BUSFREQ_66MHZ: 2057 period = 15; 2058 break; 2059 default: 2060 /* lowest possible clock */ 2061 period = 60; 2062 break; 2063 } 2064 } 2065 2066 /* Timer Interrupt register address varies */ 2067 uint16_t re8139_reg; 2068 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 2069 re8139_reg = RTK_TIMERINT; 2070 else 2071 re8139_reg = RTK_TIMERINT_8169; 2072 CSR_WRITE_4(sc, re8139_reg, defer / period); 2073 2074 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 2075 /* 2076 * For 8169 gigE NICs, set the max allowed RX packet 2077 * size so we can receive jumbo frames. 2078 */ 2079 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 2080 } 2081 2082 if (sc->re_testmode) 2083 return 0; 2084 2085 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 2086 2087 ifp->if_flags |= IFF_RUNNING; 2088 ifp->if_flags &= ~IFF_OACTIVE; 2089 2090 callout_schedule(&sc->rtk_tick_ch, hz); 2091 2092 out: 2093 if (error) { 2094 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2095 ifp->if_timer = 0; 2096 printf("%s: interface not running\n", 2097 device_xname(sc->sc_dev)); 2098 } 2099 2100 return error; 2101 } 2102 2103 static int 2104 re_ioctl(struct ifnet *ifp, u_long command, void *data) 2105 { 2106 struct rtk_softc *sc = ifp->if_softc; 2107 struct ifreq *ifr = data; 2108 int s, error = 0; 2109 2110 s = splnet(); 2111 2112 switch (command) { 2113 case SIOCSIFMTU: 2114 /* 2115 * Disable jumbo frames if it's not supported. 2116 */ 2117 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 2118 ifr->ifr_mtu > ETHERMTU) { 2119 error = EINVAL; 2120 break; 2121 } 2122 2123 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2124 error = EINVAL; 2125 else if ((error = ifioctl_common(ifp, command, data)) == 2126 ENETRESET) 2127 error = 0; 2128 break; 2129 default: 2130 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2131 break; 2132 2133 error = 0; 2134 2135 if (command == SIOCSIFCAP) 2136 error = if_init(ifp); 2137 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2138 ; 2139 else if (ifp->if_flags & IFF_RUNNING) 2140 rtk_setmulti(sc); 2141 break; 2142 } 2143 2144 splx(s); 2145 2146 return error; 2147 } 2148 2149 static void 2150 re_watchdog(struct ifnet *ifp) 2151 { 2152 struct rtk_softc *sc; 2153 int s; 2154 2155 sc = ifp->if_softc; 2156 s = splnet(); 2157 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2158 if_statinc(ifp, if_oerrors); 2159 2160 re_txeof(sc); 2161 re_rxeof(sc); 2162 2163 re_init(ifp); 2164 2165 splx(s); 2166 } 2167 2168 /* 2169 * Stop the adapter and free any mbufs allocated to the 2170 * RX and TX lists. 2171 */ 2172 static void 2173 re_stop(struct ifnet *ifp, int disable) 2174 { 2175 int i; 2176 struct rtk_softc *sc = ifp->if_softc; 2177 2178 callout_stop(&sc->rtk_tick_ch); 2179 2180 mii_down(&sc->mii); 2181 2182 /* 2183 * Disable accepting frames to put RX MAC into idle state. 2184 * Otherwise it's possible to get frames while stop command 2185 * execution is in progress and controller can DMA the frame 2186 * to already freed RX buffer during that period. 2187 */ 2188 CSR_WRITE_4(sc, RTK_RXCFG, CSR_READ_4(sc, RTK_RXCFG) & 2189 ~(RTK_RXCFG_RX_ALLPHYS | RTK_RXCFG_RX_INDIV | RTK_RXCFG_RX_MULTI | 2190 RTK_RXCFG_RX_BROAD)); 2191 2192 if (sc->sc_quirk & RTKQ_RXDV_GATED) { 2193 CSR_WRITE_4(sc, RTK_MISC, 2194 CSR_READ_4(sc, RTK_MISC) | RTK_MISC_RXDV_GATED_EN); 2195 } 2196 2197 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 2198 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 2199 RTK_CMD_RX_ENB); 2200 else 2201 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2202 DELAY(1000); 2203 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2204 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 2205 2206 if (sc->re_head != NULL) { 2207 m_freem(sc->re_head); 2208 sc->re_head = sc->re_tail = NULL; 2209 } 2210 2211 /* Free the TX list buffers. */ 2212 for (i = 0; i < RE_TX_QLEN; i++) { 2213 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2214 bus_dmamap_unload(sc->sc_dmat, 2215 sc->re_ldata.re_txq[i].txq_dmamap); 2216 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2217 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2218 } 2219 } 2220 2221 /* Free the RX list buffers. */ 2222 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2223 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2224 bus_dmamap_unload(sc->sc_dmat, 2225 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2226 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2227 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2228 } 2229 } 2230 2231 if (disable) 2232 re_disable(sc); 2233 2234 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2235 ifp->if_timer = 0; 2236 } 2237
Indexes created Sat Sep 20 22:09:52 GMT 2025