| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_vegam_smumgr.c | 727 uint32_t ref_clock; local in function:vegam_calculate_sclk_params
751 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
763 ref_clock);
766 do_div(temp, ref_clock);
773 ref_clock);
782 ref_clock);
785 do_div(temp, ref_clock);
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| amdgpu_ci_smumgr.c | 310 uint32_t ref_clock; local in function:ci_calculate_sclk_params
323 ref_clock = atomctrl_get_reference_clock(hwmgr);
350 uint32_t clk_s = ref_clock * 5 /
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| amdgpu_fiji_smumgr.c | 872 uint32_t ref_clock; local in function:fiji_calculate_sclk_params
885 ref_clock = atomctrl_get_reference_clock(hwmgr);
918 uint32_t clk_s = ref_clock * 5 /
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| amdgpu_polaris10_smumgr.c | 852 uint32_t ref_clock; local in function:polaris10_calculate_sclk_params
876 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
886 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
889 do_div(temp, ref_clock);
894 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
901 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
904 do_div(temp, ref_clock);
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_ddi.c | 1380 u32 p0, p1, p2, dco_freq, ref_clock; local in function:cnl_calc_wrpll_link
1419 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1422 * ref_clock;
1425 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1458 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; local in function:icl_calc_mg_pll_link
1461 ref_clock = dev_priv->cdclk.hw.ref;
1519 tmp = (u64)m1 * m2_int * ref_clock +
1520 (((u64)m1 * m2_frac * ref_clock) >> 22);
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| intel_dpll_mgr.c | 2268 int ref_clock = dev_priv->cdclk.hw.ref; local in function:cnl_hdmi_pll_ref_clock
2274 if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
2275 ref_clock = 19200;
2277 return ref_clock;
2286 u32 ref_clock; local in function:cnl_ddi_calculate_wrpll
2319 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
2321 cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu7_hwmgr.c | 4082 uint32_t ref_clock, refresh_rate; local in function:smu7_program_display_gap
4087 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4104 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ci_dpm.c | 1996 u32 ref_clock = rdev->clock.spll.reference_freq; local in function:ci_program_display_gap
2014 tmp = pre_vbi_time_in_us * (ref_clock / 100);
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