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    Searched defs:reg1 (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/arch/powerpc/pci/
pchb.c 80 pcireg_t reg1, reg2; local in function:mpc105_print
83 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR1);
103 switch (reg1 & MPC105_PICR1_L2_MP) {
123 pcireg_t reg1, reg2; local in function:mpc106_print
126 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR1);
146 switch (reg1 & MPC106_PICR1_EXT_L2_EN) {
148 switch (reg1 & MPC106_PICR1_L2_MP) {
164 switch (reg1 & MPC106_PICR1_L2_MP) {
182 pcireg_t reg1; local in function:ibm82660_print
188 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag
    [all...]
  /src/sys/arch/sgimips/ioc/
oioc.c 98 uint32_t reg1, reg2; local in function:oioc_attach
118 reg1 = 12 << OIOC2_CONFIG_HIWAT_SHFT;
119 reg1 |= OIOC2_CONFIG_BURST_MASK;
120 bus_space_write_4(sc->sc_iot, sc->sc_ioh, OIOC2_CONFIG, reg1);
123 if ((reg2 & (reg1 | OIOC2_CONFIG_NOSYNC_MASK)) == reg1)
  /src/sys/arch/hpcsh/dev/
psh3lcd.c 72 uint8_t reg1; member in struct:psh3lcd_x0_bcd
83 uint8_t reg1; member in struct:psh3lcd_xx0_bcd
144 bcr1 == psh3lcd_x0_bcd[i].reg1 &&
161 for (i = 0; psh3lcd_xx0_bcd[i].reg1 != 0; i++)
162 if (bcr1 == psh3lcd_xx0_bcd[i].reg1 &&
165 if (psh3lcd_xx0_bcd[i].reg1 == 0)
174 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_xx0_bcd[index].reg1);
183 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_x0_bcd[index].reg1);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
nouveau_dispnv04_hw.c 136 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
147 if (reg1 <= 0x405c) {
174 uint32_t reg1, pll1, pll2 = 0; local in function:nouveau_hw_get_pllvals
179 if (ret || !(reg1 = pll_lim.reg))
182 pll1 = nvif_rd32(device, reg1);
183 if (reg1 <= 0x405c)
184 pll2 = nvif_rd32(device, reg1 + 4);
186 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
191 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF)
    [all...]
  /src/sys/arch/hpcmips/dev/
plumicu.c 332 plumreg_t reg1, reg2, reg_ext, reg_pccard; local in function:plumicu_intr
337 reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG);
350 if (!(pic->ic_ackpat1 & reg1))
  /src/sys/arch/hpcmips/vr/
vrc4172gpio.c 161 u_int16_t reg0, reg1; local in function:read_4
164 reg1 = read_2(sc, off + VRC2_EXGP_OFFSET);
166 return (reg0|(reg1<<16));
  /src/sys/dev/ic/
aic6915.c 1232 uint32_t reg0, reg1, reg2; local in function:sf_set_filter_perfect
1235 reg1 = enaddr[3] | (enaddr[2] << 8);
1239 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 930 uint32_t reg1 = 0; local in function:dce110_stream_encoder_dp_blank
939 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
940 if ((reg1 & 0x1) == 0)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 885 uint32_t reg1 = 0; local in function:enc1_stream_encoder_dp_blank
895 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
896 if ((reg1 & 0x1) == 0)
  /src/sys/dev/isa/
wbsio.c 370 uint8_t reg0, reg1, rev; local in function:wbsio_search
385 reg1 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_HM_ADDR_MSB);
390 iobase = (reg1 << 8) | (reg0 & ~0x7);
537 uint8_t reg0, reg1; local in function:wbsio_gpio_rt_init
545 reg1 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_GPIO_ADDR_MSB);
546 iobase = (reg1 << 8) | (reg0 & ~0x7);
ess.c 615 u_char reg1; local in function:ess_identify
632 if ((reg1 = ess_rdsp(sc)) != 0x68) {
633 printf("ess: First ID byte wrong (0x%02x)\n", reg1);
647 sc->sc_version = (reg1 << 8) + reg2;
654 reg1 = ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL);
655 reg2 = reg1 ^ 0x04; /* toggle bit 2 */
674 ess_write_mix_reg(sc, ESS_MREG_VOLUME_CTRL, reg1);
683 reg1 = ess_read_mix_reg(sc, ESS_MREG_SAMPLE_RATE);
684 reg2 = reg1 ^ 0xff; /* toggle all bits */
717 reg1 = ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL)
    [all...]
  /src/sys/arch/hpcmips/tx/
txcom.c 539 txreg_t reg, reg1; local in function:txcom_setbaudrate
547 reg1 = tx_conf_read(chip->sc_tc, ofs);
548 reg1 &= ~TX39_UARTCTRL1_ENUART;
549 tx_conf_write(chip->sc_tc, ofs, reg1);
556 reg1 |= TX39_UARTCTRL1_ENUART;
557 tx_conf_write(chip->sc_tc, ofs, reg1);
  /src/sys/dev/pci/
if_msk.c 926 uint32_t imtimer_ticks, reg1; local in function:mskc_reset
979 reg1 = sk_win_read_4(sc, SK_GPIO);
980 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS;
981 sk_win_write_4(sc, SK_GPIO, reg1);
986 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
988 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
990 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
991 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
gffb.c 768 uint8_t reg0, reg1; local in function:gffb_setvideo
774 reg1 = gffb_read_crtc(sc, 1, 0x1a) & 0x3f;
778 reg1 |= 0xc0;
782 gffb_write_crtc(sc, 1, 0x1a, reg1);
  /src/lib/libnvmm/
libnvmm_x86.c 957 int reg1; member in struct:x86_dualreg
2082 int reg1, reg2; local in function:node_dual
2084 reg1 = gpr_dual_reg1_rm[instr->regmodrm.rm];
2097 instr->strm->u.dualreg.reg1 = reg1;
3064 gva = gpr_read_address(instr, state, store->u.dualreg.reg1) +
  /src/sys/dev/usb/
if_urtwn.c 4567 uint32_t reg0, reg1, reg2; local in function:urtwn_iq_calib
4582 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
4654 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1);

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