| /src/sys/arch/powerpc/pci/ |
| pchb.c | 80 pcireg_t reg1, reg2; local in function:mpc105_print
84 reg2 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR2);
87 switch (reg2 & MPC105_PICR2_L2_SIZE) {
123 pcireg_t reg1, reg2; local in function:mpc106_print
127 reg2 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR2);
130 switch (reg2 & MPC106_PICR2_L2_SIZE) {
184 pcireg_t reg2; local in function:ibm82660_print
191 reg2 = in32rb(PREP_BUS_SPACE_IO+IBM_82660_SYSTEM_CTRL);
192 if (reg2 & IBM_82660_SYSTEM_CTRL_L2_EN) {
197 if (reg2 & IBM_82660_SYSTEM_CTRL_L2_MI
[all...] |
| /src/sys/arch/sgimips/ioc/ |
| oioc.c | 98 uint32_t reg1, reg2; local in function:oioc_attach
122 reg2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, OIOC2_CONFIG);
123 if ((reg2 & (reg1 | OIOC2_CONFIG_NOSYNC_MASK)) == reg1)
135 (u_quad_t)reg2 & 0xffffffff);
|
| /src/sys/dev/acpi/ |
| ipmi_acpi.c | 88 bus_addr_t reg2; local in function:ipmi_acpi_attach
145 reg2 = 0;
149 reg2 = (bus_addr_t)io->ar_base;
153 reg2 = mem->ar_base;
156 if (reg2 > ia->iaa_if_iobase)
157 ia->iaa_if_iospacing = reg2 - ia->iaa_if_iobase;
|
| /src/sys/arch/hpcsh/dev/ |
| psh3lcd.c | 73 uint8_t reg2; member in struct:psh3lcd_x0_bcd
84 uint8_t reg2; member in struct:psh3lcd_xx0_bcd
145 bcr2 == psh3lcd_x0_bcd[i].reg2)
163 bcr2 == psh3lcd_xx0_bcd[i].reg2)
175 _reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_xx0_bcd[index].reg2);
184 _reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_x0_bcd[index].reg2);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_hw.c | 186 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); local in function:nouveau_hw_get_pllvals
188 pll2 = nvif_rd32(device, reg2);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 209 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); local in function:setPLL_double_highregs
211 uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0;
271 nvkm_wr32(device, reg2, pll2);
|
| /src/sys/arch/hpcmips/dev/ |
| plumicu.c | 332 plumreg_t reg1, reg2, reg_ext, reg_pccard; local in function:plumicu_intr
362 reg2 = pic->ic_ackreg2 == PLUM_INT_PCCINTS_REG
365 if (pic->ic_ackpat2 & reg2)
|
| it8368.c | 354 u_int16_t reg2; local in function:it8368_intr
355 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2);
357 dbg_bit_print(reg2);
|
| /src/sys/dev/pcmcia/ |
| pcmcia_cis.c | 1049 u_int reg, reg2; local in function:decode_cftable_entry
1170 reg2 = pcmcia_tuple_read_1(tuple, idx);
1178 } while (reg2 & 0x80);
|
| /src/sys/lib/libunwind/ |
| DwarfParser.hpp | 318 uint64_t reg2; local in function:_Unwind::CFI_Parser::parseInstructions
376 reg2 = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));
379 if (reg2 > kMaxRegisterNumber)
382 results->savedRegisters[reg].value = reg2;
|
| /src/sys/dev/ic/ |
| aic6915.c | 1232 uint32_t reg0, reg1, reg2; local in function:sf_set_filter_perfect
1236 reg2 = enaddr[1] | (enaddr[0] << 8);
1240 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2);
|
| tcic2.c | 836 int reg2; local in function:tcic_chip_do_mem_map
837 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin));
838 reg2 &= ~TCIC_MCTL_WSCNT_MASK;
839 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK;
840 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2);
|
| /src/sys/dev/isa/ |
| ess.c | 616 u_char reg2; local in function:ess_identify
637 reg2 = ess_rdsp(sc);
638 if (((reg2 & 0xf0) != 0x80) ||
639 ((reg2 & 0x0f) < 8)) {
647 sc->sc_version = (reg1 << 8) + reg2;
655 reg2 = reg1 ^ 0x04; /* toggle bit 2 */
657 ess_write_mix_reg(sc, ESS_MREG_VOLUME_CTRL, reg2);
659 if (ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL) != reg2) {
684 reg2 = reg1 ^ 0xff; /* toggle all bits */
686 ess_write_mix_reg(sc, ESS_MREG_SAMPLE_RATE, reg2);
[all...] |
| /src/sys/dev/sbus/ |
| dbri.c | 783 uint32_t reg2; local in function:mmcodec_init
786 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
787 DPRINTF("mmcodec_init: PIO reads %x\n", reg2);
789 if (reg2 & DBRI_PIO2) {
794 if (reg2 & DBRI_PIO0) {
800 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) {
806 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) {
|
| /src/sys/dev/ieee1394/ |
| fwohci.c | 1144 uint32_t reg, reg2; local in function:fwohci_probe_phy
1172 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
1175 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
1187 reg2 = fwphy_rddata(sc, 5);
1196 reg2 |= 0x03;
1204 reg2 &= ~0x83;
1207 reg2 = fwphy_wrdata(sc, 5, reg2);
1224 uint32_t reg, reg2; local in function:fwohci_reset
1260 reg2 = reg | OHCI_BUSFNC
[all...] |
| /src/lib/libnvmm/ |
| libnvmm_x86.c | 958 int reg2; member in struct:x86_dualreg
2082 int reg1, reg2; local in function:node_dual
2088 reg2 = NVMM_X64_GPR_RSI;
2091 reg2 = NVMM_X64_GPR_RDI;
2098 instr->strm->u.dualreg.reg2 = reg2;
3065 gpr_read_address(instr, state, store->u.dualreg.reg2);
|
| /src/sys/dev/pci/ |
| pci_subr.c | 1626 pcireg_t reg, reg2, val; local in function:pci_conf_print_secure_cap
1663 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)];
1664 printf(" Base Address High Register: 0x%08x\n", reg2);
1666 ((uint64_t)reg2 << 32)
2594 pcireg_t reg, reg2; local in function:pci_conf_print_ea_cap
2680 reg2 = regs[o2i(entoff + 12)];
2682 reg2);
2683 base |= (uint64_t)reg2 << 32;
2693 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))];
2695 reg2);
[all...] |
| if_wm.c | 16442 uint32_t reg2; local in function:wm_ulp_disable
16446 reg2 = CSR_READ(sc, WMREG_CTRL_EXT);
16447 reg2 |= CTRL_EXT_FORCE_SMBUS;
16448 CSR_WRITE(sc, WMREG_CTRL_EXT, reg2);
|
| /src/sys/dev/usb/ |
| if_urtwn.c | 4567 uint32_t reg0, reg1, reg2; local in function:urtwn_iq_calib
4583 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
4653 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2);
|
