| /src/sys/arch/x86/pci/ |
| fwhrng.c | 121 uint8_t reg8; local
138 reg8 = bus_space_read_1(sc->sc_st, sc->sc_sh, I82802_RNG_HSR);
140 reg8 | I82802_RNG_HSR_ENABLE);
141 reg8 = bus_space_read_1(sc->sc_st, sc->sc_sh, I82802_RNG_HSR);
142 if ((reg8 & I82802_RNG_HSR_ENABLE) == 0) {
152 reg8 = bus_space_read_1(sc->sc_st, sc->sc_sh,
154 if (!(reg8 & I82802_RNG_DSR_VALID)) {
158 reg8 = bus_space_read_1(sc->sc_st, sc->sc_sh,
168 if (reg8 == 0xff)
174 reg8 = bus_space_read_1(sc->sc_st, sc->sc_sh, I82802_RNG_HSR)
208 uint8_t reg8; local
[all...] |
| /src/sys/dev/fdt/ |
| pinctrl_single.c | 75 uint8_t reg8; member in union:__anon2557
82 u.reg8 = bus_space_read_1(sc->sc_bst, sc->sc_bsh, off);
83 u.reg8 &= ~sc->sc_funcmask;
84 u.reg8 |= val;
85 bus_space_write_1(sc->sc_bst, sc->sc_bsh, off, u.reg8);
|
| /src/external/gpl3/gcc.old/dist/gcc/config/avr/ |
| avr.cc | 6312 rtx reg8 = simplify_gen_subreg (QImode, xreg, mode, i);
6319 bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
6321 xop[0] = reg8;
6327 && test_hard_reg_class (ADDW_REGS, reg8))
8215 rtx reg8 = simplify_gen_subreg (QImode, xop[0], mode, i);
8222 bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
8224 op[0] = reg8;
8235 && test_hard_reg_class (ADDW_REGS, reg8))
8853 rtx reg8 = simplify_gen_subreg (QImode, xop[0], mode, i);
8863 bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
6311 rtx reg8 = simplify_gen_subreg (QImode, xreg, mode, i); local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/avr/ |
| avr.cc | 7124 rtx reg8 = simplify_gen_subreg (QImode, xreg, mode, i);
7131 bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
7133 xop[0] = reg8;
7139 && avr_adiw_reg_p (reg8))
9014 rtx reg8 = simplify_gen_subreg (QImode, xop[0], mode, i);
9021 bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
9023 op[0] = reg8;
9031 && avr_adiw_reg_p (reg8))
9660 rtx reg8 = simplify_gen_subreg (QImode, xop[0], mode, i);
9670 bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
7123 rtx reg8 = simplify_gen_subreg (QImode, xreg, mode, i); local
[all...] |
