| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| atom.h | 141 uint16_t reg_block; member in struct:atom_context
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| amdgpu_atombios.c | 1598 ATOM_INIT_REG_BLOCK *reg_block = local in function:amdgpu_atombios_init_mc_reg_table
1603 ((u8 *)reg_block + (2 * sizeof(u16)) +
1604 le16_to_cpu(reg_block->usRegIndexTblSize));
1605 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
1606 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1643 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
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| amdgpu_dce_v6_0.c | 2821 u32 reg_block, interrupt_mask; local in function:dce_v6_0_set_crtc_vblank_interrupt_state
2830 reg_block = SI_CRTC0_REGISTER_OFFSET;
2833 reg_block = SI_CRTC1_REGISTER_OFFSET;
2836 reg_block = SI_CRTC2_REGISTER_OFFSET;
2839 reg_block = SI_CRTC3_REGISTER_OFFSET;
2842 reg_block = SI_CRTC4_REGISTER_OFFSET;
2845 reg_block = SI_CRTC5_REGISTER_OFFSET;
2854 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2856 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2859 interrupt_mask = RREG32(mmINT_MASK + reg_block);
[all...] |
| amdgpu_dce_v8_0.c | 2867 u32 reg_block, lb_interrupt_mask; local in function:dce_v8_0_set_crtc_vblank_interrupt_state
2876 reg_block = CRTC0_REGISTER_OFFSET;
2879 reg_block = CRTC1_REGISTER_OFFSET;
2882 reg_block = CRTC2_REGISTER_OFFSET;
2885 reg_block = CRTC3_REGISTER_OFFSET;
2888 reg_block = CRTC4_REGISTER_OFFSET;
2891 reg_block = CRTC5_REGISTER_OFFSET;
2900 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2902 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2905 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2918 u32 reg_block, lb_interrupt_mask; local in function:dce_v8_0_set_crtc_vline_interrupt_state
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| atom.h | 139 uint16_t reg_block; member in struct:atom_context
|
| radeon_atombios.c | 4004 ATOM_INIT_REG_BLOCK *reg_block = local in function:radeon_atom_init_mc_reg_table
4009 ((u8 *)reg_block + (2 * sizeof(u16)) +
4010 le16_to_cpu(reg_block->usRegIndexTblSize));
4011 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4012 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4049 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_ppatomctrl.c | 54 ATOM_INIT_REG_BLOCK *reg_block,
60 ((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize));
89 ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ;
102 * @param reg_block the address ATOM_INIT_REG_BLOCK
107 ATOM_INIT_REG_BLOCK *reg_block,
111 uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize))
113 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
143 ATOM_INIT_REG_BLOCK *reg_block; local in function:atomctrl_initialize_mc_reg_table
161 reg_block = (ATOM_INIT_REG_BLOCK *
[all...] |
| /src/sys/dev/pci/ |
| if_ixl.c | 5443 uint32_t reg_block = 0; local in function:ixl_clear_hw
5446 reg_block = abs_queue_idx / 128;
5450 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block));
5455 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
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