| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| clearstate_defs.h | 37 const unsigned int reg_index; member in struct:cs_extent_def
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| clearstate_defs.h | 37 const unsigned int reg_index; member in struct:cs_extent_def
|
| radeon_sumo_dpm.c | 481 u32 reg_index = index / 4; local in function:sumo_set_divider_value
485 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
488 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
491 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
494 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
587 u32 reg_index = index / 4; local in function:sumo_power_level_enable
591 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
594 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
597 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
600 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4)
[all...] |
| /src/usr.sbin/gspa/gspa/ |
| gsp_act.c | 146 reg_index(int reg, expr disp) function in typeref:typename:operand
|
| /src/usr.bin/scmdctl/ |
| common.c | 193 int reg_index; local in function:common_set_motor
203 reg_index = a_module * 2;
205 reg_index++;
206 reg = SCMD_REG_MA_DRIVE + reg_index;
209 fprintf(stderr,"common_set_motor: reg_index: %d ; reg: %02X ; reg_v: %d\n",reg_index,reg,reg_v);
221 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_invert_motor
243 reg_index = 1 << motor_index;
246 fprintf(stderr,"common_invert_motor: remote invert: motor_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",motor_index,reg_offset,reg_index,reg)
263 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_bridge_motor
[all...] |
