| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/ |
| ir3_shader.c | 73 * regid's might not even be valid)
81 if (v->inputs[i].regid >= regid(48,0))
86 int32_t regid = v->inputs[i].regid + n; local
89 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
91 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
94 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
100 int32_t regid = v->outputs[i].regid + 3 local
312 uint32_t regid; local
323 uint8_t regid; local
368 uint8_t regid = so->outputs[i].regid; local
376 uint8_t regid = so->inputs[i].regid; local
388 uint8_t regid = so->outputs[i].regid; local
396 uint8_t regid = so->inputs[i].regid; local
[all...] |
| ir3.h | 582 static inline uint32_t regid(int num, int comp) function
637 if (dst->num == regid(REG_P0, 0))
639 if (dst->num == regid(REG_A0, 0))
|
| ir3_shader.h | 377 * + From the vert shader, we only need the output regid
392 uint8_t regid; member in struct:ir3_shader_variant::__anon3502
403 uint8_t regid; member in struct:ir3_shader_variant::__anon3503
603 uint8_t regid; member in struct:ir3_shader_linkage::__anon3507
610 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
616 l->var[i].regid = regid;
640 ir3_link_add(l, vs->outputs[k].regid,
651 return so->outputs[j].regid;
652 return regid(63, 0)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/ |
| ir3_shader.c | 69 * regid's might not even be valid)
77 if (v->inputs[i].regid >= regid(48, 0))
82 int32_t regid = v->inputs[i].regid + n; local
85 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
87 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
90 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
97 if (!VALIDREG(v->outputs[i].regid))
99 int32_t regid = v->outputs[i].regid + 3 local
113 int32_t regid = v->sampler_prefetch[i].dst + n; local
621 uint32_t regid; local
663 uint8_t regid; local
707 uint8_t regid = so->outputs[i].regid; local
716 uint8_t regid = so->inputs[i].regid; local
[all...] |
| ir3_shader.h | 454 /* Represents half register in regid */
549 * + From the vert shader, we only need the output regid
565 uint8_t regid; member in struct:ir3_shader_variant::__anon979
589 uint8_t regid; member in struct:ir3_shader_variant::__anon980
879 uint8_t regid; member in struct:ir3_shader_linkage::__anon982
905 if (regid_ != regid(63, 0)) {
909 l->var[i].regid = regid_;
928 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0);
962 ir3_link_add(l, k >= 0 ? vs->outputs[k].regid : default_regid
[all...] |
| instr-a3xx.h | 417 regid(int num, int comp) function
422 #define INVALID_REG regid(63, 0)
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_const.c | 32 /* regid: base const register
38 const struct ir3_shader_variant *v, uint32_t regid,
41 emit_const_asserts(ring, v, regid, sizedwords);
52 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS,
60 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS,
69 const struct ir3_shader_variant *v, uint32_t regid,
72 uint32_t dst_off = regid / 4;
77 emit_const_asserts(ring, v, regid, sizedwords);
116 const unsigned regid = const_state->offsets.primitive_param * 4 + 4; variable
120 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4)
133 const unsigned regid = const_state->offsets.primitive_param; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/freedreno/decode/ |
| pgmdump2.c | 277 uint32_t regid; member in struct:shader_constant_block
287 R(c, regid, 'c');
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_clear_blit.c | 692 unsigned regid = 0; local
694 regid = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + rt++);
695 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(regid));
|
