| /src/sys/dev/ic/ |
| dwc_gmac.c | 285 * Allocate Tx and Rx rings
288 aprint_error_dev(sc->sc_dev, "could not allocate DMA rings\n");
599 void *rings; local in function:dwc_gmac_alloc_dma_rings
619 ringsize, &rings, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
626 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dma_ring_map, rings,
635 sc->sc_rxq.r_desc = rings;
638 /* and next rings to the TX side */
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| cmd_parser.c | 424 /* rings that support this cmd: BLT/RCS/VCS/VECS */
425 u16 rings; member in struct:cmd_info
660 if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))
3038 unsigned int opcode, unsigned long rings)
3043 for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
3070 e->info->opcode, e->info->rings);
3082 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3084 e->info->devices, e->info->rings);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu.h | 428 * CP & rings.
530 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
872 /* rings */
875 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; member in struct:amdgpu_device
969 /* keep an lru list of rings by HW IP */
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