1 /* $NetBSD: rk_cru.c,v 1.10 2022/09/18 21:33:57 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_console.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_cru.c,v 1.10 2022/09/18 21:33:57 ryo Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #include <dev/clk/clk_backend.h> 43 44 #include <arm/rockchip/rk_cru.h> 45 46 static void * 47 rk_cru_reset_acquire(device_t dev, const void *data, size_t len) 48 { 49 if (len != 4) 50 return NULL; 51 52 return (void *)(uintptr_t)be32dec(data); 53 } 54 55 static void 56 rk_cru_reset_release(device_t dev, void *priv) 57 { 58 } 59 60 static int 61 rk_cru_reset_assert(device_t dev, void *priv) 62 { 63 struct rk_cru_softc * const sc = device_private(dev); 64 const uintptr_t reset_id = (uintptr_t)priv; 65 const bus_size_t reg = sc->sc_softrst_base + (reset_id / 16) * 4; 66 const u_int shift = reset_id % 16; 67 68 CRU_WRITE(sc, reg, (1 << (shift + 16)) | (1 << shift)); 69 70 return 0; 71 } 72 73 static int 74 rk_cru_reset_deassert(device_t dev, void *priv) 75 { 76 struct rk_cru_softc * const sc = device_private(dev); 77 const uintptr_t reset_id = (uintptr_t)priv; 78 const bus_size_t reg = sc->sc_softrst_base + (reset_id / 16) * 4; 79 const u_int shift = reset_id % 16; 80 81 CRU_WRITE(sc, reg, (1 << (shift + 16)) | (0 << shift)); 82 83 return 0; 84 } 85 86 static const struct fdtbus_reset_controller_func rk_cru_fdtreset_funcs = { 87 .acquire = rk_cru_reset_acquire, 88 .release = rk_cru_reset_release, 89 .reset_assert = rk_cru_reset_assert, 90 .reset_deassert = rk_cru_reset_deassert, 91 }; 92 93 static struct clk * 94 rk_cru_clock_decode(device_t dev, int cc_phandle, const void *data, size_t len) 95 { 96 struct rk_cru_softc * const sc = device_private(dev); 97 struct rk_cru_clk *clk; 98 99 if (len != 4) 100 return NULL; 101 102 const u_int clock_id = be32dec(data); 103 104 for (int i = 0; i < sc->sc_nclks; i++) { 105 clk = &sc->sc_clks[i]; 106 if (clk->id == clock_id) 107 return &clk->base; 108 } 109 110 return NULL; 111 } 112 113 static const struct fdtbus_clock_controller_func rk_cru_fdtclock_funcs = { 114 .decode = rk_cru_clock_decode, 115 }; 116 117 static struct clk * 118 rk_cru_clock_get(void *priv, const char *name) 119 { 120 struct rk_cru_softc * const sc = priv; 121 struct rk_cru_clk *clk; 122 123 clk = rk_cru_clock_find(sc, name); 124 if (clk == NULL) 125 return NULL; 126 127 return &clk->base; 128 } 129 130 static void 131 rk_cru_clock_put(void *priv, struct clk *clk) 132 { 133 } 134 135 static u_int 136 rk_cru_clock_get_rate(void *priv, struct clk *clkp) 137 { 138 struct rk_cru_softc * const sc = priv; 139 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 140 struct clk *clkp_parent; 141 142 if (clk->get_rate) 143 return clk->get_rate(sc, clk); 144 145 clkp_parent = clk_get_parent(clkp); 146 if (clkp_parent == NULL) { 147 aprint_debug("%s: no parent for %s\n", __func__, 148 clk->base.name); 149 return 0; 150 } 151 152 return clk_get_rate(clkp_parent); 153 } 154 155 static int 156 rk_cru_clock_set_rate(void *priv, struct clk *clkp, u_int rate) 157 { 158 struct rk_cru_softc * const sc = priv; 159 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 160 struct clk *clkp_parent; 161 162 if (clkp->flags & CLK_SET_RATE_PARENT) { 163 clkp_parent = clk_get_parent(clkp); 164 if (clkp_parent == NULL) { 165 aprint_error("%s: no parent for %s\n", __func__, 166 clk->base.name); 167 return ENXIO; 168 } 169 return clk_set_rate(clkp_parent, rate); 170 } 171 172 if (clk->set_rate) 173 return clk->set_rate(sc, clk, rate); 174 175 return ENXIO; 176 } 177 178 static u_int 179 rk_cru_clock_round_rate(void *priv, struct clk *clkp, u_int rate) 180 { 181 struct rk_cru_softc * const sc = priv; 182 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 183 struct clk *clkp_parent; 184 185 if (clkp->flags & CLK_SET_RATE_PARENT) { 186 clkp_parent = clk_get_parent(clkp); 187 if (clkp_parent == NULL) { 188 aprint_error("%s: no parent for %s\n", __func__, 189 clk->base.name); 190 return 0; 191 } 192 return clk_round_rate(clkp_parent, rate); 193 } 194 195 if (clk->round_rate) 196 return clk->round_rate(sc, clk, rate); 197 198 return 0; 199 } 200 201 static int 202 rk_cru_clock_enable(void *priv, struct clk *clkp) 203 { 204 struct rk_cru_softc * const sc = priv; 205 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 206 struct clk *clkp_parent; 207 int error = 0; 208 209 clkp_parent = clk_get_parent(clkp); 210 if (clkp_parent != NULL) { 211 error = clk_enable(clkp_parent); 212 if (error != 0) 213 return error; 214 } 215 216 if (clk->enable) 217 error = clk->enable(sc, clk, 1); 218 219 return error; 220 } 221 222 static int 223 rk_cru_clock_disable(void *priv, struct clk *clkp) 224 { 225 struct rk_cru_softc * const sc = priv; 226 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 227 int error = EINVAL; 228 229 if (clk->enable) 230 error = clk->enable(sc, clk, 0); 231 232 return error; 233 } 234 235 static int 236 rk_cru_clock_set_parent(void *priv, struct clk *clkp, struct clk *clkp_parent) 237 { 238 struct rk_cru_softc * const sc = priv; 239 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 240 241 if (clk->set_parent == NULL) 242 return EINVAL; 243 244 return clk->set_parent(sc, clk, clkp_parent->name); 245 } 246 247 static struct clk * 248 rk_cru_clock_get_parent(void *priv, struct clk *clkp) 249 { 250 struct rk_cru_softc * const sc = priv; 251 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 252 struct rk_cru_clk *clk_parent; 253 const char *parent; 254 255 if (clk->get_parent == NULL) 256 return NULL; 257 258 parent = clk->get_parent(sc, clk); 259 if (parent == NULL) 260 return NULL; 261 262 clk_parent = rk_cru_clock_find(sc, parent); 263 if (clk_parent != NULL) 264 return &clk_parent->base; 265 266 /* No parent in this domain, try FDT */ 267 return fdtbus_clock_byname(parent); 268 } 269 270 static const struct clk_funcs rk_cru_clock_funcs = { 271 .get = rk_cru_clock_get, 272 .put = rk_cru_clock_put, 273 .get_rate = rk_cru_clock_get_rate, 274 .set_rate = rk_cru_clock_set_rate, 275 .round_rate = rk_cru_clock_round_rate, 276 .enable = rk_cru_clock_enable, 277 .disable = rk_cru_clock_disable, 278 .set_parent = rk_cru_clock_set_parent, 279 .get_parent = rk_cru_clock_get_parent, 280 }; 281 282 struct rk_cru_clk * 283 rk_cru_clock_find(struct rk_cru_softc *sc, const char *name) 284 { 285 for (int i = 0; i < sc->sc_nclks; i++) { 286 if (sc->sc_clks[i].base.name == NULL) 287 continue; 288 if (strcmp(sc->sc_clks[i].base.name, name) == 0) 289 return &sc->sc_clks[i]; 290 } 291 292 return NULL; 293 } 294 295 int 296 rk_cru_attach(struct rk_cru_softc *sc) 297 { 298 bus_addr_t addr; 299 bus_size_t size; 300 int i; 301 302 if (of_hasprop(sc->sc_phandle, "rockchip,grf")) { 303 sc->sc_grf = fdtbus_syscon_acquire(sc->sc_phandle, 304 "rockchip,grf"); 305 if (sc->sc_grf == NULL) { 306 aprint_error(": couldn't get grf syscon\n"); 307 return ENXIO; 308 } 309 } 310 311 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr, &size) != 0) { 312 aprint_error(": couldn't get registers\n"); 313 return ENXIO; 314 } 315 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 316 aprint_error(": couldn't map registers\n"); 317 return ENXIO; 318 } 319 320 sc->sc_clkdom.name = device_xname(sc->sc_dev); 321 sc->sc_clkdom.funcs = &rk_cru_clock_funcs; 322 sc->sc_clkdom.priv = sc; 323 for (i = 0; i < sc->sc_nclks; i++) { 324 sc->sc_clks[i].base.domain = &sc->sc_clkdom; 325 clk_attach(&sc->sc_clks[i].base); 326 } 327 328 fdtbus_register_clock_controller(sc->sc_dev, sc->sc_phandle, 329 &rk_cru_fdtclock_funcs); 330 331 fdtbus_register_reset_controller(sc->sc_dev, sc->sc_phandle, 332 &rk_cru_fdtreset_funcs); 333 334 return 0; 335 } 336 337 void 338 rk_cru_print(struct rk_cru_softc *sc) 339 { 340 struct rk_cru_clk *clk; 341 struct clk *clkp_parent; 342 const char *type; 343 int i; 344 345 for (i = 0; i < sc->sc_nclks; i++) { 346 clk = &sc->sc_clks[i]; 347 if (clk->type == RK_CRU_UNKNOWN) 348 continue; 349 350 clkp_parent = clk_get_parent(&clk->base); 351 352 switch (clk->type) { 353 case RK_CRU_PLL: type = "pll"; break; 354 case RK_CRU_ARM: type = "arm"; break; 355 case RK_CRU_COMPOSITE: type = "comp"; break; 356 case RK_CRU_GATE: type = "gate"; break; 357 case RK_CRU_MUX: type = "mux"; break; 358 default: type = "???"; break; 359 } 360 361 aprint_debug_dev(sc->sc_dev, 362 "%3d %-14s %2s %-14s %-7s ", 363 clk->id, 364 clk->base.name, 365 clkp_parent ? "<-" : "", 366 clkp_parent ? clkp_parent->name : "", 367 type); 368 aprint_debug("%10d Hz\n", clk_get_rate(&clk->base)); 369 } 370 } 371
Indexes created Sat Sep 20 22:09:52 GMT 2025