1 /* $NetBSD: amdgpu_rn_clk_mgr.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_rn_clk_mgr.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $"); 30 31 #include "dccg.h" 32 #include "clk_mgr_internal.h" 33 34 35 #include "dcn20/dcn20_clk_mgr.h" 36 #include "rn_clk_mgr.h" 37 38 39 #include "dce100/dce_clk_mgr.h" 40 #include "rn_clk_mgr_vbios_smu.h" 41 #include "reg_helper.h" 42 #include "core_types.h" 43 #include "dm_helpers.h" 44 45 #include "atomfirmware.h" 46 #include "clk/clk_10_0_2_offset.h" 47 #include "clk/clk_10_0_2_sh_mask.h" 48 #include "renoir_ip_offset.h" 49 50 51 /* Constants */ 52 53 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */ 54 55 /* Macros */ 56 57 #define REG(reg_name) \ 58 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 59 60 61 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */ 62 int rn_get_active_display_cnt_wa( 63 struct dc *dc, 64 struct dc_state *context) 65 { 66 int i, display_count; 67 bool tmds_present = false; 68 69 display_count = 0; 70 for (i = 0; i < context->stream_count; i++) { 71 const struct dc_stream_state *stream = context->streams[i]; 72 73 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 74 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 75 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 76 tmds_present = true; 77 } 78 79 for (i = 0; i < dc->link_count; i++) { 80 const struct dc_link *link = dc->links[i]; 81 82 /* 83 * Only notify active stream or virtual stream. 84 * Need to notify virtual stream to work around 85 * headless case. HPD does not fire when system is in 86 * S0i2. 87 */ 88 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 89 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL || 90 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 91 display_count++; 92 } 93 94 /* WA for hang on HDMI after display off back back on*/ 95 if (display_count == 0 && tmds_present) 96 display_count = 1; 97 98 return display_count; 99 } 100 101 void rn_update_clocks(struct clk_mgr *clk_mgr_base, 102 struct dc_state *context, 103 bool safe_to_lower) 104 { 105 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 106 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 107 struct dc *dc = clk_mgr_base->ctx->dc; 108 int display_count; 109 bool update_dppclk = false; 110 bool update_dispclk = false; 111 bool dpp_clock_lowered = false; 112 113 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 114 115 if (dc->work_arounds.skip_clock_update) 116 return; 117 118 /* 119 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 120 * also if safe to lower is false, we just go in the higher state 121 */ 122 if (safe_to_lower) { 123 /* check that we're not already in lower */ 124 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 125 126 display_count = rn_get_active_display_cnt_wa(dc, context); 127 /* if we can go lower, go lower */ 128 if (display_count == 0) { 129 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); 130 /* update power state */ 131 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 132 } 133 } 134 } else { 135 /* check that we're not already in D0 */ 136 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 137 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE); 138 /* update power state */ 139 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 140 } 141 } 142 143 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 144 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 145 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); 146 } 147 148 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 149 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 151 } 152 153 if (should_set_clock(safe_to_lower, 154 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 155 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 156 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 157 } 158 159 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 160 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 161 if (new_clocks->dppclk_khz < 100000) 162 new_clocks->dppclk_khz = 100000; 163 } 164 165 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 166 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 167 dpp_clock_lowered = true; 168 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 169 update_dppclk = true; 170 } 171 172 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 173 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 174 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 175 176 update_dispclk = true; 177 } 178 179 if (dpp_clock_lowered) { 180 // increase per DPP DTO before lowering global dppclk 181 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 182 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 183 } else { 184 // increase global DPPCLK before lowering per DPP DTO 185 if (update_dppclk || update_dispclk) 186 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 187 // always update dtos unless clock is lowered and not safe to lower 188 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 189 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 190 } 191 192 if (update_dispclk && 193 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 194 /*update dmcu for wait_loop count*/ 195 dmcu->funcs->set_psr_wait_loop(dmcu, 196 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 197 } 198 } 199 200 201 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 202 { 203 /* get FbMult value */ 204 struct fixed31_32 pll_req; 205 unsigned int fbmult_frac_val = 0; 206 unsigned int fbmult_int_val = 0; 207 208 209 /* 210 * Register value of fbmult is in 8.16 format, we are converting to 31.32 211 * to leverage the fix point operations available in driver 212 */ 213 214 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 215 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 216 217 pll_req = dc_fixpt_from_int(fbmult_int_val); 218 219 /* 220 * since fractional part is only 16 bit in register definition but is 32 bit 221 * in our fix point definiton, need to shift left by 16 to obtain correct value 222 */ 223 pll_req.value |= fbmult_frac_val << 16; 224 225 /* multiply by REFCLK period */ 226 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 227 228 /* integer part is now VCO frequency in kHz */ 229 return dc_fixpt_floor(pll_req); 230 } 231 232 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) 233 { 234 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 235 236 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); 237 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); 238 239 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider 240 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); 241 242 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); 243 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); 244 245 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); 246 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); 247 248 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); 249 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); 250 } 251 252 /* This function collect raw clk register values */ 253 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 254 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 255 { 256 struct rn_clk_internal internal = {0}; 257 const char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; 258 unsigned int chars_printed = 0; 259 unsigned int remaining_buffer = log_info->bufSize; 260 261 rn_dump_clk_registers_internal(&internal, clk_mgr_base); 262 263 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 264 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; 265 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; 266 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; 267 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; 268 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 269 270 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 271 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 272 regs_and_bypass->dppclk_bypass = 0; 273 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 274 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 275 regs_and_bypass->dcfclk_bypass = 0; 276 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 277 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 278 regs_and_bypass->dispclk_bypass = 0; 279 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 280 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 281 regs_and_bypass->dprefclk_bypass = 0; 282 283 if (log_info->enabled) { 284 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); 285 remaining_buffer -= chars_printed; 286 *log_info->sum_chars_printed += chars_printed; 287 log_info->pBuf += chars_printed; 288 289 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 290 regs_and_bypass->dcfclk, 291 regs_and_bypass->dcf_deep_sleep_divider, 292 regs_and_bypass->dcf_deep_sleep_allow, 293 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); 294 remaining_buffer -= chars_printed; 295 *log_info->sum_chars_printed += chars_printed; 296 log_info->pBuf += chars_printed; 297 298 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n", 299 regs_and_bypass->dprefclk, 300 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); 301 remaining_buffer -= chars_printed; 302 *log_info->sum_chars_printed += chars_printed; 303 log_info->pBuf += chars_printed; 304 305 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n", 306 regs_and_bypass->dispclk, 307 bypass_clks[(int) regs_and_bypass->dispclk_bypass]); 308 remaining_buffer -= chars_printed; 309 *log_info->sum_chars_printed += chars_printed; 310 log_info->pBuf += chars_printed; 311 312 //split 313 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n"); 314 remaining_buffer -= chars_printed; 315 *log_info->sum_chars_printed += chars_printed; 316 log_info->pBuf += chars_printed; 317 318 // REGISTER VALUES 319 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n"); 320 remaining_buffer -= chars_printed; 321 *log_info->sum_chars_printed += chars_printed; 322 log_info->pBuf += chars_printed; 323 324 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", 325 internal.CLK1_CLK3_CURRENT_CNT); 326 remaining_buffer -= chars_printed; 327 *log_info->sum_chars_printed += chars_printed; 328 log_info->pBuf += chars_printed; 329 330 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", 331 internal.CLK1_CLK3_DS_CNTL); 332 remaining_buffer -= chars_printed; 333 *log_info->sum_chars_printed += chars_printed; 334 log_info->pBuf += chars_printed; 335 336 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", 337 internal.CLK1_CLK3_ALLOW_DS); 338 remaining_buffer -= chars_printed; 339 *log_info->sum_chars_printed += chars_printed; 340 log_info->pBuf += chars_printed; 341 342 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", 343 internal.CLK1_CLK2_CURRENT_CNT); 344 remaining_buffer -= chars_printed; 345 *log_info->sum_chars_printed += chars_printed; 346 log_info->pBuf += chars_printed; 347 348 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", 349 internal.CLK1_CLK0_CURRENT_CNT); 350 remaining_buffer -= chars_printed; 351 *log_info->sum_chars_printed += chars_printed; 352 log_info->pBuf += chars_printed; 353 354 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", 355 internal.CLK1_CLK1_CURRENT_CNT); 356 remaining_buffer -= chars_printed; 357 *log_info->sum_chars_printed += chars_printed; 358 log_info->pBuf += chars_printed; 359 360 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", 361 internal.CLK1_CLK3_BYPASS_CNTL); 362 remaining_buffer -= chars_printed; 363 *log_info->sum_chars_printed += chars_printed; 364 log_info->pBuf += chars_printed; 365 366 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", 367 internal.CLK1_CLK2_BYPASS_CNTL); 368 remaining_buffer -= chars_printed; 369 *log_info->sum_chars_printed += chars_printed; 370 log_info->pBuf += chars_printed; 371 372 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", 373 internal.CLK1_CLK0_BYPASS_CNTL); 374 remaining_buffer -= chars_printed; 375 *log_info->sum_chars_printed += chars_printed; 376 log_info->pBuf += chars_printed; 377 378 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", 379 internal.CLK1_CLK1_BYPASS_CNTL); 380 remaining_buffer -= chars_printed; 381 *log_info->sum_chars_printed += chars_printed; 382 log_info->pBuf += chars_printed; 383 } 384 } 385 386 /* This function produce translated logical clk state values*/ 387 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) 388 { 389 struct clk_state_registers_and_bypass sb = { 0 }; 390 struct clk_log_info log_info = { 0 }; 391 392 rn_dump_clk_registers(&sb, clk_mgr_base, &log_info); 393 394 s->dprefclk_khz = sb.dprefclk * 1000; 395 } 396 397 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) 398 { 399 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 400 401 rn_vbios_smu_enable_pme_wa(clk_mgr); 402 } 403 404 void rn_init_clocks(struct clk_mgr *clk_mgr) 405 { 406 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 407 // Assumption is that boot state always supports pstate 408 clk_mgr->clks.p_state_change_support = true; 409 clk_mgr->clks.prev_p_state_change_support = true; 410 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 411 } 412 413 void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) 414 { 415 int i, num_valid_sets; 416 417 num_valid_sets = 0; 418 419 for (i = 0; i < WM_SET_COUNT; i++) { 420 /* skip empty entries, the smu array has no holes*/ 421 if (!bw_params->wm_table.entries[i].valid) 422 continue; 423 424 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; 425 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; 426 /* We will not select WM based on fclk, so leave it as unconstrained */ 427 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 428 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 429 /* dcfclk wil be used to select WM*/ 430 431 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { 432 if (i == 0) 433 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; 434 else { 435 /* add 1 to make it non-overlapping with next lvl */ 436 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 437 } 438 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 439 440 } else { 441 /* unconstrained for memory retraining */ 442 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 443 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 444 445 /* Modify previous watermark range to cover up to max */ 446 ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 447 } 448 num_valid_sets++; 449 } 450 451 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 452 ranges->num_reader_wm_sets = num_valid_sets; 453 454 /* modify the min and max to make sure we cover the whole range*/ 455 ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 456 ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 457 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 458 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 459 460 /* This is for writeback only, does not matter currently as no writeback support*/ 461 ranges->num_writer_wm_sets = 1; 462 ranges->writer_wm_sets[0].wm_inst = WM_A; 463 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 464 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 465 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 466 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 467 468 } 469 470 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 471 { 472 struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug; 473 struct pp_smu_wm_range_sets ranges = {0}; 474 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 475 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; 476 477 if (!debug->disable_pplib_wm_range) { 478 build_watermark_ranges(clk_mgr_base->bw_params, &ranges); 479 480 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 481 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) 482 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); 483 } 484 485 } 486 487 static bool rn_are_clock_states_equal(struct dc_clocks *a, 488 struct dc_clocks *b) 489 { 490 if (a->dispclk_khz != b->dispclk_khz) 491 return false; 492 else if (a->dppclk_khz != b->dppclk_khz) 493 return false; 494 else if (a->dcfclk_khz != b->dcfclk_khz) 495 return false; 496 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 497 return false; 498 499 return true; 500 } 501 502 503 static struct clk_mgr_funcs dcn21_funcs = { 504 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 505 .update_clocks = rn_update_clocks, 506 .init_clocks = rn_init_clocks, 507 .enable_pme_wa = rn_enable_pme_wa, 508 .are_clock_states_equal = rn_are_clock_states_equal, 509 .notify_wm_ranges = rn_notify_wm_ranges 510 }; 511 512 struct clk_bw_params rn_bw_params = { 513 .vram_type = Ddr4MemType, 514 .num_channels = 1, 515 .clk_table = { 516 .entries = { 517 { 518 .voltage = 0, 519 .dcfclk_mhz = 400, 520 .fclk_mhz = 400, 521 .memclk_mhz = 800, 522 .socclk_mhz = 0, 523 }, 524 { 525 .voltage = 0, 526 .dcfclk_mhz = 483, 527 .fclk_mhz = 800, 528 .memclk_mhz = 1600, 529 .socclk_mhz = 0, 530 }, 531 { 532 .voltage = 0, 533 .dcfclk_mhz = 602, 534 .fclk_mhz = 1067, 535 .memclk_mhz = 1067, 536 .socclk_mhz = 0, 537 }, 538 { 539 .voltage = 0, 540 .dcfclk_mhz = 738, 541 .fclk_mhz = 1333, 542 .memclk_mhz = 1600, 543 .socclk_mhz = 0, 544 }, 545 }, 546 547 .num_entries = 4, 548 }, 549 550 }; 551 552 struct wm_table ddr4_wm_table = { 553 .entries = { 554 { 555 .wm_inst = WM_A, 556 .wm_type = WM_TYPE_PSTATE_CHG, 557 .pstate_latency_us = 11.72, 558 .sr_exit_time_us = 6.09, 559 .sr_enter_plus_exit_time_us = 7.14, 560 .valid = true, 561 }, 562 { 563 .wm_inst = WM_B, 564 .wm_type = WM_TYPE_PSTATE_CHG, 565 .pstate_latency_us = 11.72, 566 .sr_exit_time_us = 10.12, 567 .sr_enter_plus_exit_time_us = 11.48, 568 .valid = true, 569 }, 570 { 571 .wm_inst = WM_C, 572 .wm_type = WM_TYPE_PSTATE_CHG, 573 .pstate_latency_us = 11.72, 574 .sr_exit_time_us = 10.12, 575 .sr_enter_plus_exit_time_us = 11.48, 576 .valid = true, 577 }, 578 { 579 .wm_inst = WM_D, 580 .wm_type = WM_TYPE_PSTATE_CHG, 581 .pstate_latency_us = 11.72, 582 .sr_exit_time_us = 10.12, 583 .sr_enter_plus_exit_time_us = 11.48, 584 .valid = true, 585 }, 586 } 587 }; 588 589 struct wm_table lpddr4_wm_table = { 590 .entries = { 591 { 592 .wm_inst = WM_A, 593 .wm_type = WM_TYPE_PSTATE_CHG, 594 .pstate_latency_us = 11.65333, 595 .sr_exit_time_us = 5.32, 596 .sr_enter_plus_exit_time_us = 6.38, 597 .valid = true, 598 }, 599 { 600 .wm_inst = WM_B, 601 .wm_type = WM_TYPE_PSTATE_CHG, 602 .pstate_latency_us = 11.65333, 603 .sr_exit_time_us = 9.82, 604 .sr_enter_plus_exit_time_us = 11.196, 605 .valid = true, 606 }, 607 { 608 .wm_inst = WM_C, 609 .wm_type = WM_TYPE_PSTATE_CHG, 610 .pstate_latency_us = 11.65333, 611 .sr_exit_time_us = 9.89, 612 .sr_enter_plus_exit_time_us = 11.24, 613 .valid = true, 614 }, 615 { 616 .wm_inst = WM_D, 617 .wm_type = WM_TYPE_PSTATE_CHG, 618 .pstate_latency_us = 11.65333, 619 .sr_exit_time_us = 9.748, 620 .sr_enter_plus_exit_time_us = 11.102, 621 .valid = true, 622 }, 623 } 624 }; 625 626 627 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) 628 { 629 int i; 630 631 for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) { 632 if (clock_table->DcfClocks[i].Vol == voltage) 633 return clock_table->DcfClocks[i].Freq; 634 } 635 636 ASSERT(0); 637 return 0; 638 } 639 640 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) 641 { 642 int i, j = 0; 643 644 j = -1; 645 646 ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); 647 648 /* Find lowest DPM, FCLK is filled in reverse order*/ 649 650 for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) { 651 if (clock_table->FClocks[i].Freq != 0) { 652 j = i; 653 break; 654 } 655 } 656 657 if (j == -1) { 658 /* clock table is all 0s, just use our own hardcode */ 659 ASSERT(0); 660 return; 661 } 662 663 bw_params->clk_table.num_entries = j + 1; 664 665 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 666 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; 667 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; 668 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; 669 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); 670 } 671 672 bw_params->vram_type = bios_info->memory_type; 673 bw_params->num_channels = bios_info->ma_channel_number; 674 675 for (i = 0; i < WM_SET_COUNT; i++) { 676 bw_params->wm_table.entries[i].wm_inst = i; 677 678 if (i >= bw_params->clk_table.num_entries) { 679 bw_params->wm_table.entries[i].valid = false; 680 continue; 681 } 682 683 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 684 bw_params->wm_table.entries[i].valid = true; 685 } 686 687 if (bw_params->vram_type == LpDdr4MemType) { 688 /* 689 * WM set D will be re-purposed for memory retraining 690 */ 691 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; 692 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; 693 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; 694 bw_params->wm_table.entries[WM_D].valid = true; 695 } 696 697 } 698 699 void rn_clk_mgr_construct( 700 struct dc_context *ctx, 701 struct clk_mgr_internal *clk_mgr, 702 struct pp_smu_funcs *pp_smu, 703 struct dccg *dccg) 704 { 705 struct dc_debug_options *debug = &ctx->dc->debug; 706 struct dpm_clocks clock_table = { 0 }; 707 708 clk_mgr->base.ctx = ctx; 709 clk_mgr->base.funcs = &dcn21_funcs; 710 711 clk_mgr->pp_smu = pp_smu; 712 713 clk_mgr->dccg = dccg; 714 clk_mgr->dfs_bypass_disp_clk = 0; 715 716 clk_mgr->dprefclk_ss_percentage = 0; 717 clk_mgr->dprefclk_ss_divider = 1000; 718 clk_mgr->ss_on_dprefclk = false; 719 clk_mgr->dfs_ref_freq_khz = 48000; 720 721 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); 722 723 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 724 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga; 725 clk_mgr->base.dentist_vco_freq_khz = 3600000; 726 } else { 727 struct clk_log_info log_info = {0}; 728 729 /* TODO: Check we get what we expect during bringup */ 730 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); 731 732 /* in case we don't get a value from the register, use default */ 733 if (clk_mgr->base.dentist_vco_freq_khz == 0) 734 clk_mgr->base.dentist_vco_freq_khz = 3600000; 735 736 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { 737 rn_bw_params.wm_table = lpddr4_wm_table; 738 } else { 739 rn_bw_params.wm_table = ddr4_wm_table; 740 } 741 /* Saved clocks configured at boot for debug purposes */ 742 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info); 743 } 744 745 clk_mgr->base.dprefclk_khz = 600000; 746 dce_clock_read_ss_info(clk_mgr); 747 748 749 clk_mgr->base.bw_params = &rn_bw_params; 750 751 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { 752 pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); 753 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 754 rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info); 755 } 756 } 757 758 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { 759 /* enable powerfeatures when displaycount goes to 0 */ 760 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); 761 } 762 } 763 764
Indexes created Mon Sep 22 05:09:51 GMT 2025