/src/sys/arch/riscv/riscv/ |
db_machdep.c | 188 register_t rs1 = get_reg_value(tf, i.type_b.b_rs1); local in function:branch_taken 193 branch_p = (rs1 == rs2); 196 branch_p = ((rs1 & (1 << (i.type_b.b_rs2))) != 0); 199 branch_p = (rs1 < rs2); 203 branch_p = ((uregister_t)rs1 < (uregister_t)rs2);
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db_disasm.c | 140 unsigned rd, rs1, rs2; local in function:db_disasm_16 153 rs1 = INSN16_RS1x(insn); 158 riscv_registers[rs1]); 162 (int32_t)imm, riscv_registers[rs1]); 166 rs1 = INSN16_RS1x(insn); 170 (int32_t)imm, riscv_registers[rs1]); 173 rs1 = INSN16_RS1x(insn); 178 riscv_registers[rs1]); 182 (int32_t)imm, riscv_registers[rs1]); 186 rs1 = INSN16_RS1x(insn) [all...] |
/src/sys/arch/sparc/fpu/ |
fpu.c | 305 int opf, rs1, rs2, rd, type, mask, fsr, cx; local in function:fpu_execute 308 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; local in function:fpu_execute 337 rs1 = instr.i_opf.i_rs1; 338 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5); 344 if ((rs1 | rs2 | rd) & mask) 362 rs1 = fs->fs_regs[rs2]; 368 rs1 = fs->fs_regs[rs2]; 374 rs1 = fs->fs_regs[rs2] [all...] |
/src/sys/arch/sparc/sparc/ |
emul.c | 134 union instr *code, int32_t *rd, int32_t *rs1, int32_t *rs2) 173 * ignore the error and return *rd = *rs1. 180 *rd = *rs1 / *rs2; 181 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd)); 184 *rd = *rs1 * *rs2; 185 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd)); 198 if (*rd * *rs2 != *rs1) 202 if (*rd / *rs2 != *rs1) 248 int32_t rs1, rs2; local in function:fixalign 274 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) 388 int32_t rs1, rs2, rd; local in function:emulinstr [all...] |
/src/sys/arch/sparc64/sparc64/ |
emul.c | 132 muldiv(struct trapframe64 *tf, union instr *code, int32_t *rd, int32_t *rs1, 172 * ignore the error and return *rd = *rs1. 179 *rd = *rs1 / *rs2; 180 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd)); 183 *rd = *rs1 * *rs2; 184 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd)); 197 if (*rd * *rs2 != *rs1) 201 if (*rd / *rs2 != *rs1) 245 int64_t rs1, rs2; local in function:fixalign 271 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) 380 int32_t rs1, rs2, rd; local in function:emulinstr [all...] |
/src/sys/dev/ic/ |
isp.c | 3349 sns_gid_ft_rsp_t *rs0, *rs1; local in function:isp_scan_fabric 3422 rs1 = (sns_gid_ft_rsp_t *) ((uint8_t *)fcp->isp_scratch+OGPOFF); 3423 isp_get_gid_ft_response(isp, rs0, rs1, NGENT); 3429 if (rs1->snscb_cthdr.ct_cmd_resp != LS_ACC) { 3431 if (rs1->snscb_cthdr.ct_reason == 9 && 3432 rs1->snscb_cthdr.ct_explanation == 7) { 3439 rs1->snscb_cthdr.ct_reason, 3440 rs1->snscb_cthdr.ct_explanation); 3464 if (rs1->snscb_ports[portidx].control & 0x80) { 3472 if ((rs1->snscb_ports[portidx].control & 0x80) == 0) [all...] |