1 /* $NetBSD: dbcool.c,v 1.66 2025/09/21 13:54:56 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.66 2025/09/21 13:54:56 thorpej Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/sysctl.h> 60 #include <sys/module.h> 61 62 #include <dev/i2c/dbcool_var.h> 63 #include <dev/i2c/dbcool_reg.h> 64 65 /* Config interface */ 66 static int dbcool_match(device_t, cfdata_t, void *); 67 static void dbcool_attach(device_t, device_t, void *); 68 static int dbcool_detach(device_t, int); 69 70 /* Device attributes */ 71 static int dbcool_supply_voltage(struct dbcool_softc *); 72 static bool dbcool_islocked(struct dbcool_softc *); 73 74 /* Sensor read functions */ 75 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 76 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 77 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 78 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 79 80 /* Sensor get/set limit functions */ 81 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 82 sysmon_envsys_lim_t *, uint32_t *); 83 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 84 sysmon_envsys_lim_t *, uint32_t *); 85 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 86 sysmon_envsys_lim_t *, uint32_t *); 87 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 88 sysmon_envsys_lim_t *, uint32_t *); 89 90 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 91 sysmon_envsys_lim_t *, uint32_t *); 92 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 93 sysmon_envsys_lim_t *, uint32_t *); 94 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 95 sysmon_envsys_lim_t *, uint32_t *); 96 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 97 sysmon_envsys_lim_t *, uint32_t *); 98 99 /* SYSCTL Helpers */ 100 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct dbcool_sensor ADM1031_sensor_table[] = { 549 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 550 DBCOOL_ADM1030_L_HI_LIM, 551 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 552 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 553 DBCOOL_ADM1030_R_HI_LIM, 554 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 555 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 556 DBCOOL_ADM1031_R2_HI_LIM, 557 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 558 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 559 DBCOOL_NO_REG, 560 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 561 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 562 DBCOOL_NO_REG, 563 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 564 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 565 DBCOOL_NO_REG, 566 DBCOOL_NO_REG }, 0, 8, 0 }, 567 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 568 DBCOOL_NO_REG, 569 DBCOOL_NO_REG }, 0, 9, 0 }, 570 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 571 DBCOOL_NO_REG, 572 DBCOOL_NO_REG }, 0, 6, 0 }, 573 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 574 DBCOOL_NO_REG, 575 DBCOOL_NO_REG }, 1, 8, 0 }, 576 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 577 DBCOOL_NO_REG, 578 DBCOOL_NO_REG }, 1, 9, 0 }, 579 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 580 DBCOOL_NO_REG, 581 DBCOOL_NO_REG }, 1, 6, 0 }, 582 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 583 DBCOOL_NO_REG, 584 DBCOOL_NO_REG }, 2, 8, 0 }, 585 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 586 DBCOOL_NO_REG, 587 DBCOOL_NO_REG }, 2, 9, 0 }, 588 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 589 DBCOOL_NO_REG, 590 DBCOOL_NO_REG }, 2, 6, 0 }, 591 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 592 }; 593 594 struct dbcool_power_control ADM1031_power_table[] = { 595 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 596 DBCOOL_ADM1030_FAN_SPEED_CFG }, 597 "fan_control_1" }, 598 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 599 DBCOOL_ADM1030_FAN_SPEED_CFG }, 600 "fan_control_2" }, 601 { { 0, 0, 0, 0 }, NULL } 602 }; 603 604 struct dbcool_sensor EMC6D103S_sensor_table[] = { 605 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 606 DBCOOL_LOCAL_HIGHLIM, 607 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 608 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 609 DBCOOL_REMOTE1_HIGHLIM, 610 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 611 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 612 DBCOOL_REMOTE2_HIGHLIM, 613 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 614 { DBC_VOLT, { DBCOOL_VCCP, 615 DBCOOL_VCCP_HIGHLIM, 616 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 617 { DBC_VOLT, { DBCOOL_VCC, 618 DBCOOL_VCC_HIGHLIM, 619 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 620 { DBC_VOLT, { DBCOOL_25VIN, 621 DBCOOL_25VIN_HIGHLIM, 622 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 623 { DBC_VOLT, { DBCOOL_5VIN, 624 DBCOOL_5VIN_HIGHLIM, 625 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 626 { DBC_VOLT, { DBCOOL_12VIN, 627 DBCOOL_12VIN_HIGHLIM, 628 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 629 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 630 DBCOOL_NO_REG, 631 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 632 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 633 DBCOOL_NO_REG, 634 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 635 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 636 DBCOOL_NO_REG, 637 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 638 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 639 DBCOOL_NO_REG, 640 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 641 { DBC_VID, { DBCOOL_VID_REG, 642 DBCOOL_NO_REG, 643 DBCOOL_NO_REG }, 16, 0, 0 }, 644 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 645 DBCOOL_NO_REG, 646 DBCOOL_NO_REG }, 0, 5, 0 }, 647 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 648 DBCOOL_NO_REG, 649 DBCOOL_NO_REG }, 0, 6, 0 }, 650 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 651 DBCOOL_NO_REG, 652 DBCOOL_NO_REG }, 1, 5, 0 }, 653 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 654 DBCOOL_NO_REG, 655 DBCOOL_NO_REG }, 1, 6, 0 }, 656 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 657 DBCOOL_NO_REG, 658 DBCOOL_NO_REG }, 2, 5, 0 }, 659 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 660 DBCOOL_NO_REG, 661 DBCOOL_NO_REG }, 2, 6, 0 }, 662 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 663 }; 664 665 struct chip_id chip_table[] = { 666 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 667 ADT7490_sensor_table, ADT7475_power_table, 668 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 669 90000 * 60, "ADT7490" }, 670 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 671 ADT7476_sensor_table, ADT7475_power_table, 672 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 673 90000 * 60, "ADT7476" }, 674 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 675 ADT7475_sensor_table, ADT7475_power_table, 676 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 677 90000 * 60, "ADT7475" }, 678 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 679 ADT7475_sensor_table, ADT7475_power_table, 680 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 681 90000 * 60, "ADT7460/ADT7463" }, 682 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 683 ADT7475_sensor_table, ADT7475_power_table, 684 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 685 90000 * 60, "ADT7463-1" }, 686 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 687 ADT7476_sensor_table, ADT7475_power_table, 688 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 689 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 690 90000 * 60, "ADT7467/ADT7468" }, 691 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 692 ADT7466_sensor_table, NULL, 693 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 694 82000 * 60, "ADT7466" }, 695 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 696 ADM1027_sensor_table, ADT7475_power_table, 697 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 698 90000 * 60, "ADT7463" }, 699 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 700 ADM1027_sensor_table, ADT7475_power_table, 701 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 702 DBCFLAG_HAS_VID_SEL, 703 90000 * 60, "ADT7463" }, 704 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 705 ADM1027_sensor_table, ADT7475_power_table, 706 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 707 90000 * 60, "ADM1027" }, 708 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 709 ADM1030_sensor_table, ADM1030_power_table, 710 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 711 11250 * 60, "ADM1030" }, 712 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 713 ADM1031_sensor_table, ADM1030_power_table, 714 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 715 11250 * 60, "ADM1031" }, 716 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 717 EMC6D103S_sensor_table, ADT7475_power_table, 718 DBCFLAG_4BIT_VER, 719 90000 * 60, "EMC6D103S" }, 720 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 721 }; 722 723 static const char *behavior[] = { 724 "remote1", "local", "remote2", "full-speed", 725 "disabled", "local+remote2","all-temps", "manual" 726 }; 727 728 static char dbcool_cur_behav[16]; 729 730 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 731 dbcool_match, dbcool_attach, dbcool_detach, NULL); 732 733 static const struct device_compatible_entry compat_data[] = { 734 { .compat = "i2c-adm1031" }, 735 { .compat = "adt7467" }, 736 { .compat = "adt7460" }, 737 { .compat = "adm1030" }, 738 DEVICE_COMPAT_EOL 739 }; 740 741 int 742 dbcool_match(device_t parent, cfdata_t cf, void *aux) 743 { 744 struct i2c_attach_args *ia = aux; 745 struct dbcool_chipset dc; 746 dc.dc_tag = ia->ia_tag; 747 dc.dc_addr = ia->ia_addr; 748 dc.dc_chip = NULL; 749 dc.dc_readreg = dbcool_readreg; 750 dc.dc_writereg = dbcool_writereg; 751 int match_result; 752 753 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 754 return match_result; 755 756 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 757 return 0; 758 if (dbcool_chip_ident(&dc) >= 0) 759 return I2C_MATCH_ADDRESS_AND_PROBE; 760 761 return 0; 762 } 763 764 void 765 dbcool_attach(device_t parent, device_t self, void *aux) 766 { 767 struct dbcool_softc *sc = device_private(self); 768 struct i2c_attach_args *args = aux; 769 uint8_t ver; 770 771 sc->sc_dc.dc_addr = args->ia_addr; 772 sc->sc_dc.dc_tag = args->ia_tag; 773 sc->sc_dc.dc_chip = NULL; 774 sc->sc_dc.dc_readreg = dbcool_readreg; 775 sc->sc_dc.dc_writereg = dbcool_writereg; 776 sc->sc_dev = self; 777 778 if (dbcool_chip_ident(&sc->sc_dc) < 0 || sc->sc_dc.dc_chip == NULL) 779 panic("could not identify chip at addr %d", args->ia_addr); 780 781 aprint_naive("\n"); 782 aprint_normal("\n"); 783 784 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 785 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 786 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 787 { 788 aprint_normal_dev(self, "SMSC %s Controller " 789 "(rev 0x%02x, stepping 0x%02x)\n", 790 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 791 } else { 792 aprint_normal_dev(self, "%s dBCool(tm) Controller " 793 "(rev 0x%02x, stepping 0x%02x)\n", 794 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 795 } 796 else 797 aprint_normal_dev(self, "%s dBCool(tm) Controller " 798 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 799 800 sc->sc_sysctl_log = NULL; 801 802 #ifdef _MODULE 803 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 804 #endif 805 806 dbcool_setup(self); 807 808 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 809 aprint_error_dev(self, "couldn't establish power handler\n"); 810 } 811 812 static int 813 dbcool_detach(device_t self, int flags) 814 { 815 struct dbcool_softc *sc = device_private(self); 816 817 pmf_device_deregister(self); 818 819 if (sc->sc_sme != NULL) 820 sysmon_envsys_unregister(sc->sc_sme); 821 822 sysctl_teardown(&sc->sc_sysctl_log); 823 824 return 0; 825 } 826 827 /* 828 * On suspend, we save the state of the SHDN bit, then set it 829 * On resume, we restore the previous state of the SHDN bit (which 830 * we saved in sc_suspend) 831 */ 832 static bool 833 dbcool_do_pmf(device_t dev, const pmf_qual_t *qual, bool suspend) 834 { 835 struct dbcool_softc *sc = device_private(dev); 836 uint8_t reg, bit, cfg; 837 838 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 839 return true; 840 841 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 842 reg = DBCOOL_ADT7466_CONFIG2; 843 bit = DBCOOL_ADT7466_CFG2_SHDN; 844 } else { 845 reg = DBCOOL_CONFIG2_REG; 846 bit = DBCOOL_CFG2_SHDN; 847 } 848 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 849 if (suspend) { 850 sc->sc_suspend = (cfg & bit) != 0; 851 cfg |= bit; 852 } else { 853 cfg &= sc->sc_suspend ? bit : 0; 854 } 855 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 856 857 return true; 858 } 859 860 bool 861 dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 862 { 863 864 return dbcool_do_pmf(dev, qual, true); 865 } 866 867 bool 868 dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 869 { 870 871 return dbcool_do_pmf(dev, qual, false); 872 } 873 874 uint8_t 875 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 876 { 877 uint8_t data = 0; 878 879 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 880 return data; 881 882 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 883 /* ADM1027 doesn't support i2c read_byte protocol */ 884 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 885 goto bad; 886 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 887 } else 888 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 889 0); 890 891 bad: 892 iic_release_bus(dc->dc_tag, 0); 893 return data; 894 } 895 896 void 897 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 898 { 899 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 900 return; 901 902 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 903 904 iic_release_bus(dc->dc_tag, 0); 905 } 906 907 static bool 908 dbcool_islocked(struct dbcool_softc *sc) 909 { 910 uint8_t cfg_reg; 911 912 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 913 return 0; 914 915 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 916 cfg_reg = DBCOOL_ADT7466_CONFIG1; 917 else 918 cfg_reg = DBCOOL_CONFIG1_REG; 919 920 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 921 return 1; 922 else 923 return 0; 924 } 925 926 static int 927 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 928 { 929 uint8_t t1, t2, t3, val, ext = 0; 930 int temp; 931 932 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 933 /* 934 * ADT7466 temps are in strange location 935 */ 936 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 937 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 938 if (extres) 939 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 940 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 941 /* 942 * ADM1030 temps are in their own special place, too 943 */ 944 if (extres) { 945 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 946 if (reg == DBCOOL_ADM1030_L_TEMP) 947 ext >>= 6; 948 else if (reg == DBCOOL_ADM1031_R2_TEMP) 949 ext >>= 4; 950 else 951 ext >>= 1; 952 ext &= 0x03; 953 } 954 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 955 } else if (extres) { 956 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 957 958 /* Read all msb regs to unlatch them */ 959 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 960 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 961 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 962 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 963 switch (reg) { 964 case DBCOOL_REMOTE1_TEMP: 965 val = t1; 966 ext >>= 2; 967 break; 968 case DBCOOL_LOCAL_TEMP: 969 val = t3; 970 ext >>= 4; 971 break; 972 case DBCOOL_REMOTE2_TEMP: 973 val = t2; 974 ext >>= 6; 975 break; 976 default: 977 val = 0; 978 break; 979 } 980 ext &= 0x03; 981 } 982 else 983 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 984 985 /* Check for invalid temp values */ 986 if ((sc->sc_temp_offset == 0 && val == 0x80) || 987 (sc->sc_temp_offset != 0 && val == 0)) 988 return 0; 989 990 /* If using offset mode, adjust, else treat as signed */ 991 if (sc->sc_temp_offset) { 992 temp = val; 993 temp -= sc->sc_temp_offset; 994 } else 995 temp = (int8_t)val; 996 997 /* Convert degC to uK and include extended precision bits */ 998 temp *= 1000000; 999 temp += 250000 * (int)ext; 1000 temp += 273150000U; 1001 1002 return temp; 1003 } 1004 1005 static int 1006 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 1007 { 1008 int rpm; 1009 uint8_t rpm_lo, rpm_hi; 1010 1011 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1012 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1013 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1014 else 1015 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1016 1017 rpm = (rpm_hi << 8) | rpm_lo; 1018 if (rpm == 0xffff) 1019 return 0; /* 0xffff indicates stalled/failed fan */ 1020 1021 /* don't divide by zero */ 1022 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1023 } 1024 1025 /* Provide chip's supply voltage, in microvolts */ 1026 static int 1027 dbcool_supply_voltage(struct dbcool_softc *sc) 1028 { 1029 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1030 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1031 return 5002500; 1032 else 1033 return 3300000; 1034 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1035 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1036 DBCOOL_ADT7466_CFG1_Vcc) 1037 return 5000000; 1038 else 1039 return 3300000; 1040 } else 1041 return 3300000; 1042 } 1043 1044 /* 1045 * Nominal voltages are calculated in microvolts 1046 */ 1047 static int 1048 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1049 { 1050 uint8_t ext = 0, v1, v2, v3, v4, val; 1051 int64_t ret; 1052 int64_t nom; 1053 1054 nom = nominal_voltages[nom_idx]; 1055 if (nom < 0) 1056 nom = sc->sc_supply_voltage; 1057 1058 /* ADT7466 voltages are in strange locations with only 8-bits */ 1059 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1060 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1061 else 1062 /* 1063 * It's a "normal" dbCool chip - check for regs that 1064 * share extended resolution bits since we have to 1065 * read all the MSB registers to unlatch them. 1066 */ 1067 if (!extres) 1068 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1069 else if (reg == DBCOOL_12VIN) { 1070 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1071 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1072 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1073 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1074 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1075 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1076 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1077 if (reg == DBCOOL_IMON) { 1078 val = v1; 1079 ext >>= 6; 1080 } else { 1081 val = v2; 1082 ext >>= 4; 1083 } 1084 ext &= 0x0f; 1085 } else { 1086 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1087 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1088 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1089 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1090 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1091 1092 switch (reg) { 1093 case DBCOOL_25VIN: 1094 val = v1; 1095 break; 1096 case DBCOOL_VCCP: 1097 val = v2; 1098 ext >>= 2; 1099 break; 1100 case DBCOOL_VCC: 1101 val = v3; 1102 ext >>= 4; 1103 break; 1104 case DBCOOL_5VIN: 1105 val = v4; 1106 ext >>= 6; 1107 break; 1108 default: 1109 val = nom = 0; 1110 } 1111 ext &= 0x03; 1112 } 1113 1114 /* 1115 * Scale the nominal value by the 10-bit fraction 1116 * 1117 * Returned value is in microvolts. 1118 */ 1119 ret = val; 1120 ret <<= 2; 1121 ret |= ext; 1122 ret = (ret * nom) / 0x300; 1123 1124 return ret; 1125 } 1126 1127 static int 1128 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1129 { 1130 struct sysctlnode node; 1131 struct dbcool_softc *sc; 1132 int reg, error; 1133 uint8_t chipreg; 1134 uint8_t newreg; 1135 1136 node = *rnode; 1137 sc = (struct dbcool_softc *)node.sysctl_data; 1138 chipreg = node.sysctl_num & 0xff; 1139 1140 if (sc->sc_temp_offset) { 1141 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1142 reg -= sc->sc_temp_offset; 1143 } else 1144 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1145 1146 node.sysctl_data = ® 1147 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1148 1149 if (error || newp == NULL) 1150 return error; 1151 1152 /* We were asked to update the value - sanity check before writing */ 1153 if (*(int *)node.sysctl_data < -64 || 1154 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1155 return EINVAL; 1156 1157 newreg = *(int *)node.sysctl_data; 1158 newreg += sc->sc_temp_offset; 1159 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1160 return 0; 1161 } 1162 1163 static int 1164 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1165 { 1166 struct sysctlnode node; 1167 struct dbcool_softc *sc; 1168 int reg, error; 1169 uint8_t chipreg, oldreg, newreg; 1170 1171 node = *rnode; 1172 sc = (struct dbcool_softc *)node.sysctl_data; 1173 chipreg = node.sysctl_num & 0xff; 1174 1175 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1176 reg = (oldreg >> 1) & ~0x03; 1177 1178 node.sysctl_data = ® 1179 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1180 1181 if (error || newp == NULL) 1182 return error; 1183 1184 /* We were asked to update the value - sanity check before writing */ 1185 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1186 return EINVAL; 1187 1188 newreg = *(int *)node.sysctl_data; 1189 newreg &= ~0x03; 1190 newreg <<= 1; 1191 newreg |= (oldreg & 0x07); 1192 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1193 return 0; 1194 } 1195 1196 static int 1197 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1198 { 1199 struct sysctlnode node; 1200 struct dbcool_softc *sc; 1201 int reg, error, newval; 1202 uint8_t chipreg, oldreg, newreg; 1203 1204 node = *rnode; 1205 sc = (struct dbcool_softc *)node.sysctl_data; 1206 chipreg = node.sysctl_num & 0xff; 1207 1208 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1209 reg = oldreg & 0x07; 1210 1211 node.sysctl_data = ® 1212 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1213 1214 if (error || newp == NULL) 1215 return error; 1216 1217 /* We were asked to update the value - sanity check before writing */ 1218 newval = *(int *)node.sysctl_data; 1219 1220 if (newval == 5) 1221 newreg = 0; 1222 else if (newval == 10) 1223 newreg = 1; 1224 else if (newval == 20) 1225 newreg = 2; 1226 else if (newval == 40) 1227 newreg = 3; 1228 else if (newval == 80) 1229 newreg = 4; 1230 else 1231 return EINVAL; 1232 1233 newreg |= (oldreg & ~0x07); 1234 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1235 return 0; 1236 } 1237 1238 static int 1239 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1240 { 1241 struct sysctlnode node; 1242 struct dbcool_softc *sc; 1243 int reg, error; 1244 uint8_t chipreg, oldreg, newreg; 1245 1246 node = *rnode; 1247 sc = (struct dbcool_softc *)node.sysctl_data; 1248 chipreg = node.sysctl_num & 0xff; 1249 1250 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1251 reg = (uint32_t)oldreg; 1252 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1253 reg = ((reg & 0x0f) * 100) / 15; 1254 else 1255 reg = (reg * 100) / 255; 1256 node.sysctl_data = ® 1257 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1258 1259 if (error || newp == NULL) 1260 return error; 1261 1262 /* We were asked to update the value - sanity check before writing */ 1263 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1264 return EINVAL; 1265 1266 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1267 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1268 newreg |= oldreg & 0xf0; 1269 } else 1270 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1271 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1272 return 0; 1273 } 1274 1275 static int 1276 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1277 { 1278 struct sysctlnode node; 1279 struct dbcool_softc *sc; 1280 int i, reg, error; 1281 uint8_t chipreg, oldreg, newreg; 1282 1283 node = *rnode; 1284 sc = (struct dbcool_softc *)node.sysctl_data; 1285 chipreg = node.sysctl_num & 0xff; 1286 1287 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1288 1289 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1290 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1291 reg = 4; 1292 else if ((oldreg & 0x80) == 0) 1293 reg = 7; 1294 else if ((oldreg & 0x60) == 0) 1295 reg = 4; 1296 else 1297 reg = 6; 1298 } else 1299 reg = (oldreg >> 5) & 0x07; 1300 1301 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1302 node.sysctl_data = dbcool_cur_behav; 1303 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1304 1305 if (error || newp == NULL) 1306 return error; 1307 1308 /* We were asked to update the value - convert string to value */ 1309 newreg = __arraycount(behavior); 1310 for (i = 0; i < __arraycount(behavior); i++) 1311 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1312 break; 1313 if (i >= __arraycount(behavior)) 1314 return EINVAL; 1315 newreg = i; 1316 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1317 /* 1318 * ADM1030 splits fan controller behavior across two 1319 * registers. We also do not support Auto-Filter mode 1320 * nor do we support Manual-RPM-feedback. 1321 */ 1322 if (newreg == 4) { 1323 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1324 oldreg &= ~0x01; 1325 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1326 } else { 1327 if (newreg == 0) 1328 newreg = 4; 1329 else if (newreg == 6) 1330 newreg = 7; 1331 else if (newreg == 7) 1332 newreg = 0; 1333 else 1334 return EINVAL; 1335 newreg <<= 5; 1336 newreg |= (oldreg & 0x1f); 1337 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1338 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1339 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1340 } 1341 } else { 1342 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1343 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1344 } 1345 return 0; 1346 } 1347 1348 static int 1349 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1350 { 1351 struct sysctlnode node; 1352 struct dbcool_softc *sc; 1353 int reg, error; 1354 uint8_t chipreg; 1355 uint8_t newreg; 1356 1357 node = *rnode; 1358 sc = (struct dbcool_softc *)node.sysctl_data; 1359 chipreg = node.sysctl_num & 0xff; 1360 1361 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1362 node.sysctl_data = ® 1363 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1364 1365 if (error || newp == NULL) 1366 return error; 1367 1368 /* We were asked to update the value - sanity check before writing */ 1369 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1370 return EINVAL; 1371 1372 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1373 (*(int *)node.sysctl_data << 4); 1374 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1375 return 0; 1376 } 1377 1378 static int 1379 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1380 { 1381 struct sysctlnode node; 1382 struct dbcool_softc *sc; 1383 int reg, error; 1384 uint8_t chipreg; 1385 uint8_t newreg, newhyst; 1386 1387 node = *rnode; 1388 sc = (struct dbcool_softc *)node.sysctl_data; 1389 chipreg = node.sysctl_num & 0x7f; 1390 1391 /* retrieve 4-bit value */ 1392 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1393 if ((node.sysctl_num & 0x80) == 0) 1394 reg = newreg >> 4; 1395 else 1396 reg = newreg; 1397 reg = reg & 0x0f; 1398 1399 node.sysctl_data = ® 1400 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1401 1402 if (error || newp == NULL) 1403 return error; 1404 1405 /* We were asked to update the value - sanity check before writing */ 1406 newhyst = *(int *)node.sysctl_data; 1407 if (newhyst > 0x0f) 1408 return EINVAL; 1409 1410 /* Insert new value into field and update register */ 1411 if ((node.sysctl_num & 0x80) == 0) { 1412 newreg &= 0x0f; 1413 newreg |= (newhyst << 4); 1414 } else { 1415 newreg &= 0xf0; 1416 newreg |= newhyst; 1417 } 1418 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1419 return 0; 1420 } 1421 1422 #ifdef DBCOOL_DEBUG 1423 1424 /* 1425 * These routines can be used for debugging. reg_select is used to 1426 * select any arbitrary register in the device. reg_access is used 1427 * to read (and optionally update) the selected register. 1428 * 1429 * No attempt is made to validate the data passed. If you use these 1430 * routines, you are assumed to know what you're doing! 1431 * 1432 * Caveat user 1433 */ 1434 static int 1435 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1436 { 1437 struct sysctlnode node; 1438 struct dbcool_softc *sc; 1439 int reg, error; 1440 1441 node = *rnode; 1442 sc = (struct dbcool_softc *)node.sysctl_data; 1443 1444 reg = sc->sc_user_reg; 1445 node.sysctl_data = ® 1446 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1447 1448 if (error || newp == NULL) 1449 return error; 1450 1451 sc->sc_user_reg = *(int *)node.sysctl_data; 1452 return 0; 1453 } 1454 1455 static int 1456 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1457 { 1458 struct sysctlnode node; 1459 struct dbcool_softc *sc; 1460 int reg, error; 1461 uint8_t chipreg; 1462 uint8_t newreg; 1463 1464 node = *rnode; 1465 sc = (struct dbcool_softc *)node.sysctl_data; 1466 chipreg = sc->sc_user_reg; 1467 1468 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1469 node.sysctl_data = ® 1470 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1471 1472 if (error || newp == NULL) 1473 return error; 1474 1475 newreg = *(int *)node.sysctl_data; 1476 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1477 return 0; 1478 } 1479 #endif /* DBCOOL_DEBUG */ 1480 1481 /* 1482 * Encode an index number and register number for use as a sysctl_num 1483 * so we can select the correct device register later. 1484 */ 1485 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1486 1487 void 1488 dbcool_setup(device_t self) 1489 { 1490 struct dbcool_softc *sc = device_private(self); 1491 const struct sysctlnode *me = NULL; 1492 #ifdef DBCOOL_DEBUG 1493 struct sysctlnode *node = NULL; 1494 #endif 1495 uint8_t cfg_val, cfg_reg; 1496 int ret, error; 1497 1498 /* 1499 * Some chips are capable of reporting an extended temperature range 1500 * by default. On these models, config register 5 bit 0 can be set 1501 * to 1 for compatibility with other chips that report 2s complement. 1502 */ 1503 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1504 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1505 sc->sc_temp_offset = 64; 1506 else 1507 sc->sc_temp_offset = 0; 1508 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1509 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1510 DBCOOL_CFG5_TWOSCOMP) 1511 sc->sc_temp_offset = 0; 1512 else 1513 sc->sc_temp_offset = 64; 1514 } else 1515 sc->sc_temp_offset = 0; 1516 1517 /* Determine Vcc for this chip */ 1518 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1519 1520 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1521 CTLFLAG_READWRITE, 1522 CTLTYPE_NODE, device_xname(self), NULL, 1523 NULL, 0, NULL, 0, 1524 CTL_HW, CTL_CREATE, CTL_EOL); 1525 if (ret == 0) 1526 sc->sc_root_sysctl_num = me->sysctl_num; 1527 else 1528 sc->sc_root_sysctl_num = 0; 1529 1530 aprint_debug_dev(self, 1531 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1532 sc->sc_supply_voltage / 1000000, 1533 sc->sc_supply_voltage % 1000000, 1534 sc->sc_temp_offset ? "extended" : "normal"); 1535 1536 /* Create the sensors for this device */ 1537 sc->sc_sme = sysmon_envsys_create(); 1538 if (dbcool_setup_sensors(sc)) 1539 goto out; 1540 1541 if (sc->sc_root_sysctl_num != 0) { 1542 /* If supported, create sysctl tree for fan PWM controllers */ 1543 if (sc->sc_dc.dc_chip->power != NULL) 1544 dbcool_setup_controllers(sc); 1545 1546 #ifdef DBCOOL_DEBUG 1547 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1548 (void *)&node, 1549 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1550 sysctl_dbcool_reg_select, 1551 0, (void *)sc, sizeof(int), 1552 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1553 if (node != NULL) 1554 node->sysctl_data = sc; 1555 1556 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1557 (void *)&node, 1558 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1559 sysctl_dbcool_reg_access, 1560 0, (void *)sc, sizeof(int), 1561 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1562 if (node != NULL) 1563 node->sysctl_data = sc; 1564 #endif /* DBCOOL_DEBUG */ 1565 } 1566 1567 /* 1568 * Read and rewrite config register to activate device 1569 */ 1570 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1571 cfg_reg = DBCOOL_ADM1030_CFG1; 1572 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1573 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1574 else 1575 cfg_reg = DBCOOL_CONFIG1_REG; 1576 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1577 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1578 cfg_val |= DBCOOL_CFG1_START; 1579 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1580 } 1581 if (dbcool_islocked(sc)) 1582 aprint_normal_dev(self, "configuration locked\n"); 1583 1584 sc->sc_sme->sme_name = device_xname(self); 1585 sc->sc_sme->sme_cookie = sc; 1586 sc->sc_sme->sme_refresh = dbcool_refresh; 1587 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1588 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1589 1590 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1591 aprint_error_dev(self, 1592 "unable to register with sysmon (%d)\n", error); 1593 goto out; 1594 } 1595 1596 return; 1597 1598 out: 1599 sysmon_envsys_destroy(sc->sc_sme); 1600 sc->sc_sme = NULL; 1601 } 1602 1603 static int 1604 dbcool_setup_sensors(struct dbcool_softc *sc) 1605 { 1606 int i; 1607 int error = 0; 1608 uint8_t vid_reg, vid_val; 1609 struct chip_id *chip = sc->sc_dc.dc_chip; 1610 1611 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1612 if (i < DBCOOL_MAXSENSORS) 1613 sc->sc_sysctl_num[i] = -1; 1614 else if (chip->table[i].type != DBC_CTL) { 1615 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1616 break; 1617 } 1618 switch (chip->table[i].type) { 1619 case DBC_TEMP: 1620 sc->sc_sensor[i].units = ENVSYS_STEMP; 1621 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1622 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1623 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1624 error = dbcool_attach_sensor(sc, i); 1625 break; 1626 case DBC_VOLT: 1627 /* 1628 * If 12V-In pin has been reconfigured as 6th bit 1629 * of VID code, don't create a 12V-In sensor 1630 */ 1631 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1632 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1633 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1634 0x80)) 1635 break; 1636 1637 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1638 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1639 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1640 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1641 error = dbcool_attach_sensor(sc, i); 1642 break; 1643 case DBC_FAN: 1644 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1645 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1646 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1647 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1648 error = dbcool_attach_sensor(sc, i); 1649 break; 1650 case DBC_VID: 1651 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1652 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1653 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1654 1655 /* retrieve 5- or 6-bit value */ 1656 vid_reg = chip->table[i].reg.val_reg; 1657 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1658 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1659 vid_val &= 0x3f; 1660 else 1661 vid_val &= 0x1f; 1662 sc->sc_sensor[i].value_cur = vid_val; 1663 1664 error = dbcool_attach_sensor(sc, i); 1665 break; 1666 case DBC_CTL: 1667 error = dbcool_attach_temp_control(sc, i, chip); 1668 if (error) { 1669 aprint_error_dev(sc->sc_dev, 1670 "attach index %d failed %d\n", 1671 i, error); 1672 error = 0; 1673 } 1674 break; 1675 default: 1676 aprint_error_dev(sc->sc_dev, 1677 "sensor_table index %d has bad type %d\n", 1678 i, chip->table[i].type); 1679 break; 1680 } 1681 if (error) 1682 break; 1683 } 1684 return error; 1685 } 1686 1687 static int 1688 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1689 { 1690 prop_dictionary_t props = device_properties(sc->sc_dev); 1691 int name_index; 1692 int error = 0; 1693 char name[8]; 1694 const char *desc; 1695 1696 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1697 snprintf(name, 7, "s%02x", sc->sc_dc.dc_chip->table[idx].reg.val_reg); 1698 if (prop_dictionary_get_string(props, name, &desc)) { 1699 strlcpy(sc->sc_sensor[idx].desc, desc, 1700 sizeof(sc->sc_sensor[idx].desc)); 1701 } else { 1702 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1703 sizeof(sc->sc_sensor[idx].desc)); 1704 } 1705 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1706 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1707 1708 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1709 return error; 1710 } 1711 1712 static int 1713 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1714 struct chip_id *chip) 1715 { 1716 const struct sysctlnode *me2 = NULL, *node; 1717 int j, ret, sysctl_index, rw_flag; 1718 uint8_t sysctl_reg; 1719 char name[SYSCTL_NAMELEN]; 1720 1721 /* Search for the corresponding temp sensor */ 1722 for (j = 0; j < idx; j++) { 1723 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1724 continue; 1725 if (chip->table[j].name_index == chip->table[idx].name_index) 1726 break; 1727 } 1728 if (j >= idx) /* Temp sensor not found */ 1729 return ENOENT; 1730 1731 /* create sysctl node for the sensor if not one already there */ 1732 if (sc->sc_sysctl_num[j] == -1) { 1733 int name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1734 1735 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1736 CTLFLAG_READWRITE, 1737 CTLTYPE_NODE, dbc_sensor_names[name_index], 1738 sc->sc_sensor[j].desc, 1739 NULL, 0, NULL, 0, 1740 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1741 CTL_EOL); 1742 if (me2 != NULL) 1743 sc->sc_sysctl_num[j] = me2->sysctl_num; 1744 else 1745 return ret; 1746 } 1747 /* add sysctl leaf node for this control variable */ 1748 sysctl_index = chip->table[idx].sysctl_index; 1749 sysctl_reg = chip->table[idx].reg.val_reg; 1750 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1751 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1752 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1753 else 1754 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1755 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1756 CTLTYPE_INT, name, 1757 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1758 dbc_sysctl_table[sysctl_index].helper, 1759 0, (void *)sc, sizeof(int), 1760 CTL_HW, sc->sc_root_sysctl_num, 1761 sc->sc_sysctl_num[j], 1762 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1763 1764 return ret; 1765 } 1766 1767 static void 1768 dbcool_setup_controllers(struct dbcool_softc *sc) 1769 { 1770 int i, j, rw_flag; 1771 uint8_t sysctl_reg; 1772 struct chip_id *chip = sc->sc_dc.dc_chip; 1773 const struct sysctlnode *me2 = NULL; 1774 const struct sysctlnode *node = NULL; 1775 char name[SYSCTL_NAMELEN]; 1776 1777 for (i = 0; chip->power[i].desc != NULL; i++) { 1778 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1779 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1780 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1781 CTLTYPE_NODE, name, NULL, 1782 NULL, 0, NULL, 0, 1783 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1784 1785 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1786 if (j == DBC_PWM_MAX_DUTY && 1787 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1788 continue; 1789 sysctl_reg = chip->power[i].power_regs[j]; 1790 if (sysctl_reg == DBCOOL_NO_REG) 1791 continue; 1792 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1793 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1794 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1795 else 1796 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1797 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1798 &node, rw_flag, 1799 (j == DBC_PWM_BEHAVIOR)? 1800 CTLTYPE_STRING:CTLTYPE_INT, 1801 name, 1802 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1803 dbc_sysctl_table[j].helper, 1804 0, sc, 1805 ( j == DBC_PWM_BEHAVIOR)? 1806 sizeof(dbcool_cur_behav): sizeof(int), 1807 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1808 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1809 } 1810 } 1811 } 1812 1813 static void 1814 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1815 { 1816 struct dbcool_softc *sc=sme->sme_cookie; 1817 int i, nom_volt_idx, cur; 1818 struct reg_list *reg; 1819 1820 i = edata->sensor; 1821 reg = sc->sc_regs[i]; 1822 1823 edata->state = ENVSYS_SVALID; 1824 switch (edata->units) 1825 { 1826 case ENVSYS_STEMP: 1827 cur = dbcool_read_temp(sc, reg->val_reg, true); 1828 break; 1829 case ENVSYS_SVOLTS_DC: 1830 nom_volt_idx = sc->sc_nom_volt[i]; 1831 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1832 true); 1833 break; 1834 case ENVSYS_SFANRPM: 1835 cur = dbcool_read_rpm(sc, reg->val_reg); 1836 break; 1837 case ENVSYS_INTEGER: 1838 return; 1839 default: 1840 edata->state = ENVSYS_SINVALID; 1841 return; 1842 } 1843 1844 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1845 edata->state = ENVSYS_SINVALID; 1846 1847 /* 1848 * If fan is "stalled" but has no low limit, treat 1849 * it as though the fan is not installed. 1850 */ 1851 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1852 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1853 edata->state = ENVSYS_SINVALID; 1854 1855 edata->value_cur = cur; 1856 } 1857 1858 int 1859 dbcool_chip_ident(struct dbcool_chipset *dc) 1860 { 1861 /* verify this is a supported dbCool chip */ 1862 uint8_t c_id, d_id, r_id; 1863 int i; 1864 1865 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1866 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1867 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1868 1869 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1870 * NULL when we call dc->dc_readreg above we use 1871 * send_byte/receive_byte which doesn't work. 1872 * 1873 * So if we only get 0's back then try again with dc->dc_chip 1874 * set to the EMC6D103S_DEVICEID and which doesn't have 1875 * DBCFLAG_NO_READBYTE set so read_byte will be used 1876 */ 1877 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1878 for (i = 0; chip_table[i].company != 0; i++) 1879 if ((SMSC_COMPANYID == chip_table[i].company) && 1880 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1881 dc->dc_chip = &chip_table[i]; 1882 break; 1883 } 1884 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1885 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1886 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1887 } 1888 1889 for (i = 0; chip_table[i].company != 0; i++) 1890 if ((c_id == chip_table[i].company) && 1891 (d_id == chip_table[i].device || 1892 chip_table[i].device == 0xff) && 1893 (r_id == chip_table[i].rev || 1894 chip_table[i].rev == 0xff)) { 1895 dc->dc_chip = &chip_table[i]; 1896 return i; 1897 } 1898 1899 aprint_debug("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1900 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1901 r_id); 1902 1903 return -1; 1904 } 1905 1906 /* 1907 * Retrieve sensor limits from the chip registers 1908 */ 1909 static void 1910 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1911 sysmon_envsys_lim_t *limits, uint32_t *props) 1912 { 1913 int index = edata->sensor; 1914 struct dbcool_softc *sc = sme->sme_cookie; 1915 1916 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1917 switch (edata->units) { 1918 case ENVSYS_STEMP: 1919 dbcool_get_temp_limits(sc, index, limits, props); 1920 break; 1921 case ENVSYS_SVOLTS_DC: 1922 dbcool_get_volt_limits(sc, index, limits, props); 1923 break; 1924 case ENVSYS_SFANRPM: 1925 dbcool_get_fan_limits(sc, index, limits, props); 1926 1927 /* FALLTHROUGH */ 1928 default: 1929 break; 1930 } 1931 *props &= ~PROP_DRIVER_LIMITS; 1932 1933 /* If both limits provided, make sure they're sane */ 1934 if ((*props & PROP_CRITMIN) && 1935 (*props & PROP_CRITMAX) && 1936 (limits->sel_critmin >= limits->sel_critmax)) 1937 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1938 1939 /* 1940 * If this is the first time through, save these values 1941 * in case user overrides them and then requests a reset. 1942 */ 1943 if (sc->sc_defprops[index] == 0) { 1944 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1945 sc->sc_deflims[index] = *limits; 1946 } 1947 } 1948 1949 static void 1950 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1951 sysmon_envsys_lim_t *lims, uint32_t *props) 1952 { 1953 struct reg_list *reg = sc->sc_regs[idx]; 1954 uint8_t lo_lim, hi_lim; 1955 1956 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1957 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1958 1959 if (sc->sc_temp_offset) { 1960 if (lo_lim > 0x01) { 1961 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1962 *props |= PROP_CRITMIN; 1963 } 1964 if (hi_lim != 0xff) { 1965 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1966 *props |= PROP_CRITMAX; 1967 } 1968 } else { 1969 if (lo_lim != 0x80 && lo_lim != 0x81) { 1970 lims->sel_critmin = (int8_t)lo_lim; 1971 *props |= PROP_CRITMIN; 1972 } 1973 1974 if (hi_lim != 0x7f) { 1975 lims->sel_critmax = (int8_t)hi_lim; 1976 *props |= PROP_CRITMAX; 1977 } 1978 } 1979 1980 /* Convert temp limits to microKelvin */ 1981 lims->sel_critmin *= 1000000; 1982 lims->sel_critmin += 273150000; 1983 lims->sel_critmax *= 1000000; 1984 lims->sel_critmax += 273150000; 1985 } 1986 1987 static void 1988 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1989 sysmon_envsys_lim_t *lims, uint32_t *props) 1990 { 1991 struct reg_list *reg = sc->sc_regs[idx]; 1992 int64_t limit; 1993 int nom; 1994 1995 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1996 if (nom < 0) 1997 nom = dbcool_supply_voltage(sc); 1998 nom *= 1000000; /* scale for microvolts */ 1999 2000 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 2001 if (limit != 0x00 && limit != 0xff) { 2002 limit *= nom; 2003 limit /= 0xc0; 2004 lims->sel_critmin = limit; 2005 *props |= PROP_CRITMIN; 2006 } 2007 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 2008 if (limit != 0x00 && limit != 0xff) { 2009 limit *= nom; 2010 limit /= 0xc0; 2011 lims->sel_critmax = limit; 2012 *props |= PROP_CRITMAX; 2013 } 2014 } 2015 2016 static void 2017 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 2018 sysmon_envsys_lim_t *lims, uint32_t *props) 2019 { 2020 struct reg_list *reg = sc->sc_regs[idx]; 2021 int32_t limit; 2022 2023 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 2024 if (limit) { 2025 lims->sel_critmin = limit; 2026 *props |= PROP_CRITMIN; 2027 } 2028 } 2029 2030 /* 2031 * Update sensor limits in the chip registers 2032 */ 2033 static void 2034 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2035 sysmon_envsys_lim_t *limits, uint32_t *props) 2036 { 2037 int index = edata->sensor; 2038 struct dbcool_softc *sc = sme->sme_cookie; 2039 2040 if (limits == NULL) { 2041 limits = &sc->sc_deflims[index]; 2042 props = &sc->sc_defprops[index]; 2043 } 2044 switch (edata->units) { 2045 case ENVSYS_STEMP: 2046 dbcool_set_temp_limits(sc, index, limits, props); 2047 break; 2048 case ENVSYS_SVOLTS_DC: 2049 dbcool_set_volt_limits(sc, index, limits, props); 2050 break; 2051 case ENVSYS_SFANRPM: 2052 dbcool_set_fan_limits(sc, index, limits, props); 2053 2054 /* FALLTHROUGH */ 2055 default: 2056 break; 2057 } 2058 *props &= ~PROP_DRIVER_LIMITS; 2059 } 2060 2061 static void 2062 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2063 sysmon_envsys_lim_t *lims, uint32_t *props) 2064 { 2065 struct reg_list *reg = sc->sc_regs[idx]; 2066 int32_t limit; 2067 2068 if (*props & PROP_CRITMIN) { 2069 limit = lims->sel_critmin - 273150000; 2070 limit /= 1000000; 2071 if (sc->sc_temp_offset) { 2072 limit += sc->sc_temp_offset; 2073 if (limit < 0) 2074 limit = 0; 2075 else if (limit > 255) 2076 limit = 255; 2077 } else { 2078 if (limit < -127) 2079 limit = -127; 2080 else if (limit > 127) 2081 limit = 127; 2082 } 2083 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2084 (uint8_t)limit); 2085 } else if (*props & PROP_DRIVER_LIMITS) { 2086 if (sc->sc_temp_offset) 2087 limit = 0x00; 2088 else 2089 limit = 0x80; 2090 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2091 (uint8_t)limit); 2092 } 2093 2094 if (*props & PROP_CRITMAX) { 2095 limit = lims->sel_critmax - 273150000; 2096 limit /= 1000000; 2097 if (sc->sc_temp_offset) { 2098 limit += sc->sc_temp_offset; 2099 if (limit < 0) 2100 limit = 0; 2101 else if (limit > 255) 2102 limit = 255; 2103 } else { 2104 if (limit < -127) 2105 limit = -127; 2106 else if (limit > 127) 2107 limit = 127; 2108 } 2109 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2110 (uint8_t)limit); 2111 } else if (*props & PROP_DRIVER_LIMITS) { 2112 if (sc->sc_temp_offset) 2113 limit = 0xff; 2114 else 2115 limit = 0x7f; 2116 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2117 (uint8_t)limit); 2118 } 2119 } 2120 2121 static void 2122 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2123 sysmon_envsys_lim_t *lims, uint32_t *props) 2124 { 2125 struct reg_list *reg = sc->sc_regs[idx]; 2126 int64_t limit; 2127 int nom; 2128 2129 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2130 if (nom < 0) 2131 nom = dbcool_supply_voltage(sc); 2132 nom *= 1000000; /* scale for microvolts */ 2133 2134 if (*props & PROP_CRITMIN) { 2135 limit = lims->sel_critmin; 2136 limit *= 0xc0; 2137 limit /= nom; 2138 if (limit > 0xff) 2139 limit = 0xff; 2140 else if (limit < 0) 2141 limit = 0; 2142 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2143 } else if (*props & PROP_DRIVER_LIMITS) 2144 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2145 2146 if (*props & PROP_CRITMAX) { 2147 limit = lims->sel_critmax; 2148 limit *= 0xc0; 2149 limit /= nom; 2150 if (limit > 0xff) 2151 limit = 0xff; 2152 else if (limit < 0) 2153 limit = 0; 2154 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2155 } else if (*props & PROP_DRIVER_LIMITS) 2156 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2157 } 2158 2159 static void 2160 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2161 sysmon_envsys_lim_t *lims, uint32_t *props) 2162 { 2163 struct reg_list *reg = sc->sc_regs[idx]; 2164 int32_t limit, dividend; 2165 2166 if (*props & PROP_CRITMIN) { 2167 limit = lims->sel_critmin; 2168 if (limit == 0) 2169 limit = 0xffff; 2170 else { 2171 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2172 dividend = 11250 * 60; 2173 else 2174 dividend = 90000 * 60; 2175 limit = limit / dividend; 2176 if (limit > 0xffff) 2177 limit = 0xffff; 2178 } 2179 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2180 limit & 0xff); 2181 limit >>= 8; 2182 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2183 limit & 0xff); 2184 } else if (*props & PROP_DRIVER_LIMITS) { 2185 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2186 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2187 } 2188 } 2189 2190 MODULE(MODULE_CLASS_DRIVER, dbcool, "iic,sysmon_envsys"); 2191 2192 #ifdef _MODULE 2193 #include "ioconf.c" 2194 #endif 2195 2196 static int 2197 dbcool_modcmd(modcmd_t cmd, void *opaque) 2198 { 2199 int error = 0; 2200 #ifdef _MODULE 2201 static struct sysctllog *dbcool_sysctl_clog; 2202 #endif 2203 2204 switch (cmd) { 2205 case MODULE_CMD_INIT: 2206 #ifdef _MODULE 2207 error = config_init_component(cfdriver_ioconf_dbcool, 2208 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2209 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2210 #endif 2211 return error; 2212 case MODULE_CMD_FINI: 2213 #ifdef _MODULE 2214 error = config_fini_component(cfdriver_ioconf_dbcool, 2215 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2216 sysctl_teardown(&dbcool_sysctl_clog); 2217 #endif 2218 return error; 2219 default: 2220 return ENOTTY; 2221 } 2222 } 2223
Indexes created Mon Sep 22 10:09:38 GMT 2025