| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_renoir_ppt.c | 548 uint32_t *sclk_mask,
554 if (sclk_mask)
555 *sclk_mask = 0;
560 if(sclk_mask)
562 *sclk_mask = 3 - 1;
726 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:renoir_set_performance_level
742 &sclk_mask,
747 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
|
| amdgpu_navi10_ppt.c | 1419 uint32_t *sclk_mask,
1427 if (sclk_mask)
1428 *sclk_mask = 0;
1433 if(sclk_mask) {
1437 *sclk_mask = level_count - 1;
1768 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:navi10_set_performance_level
1786 &sclk_mask,
1791 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
|
| amdgpu_smu_v11_0.c | 1911 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:smu_v11_0_set_performance_level
1928 &sclk_mask,
1933 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 1588 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1595 *sclk_mask = 0;
1602 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1608 *sclk_mask = 0;
1612 *sclk_mask = gfx_dpm_table->count - 1;
1642 uint32_t sclk_mask = 0; local in function:vega12_dpm_force_dpm_level
1660 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1663 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
|
| amdgpu_vega20_hwmgr.c | 2484 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2491 *sclk_mask = 0;
2498 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2504 *sclk_mask = 0;
2508 *sclk_mask = gfx_dpm_table->count - 1;
2683 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:vega20_dpm_force_dpm_level
2702 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2705 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
|
| amdgpu_vega10_hwmgr.c | 4086 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4094 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4102 *sclk_mask = 0;
4110 *sclk_mask = 4;
4112 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4205 uint32_t sclk_mask = 0; local in function:vega10_dpm_force_dpm_level
4210 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4226 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4229 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
|
| amdgpu_smu7_hwmgr.c | 2735 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2766 *sclk_mask = count;
2771 *sclk_mask = 0;
2776 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2784 *sclk_mask = count;
2789 *sclk_mask = 0;
2794 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2813 uint32_t sclk_mask = 0; local in function:smu7_force_dpm_level
2818 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2834 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask)
[all...] |
