1 /* $NetBSD: gtsdmareg.h,v 1.6 2016/01/15 12:09:15 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gtsdmareg.h - register defines for GT-64260 SDMA 42 * 43 * creation Sun Apr 8 20:22:51 PDT 2001 cliff 44 */ 45 46 #ifndef _GTSDMAREG_H 47 #define _GTSDMAREG_H 48 49 #define GTSDMA_BASE(u) ((u) == 0 ? 0x4000 : 0x6000) 50 #define GTSDMA_SIZE 0x1000 51 52 /******************************************************************************* 53 * 54 * SDMA register address offsets relative to the base mapping 55 */ 56 #define SDMA_SDC 0x000 /* SDMA Configuration Register */ 57 #define SDMA_SDCM 0x008 /* SDMA Command Register */ 58 #define SDMA_SCRDP 0x810 /* SDMA Current RX Desc. Pointer */ 59 #define SDMA_SCTDP 0xc10 /* SDMA Current TX Desc. Pointer */ 60 #define SDMA_SFTDP 0xc14 /* SDMA First TX Desc. Pointer */ 61 62 #define SDMA_ICAUSE 0xb800 /* Interrupt Cause Register */ 63 #define SDMA_IMASK 0xb880 /* Interrupt Mask Register */ 64 65 66 /******************************************************************************* 67 * 68 * SDMA register values and bit definitions 69 */ 70 /* 71 * SDMA Configuration Register 72 */ 73 #define SDMA_SDC_RFT __BIT(0) /* RX FIFO Threshold */ 74 #define SDMA_SDC_SFM __BIT(1) /* Single Frame Mode */ 75 #define SDMA_SDC_RC_MASK __BITS(5,2) /* Re-TX count */ 76 #define SDMA_SDC_RC_SHIFT 2 77 #define SDMA_SDC_BLMR __BIT(6) /* RX Big=0 Lil=1 Endian mode */ 78 #define SDMA_SDC_BLMT __BIT(7) /* TX Big=0 Lil=1 Endian mode */ 79 #define SDMA_SDC_POVR __BIT(8) /* PCI Override */ 80 #define SDMA_SDC_RIFB __BIT(9) /* RX Intr on Frame boundaries */ 81 #define SDMA_SDC_RESa __BITS(11,10) 82 #define SDMA_SDC_BSZ_MASK __BITS(13,12) /* Maximum Burst Size */ 83 #define SDMA_SDC_BSZ_1x64 (0 << 12) /* 1 64 bit word */ 84 #define SDMA_SDC_BSZ_2x64 (1 << 12) /* 2 64 bit words */ 85 #define SDMA_SDC_BSZ_4x64 (2 << 12) /* 4 64 bit words */ 86 #define SDMA_SDC_BSZ_8x64 (3 << 12) /* 8 64 bit words */ 87 #define SDMA_SDC_RESb __BITS(31,14) 88 #define SDMA_SDC_RES (SDMA_SDC_RESa|SDMA_SDC_RESb) 89 /* 90 * SDMA Command Register 91 */ 92 #define SDMA_SDCM_RESa __BITS(6,0) 93 #define SDMA_SDCM_ERD __BIT(7) /* Enable RX DMA */ 94 #define SDMA_SDCM_RESb __BITS(14,8) 95 #define SDMA_SDCM_AR __BIT(15) /* Abort Receive */ 96 #define SDMA_SDCM_STD __BIT(16) /* Stop TX */ 97 #define SDMA_SDCM_RESc __BITS(22,17) 98 #define SDMA_SDCM_TXD __BIT(23) /* TX Demand */ 99 #define SDMA_SDCM_RESd __BITS(30,24) 100 #define SDMA_SDCM_AT __BIT(31) /* Abort TX */ 101 #define SDMA_SDCM_RES \ 102 (SDMA_SDCM_RESa|SDMA_SDCM_RESb|SDMA_SDCM_RESc|SDMA_SDCM_RESd) 103 /* 104 * SDMA Interrupt Cause and Mask Register bits 105 */ 106 #define U__(bits,u) ((bits) << (((u) % 2) * 8)) 107 #define SDMA_INTR_RXBUF(u) U__(__BIT(0),u) /* SDMA #0 Rx Buffer Return */ 108 #define SDMA_INTR_RXERR(u) U__(__BIT(1),u) /* SDMA #0 Rx Error */ 109 #define SDMA_INTR_TXBUF(u) U__(__BIT(2),u) /* SDMA #0 Tx Buffer Return */ 110 #define SDMA_INTR_TXEND(u) U__(__BIT(3),u) /* SDMA #0 Tx End */ 111 #define SDMA_INTR_RESa __BITS(7,4) 112 #define SDMA_INTR_RESb __BITS(31,12) 113 #define SDMA_INTR_RES (SDMA_INTR_RESa|SDMA_INTR_RESb) 114 #define SDMA_U_INTR_MASK(u) U__(__BITS(3,0),u) 115 116 117 /******************************************************************************* 118 * 119 * SDMA descriptor structure and definitions 120 */ 121 /* 122 * SDMA descriptor structure used for both TX and RX 123 * the `sdma_csr' and `sdma_cnt' fields differ for RX and TX 124 * `sdma_csr' varies depending on how it is tasked; 125 * see "gtmpscreg.h" for defines on SDMA descriptor CSR values 126 * for MPSC UART mode. Note that pointer fields are physical addrs. 127 */ 128 typedef struct sdma_desc { 129 uint32_t sdma_cnt; /* size (rx) or shadow (tx) and count */ 130 uint32_t sdma_csr; /* command/status */ 131 uint32_t sdma_next; /* next descriptor link */ 132 uint32_t sdma_bufp; /* buffer pointer */ 133 } sdma_desc_t; 134 135 #define SDMA_RX_CNT_BCNT_SHIFT 0 /* byte count */ 136 #define SDMA_RX_CNT_BCNT_MASK __BITS(15,0) /* " " */ 137 #define SDMA_RX_CNT_BUFSZ_SHIFT 16 /* buffer size */ 138 #define SDMA_RX_CNT_BUFSZNT_SIZE_MASK __BITS(31,19) /* " " */ 139 #define SDMA_RX_CNT_BUFP_MASK __BITS(31,3) /* buffer pointer */ 140 #define SDMA_RX_CNT_NEXT_MASK __BITS(31,4) /* next desc. pointer */ 141 142 #define SDMA_TX_CNT_SBC_SHIFT 0 /* shadow byte count */ 143 #define SDMA_TX_CNT_SBC_MASK __BITS(15,0) /* " " " */ 144 #define SDMA_TX_CNT_BCNT_SHIFT 16 /* byte count */ 145 #define SDMA_TX_CNT_BCNT_MASK __BITS(31,16 /* " " */ 146 #define SDMA_TX_CNT_NEXT_MASK __BITS(31,4) /* next desc. pointer */ 147 148 149 #endif /* _GTSDMAREG_H */ 150
Indexes created Sat Sep 20 22:09:52 GMT 2025