1 /* $NetBSD: amdgpu_sdma_v2_4.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_sdma_v2_4.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 29 30 #include <linux/delay.h> 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_trace.h" 37 #include "vi.h" 38 #include "vid.h" 39 40 #include "oss/oss_2_4_d.h" 41 #include "oss/oss_2_4_sh_mask.h" 42 43 #include "gmc/gmc_7_1_d.h" 44 #include "gmc/gmc_7_1_sh_mask.h" 45 46 #include "gca/gfx_8_0_d.h" 47 #include "gca/gfx_8_0_enum.h" 48 #include "gca/gfx_8_0_sh_mask.h" 49 50 #include "bif/bif_5_0_d.h" 51 #include "bif/bif_5_0_sh_mask.h" 52 53 #include "iceland_sdma_pkt_open.h" 54 55 #include "ivsrcid/ivsrcid_vislands30.h" 56 #include <linux/nbsd-namespace.h> 57 58 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 59 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 60 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 61 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 62 63 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); 65 66 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 67 { 68 SDMA0_REGISTER_OFFSET, 69 SDMA1_REGISTER_OFFSET 70 }; 71 72 static const u32 golden_settings_iceland_a11[] = 73 { 74 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 75 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 76 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 77 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 78 }; 79 80 static const u32 iceland_mgcg_cgcg_init[] = 81 { 82 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 83 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 84 }; 85 86 /* 87 * sDMA - System DMA 88 * Starting with CIK, the GPU has new asynchronous 89 * DMA engines. These engines are used for compute 90 * and gfx. There are two DMA engines (SDMA0, SDMA1) 91 * and each one supports 1 ring buffer used for gfx 92 * and 2 queues used for compute. 93 * 94 * The programming model is very similar to the CP 95 * (ring buffer, IBs, etc.), but sDMA has it's own 96 * packet format that is different from the PM4 format 97 * used by the CP. sDMA supports copying data, writing 98 * embedded data, solid fills, and a number of other 99 * things. It also has support for tiling/detiling of 100 * buffers. 101 */ 102 103 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 104 { 105 switch (adev->asic_type) { 106 case CHIP_TOPAZ: 107 amdgpu_device_program_register_sequence(adev, 108 iceland_mgcg_cgcg_init, 109 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 110 amdgpu_device_program_register_sequence(adev, 111 golden_settings_iceland_a11, 112 ARRAY_SIZE(golden_settings_iceland_a11)); 113 break; 114 default: 115 break; 116 } 117 } 118 119 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) 120 { 121 int i; 122 for (i = 0; i < adev->sdma.num_instances; i++) { 123 release_firmware(adev->sdma.instance[i].fw); 124 adev->sdma.instance[i].fw = NULL; 125 } 126 } 127 128 /** 129 * sdma_v2_4_init_microcode - load ucode images from disk 130 * 131 * @adev: amdgpu_device pointer 132 * 133 * Use the firmware interface to load the ucode images into 134 * the driver (not loaded into hw). 135 * Returns 0 on success, error on failure. 136 */ 137 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 138 { 139 const char *chip_name; 140 char fw_name[30]; 141 int err = 0, i; 142 struct amdgpu_firmware_info *info = NULL; 143 const struct common_firmware_header *header = NULL; 144 const struct sdma_firmware_header_v1_0 *hdr; 145 146 DRM_DEBUG("\n"); 147 148 switch (adev->asic_type) { 149 case CHIP_TOPAZ: 150 chip_name = "topaz"; 151 break; 152 default: BUG(); 153 } 154 155 for (i = 0; i < adev->sdma.num_instances; i++) { 156 if (i == 0) 157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 158 else 159 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 160 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 161 if (err) 162 goto out; 163 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 164 if (err) 165 goto out; 166 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 167 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 168 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 169 if (adev->sdma.instance[i].feature_version >= 20) 170 adev->sdma.instance[i].burst_nop = true; 171 172 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 173 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 174 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 175 info->fw = adev->sdma.instance[i].fw; 176 header = (const struct common_firmware_header *)info->fw->data; 177 adev->firmware.fw_size += 178 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 179 } 180 } 181 182 out: 183 if (err) { 184 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); 185 for (i = 0; i < adev->sdma.num_instances; i++) { 186 release_firmware(adev->sdma.instance[i].fw); 187 adev->sdma.instance[i].fw = NULL; 188 } 189 } 190 return err; 191 } 192 193 /** 194 * sdma_v2_4_ring_get_rptr - get the current read pointer 195 * 196 * @ring: amdgpu ring pointer 197 * 198 * Get the current rptr from the hardware (VI+). 199 */ 200 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 201 { 202 /* XXX check if swapping is necessary on BE */ 203 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 204 } 205 206 /** 207 * sdma_v2_4_ring_get_wptr - get the current write pointer 208 * 209 * @ring: amdgpu ring pointer 210 * 211 * Get the current wptr from the hardware (VI+). 212 */ 213 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 214 { 215 struct amdgpu_device *adev = ring->adev; 216 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 217 218 return wptr; 219 } 220 221 /** 222 * sdma_v2_4_ring_set_wptr - commit the write pointer 223 * 224 * @ring: amdgpu ring pointer 225 * 226 * Write the wptr back to the hardware (VI+). 227 */ 228 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 229 { 230 struct amdgpu_device *adev = ring->adev; 231 232 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); 233 } 234 235 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 236 { 237 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 238 int i; 239 240 for (i = 0; i < count; i++) 241 if (sdma && sdma->burst_nop && (i == 0)) 242 amdgpu_ring_write(ring, ring->funcs->nop | 243 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 244 else 245 amdgpu_ring_write(ring, ring->funcs->nop); 246 } 247 248 /** 249 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 250 * 251 * @ring: amdgpu ring pointer 252 * @ib: IB object to schedule 253 * 254 * Schedule an IB in the DMA ring (VI). 255 */ 256 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 257 struct amdgpu_job *job, 258 struct amdgpu_ib *ib, 259 uint32_t flags) 260 { 261 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 262 263 /* IB packet must end on a 8 DW boundary */ 264 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 265 266 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 267 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 268 /* base must be 32 byte aligned */ 269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 271 amdgpu_ring_write(ring, ib->length_dw); 272 amdgpu_ring_write(ring, 0); 273 amdgpu_ring_write(ring, 0); 274 275 } 276 277 /** 278 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 279 * 280 * @ring: amdgpu ring pointer 281 * 282 * Emit an hdp flush packet on the requested DMA ring. 283 */ 284 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 285 { 286 u32 ref_and_mask = 0; 287 288 if (ring->me == 0) 289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 290 else 291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 292 293 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 294 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 295 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 296 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 297 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 298 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 299 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 300 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 301 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 302 } 303 304 /** 305 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 306 * 307 * @ring: amdgpu ring pointer 308 * @fence: amdgpu fence object 309 * 310 * Add a DMA fence packet to the ring to write 311 * the fence seq number and DMA trap packet to generate 312 * an interrupt if needed (VI). 313 */ 314 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 315 unsigned flags) 316 { 317 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 318 /* write the fence */ 319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 320 amdgpu_ring_write(ring, lower_32_bits(addr)); 321 amdgpu_ring_write(ring, upper_32_bits(addr)); 322 amdgpu_ring_write(ring, lower_32_bits(seq)); 323 324 /* optionally write high bits as well */ 325 if (write64bit) { 326 addr += 4; 327 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 328 amdgpu_ring_write(ring, lower_32_bits(addr)); 329 amdgpu_ring_write(ring, upper_32_bits(addr)); 330 amdgpu_ring_write(ring, upper_32_bits(seq)); 331 } 332 333 /* generate an interrupt */ 334 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 335 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 336 } 337 338 /** 339 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 340 * 341 * @adev: amdgpu_device pointer 342 * 343 * Stop the gfx async dma ring buffers (VI). 344 */ 345 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 346 { 347 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 348 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 349 u32 rb_cntl, ib_cntl; 350 int i; 351 352 if ((adev->mman.buffer_funcs_ring == sdma0) || 353 (adev->mman.buffer_funcs_ring == sdma1)) 354 amdgpu_ttm_set_buffer_funcs_status(adev, false); 355 356 for (i = 0; i < adev->sdma.num_instances; i++) { 357 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 358 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 359 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 360 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 361 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 362 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 363 } 364 sdma0->sched.ready = false; 365 sdma1->sched.ready = false; 366 } 367 368 /** 369 * sdma_v2_4_rlc_stop - stop the compute async dma engines 370 * 371 * @adev: amdgpu_device pointer 372 * 373 * Stop the compute async dma queues (VI). 374 */ 375 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 376 { 377 /* XXX todo */ 378 } 379 380 /** 381 * sdma_v2_4_enable - stop the async dma engines 382 * 383 * @adev: amdgpu_device pointer 384 * @enable: enable/disable the DMA MEs. 385 * 386 * Halt or unhalt the async dma engines (VI). 387 */ 388 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 389 { 390 u32 f32_cntl; 391 int i; 392 393 if (!enable) { 394 sdma_v2_4_gfx_stop(adev); 395 sdma_v2_4_rlc_stop(adev); 396 } 397 398 for (i = 0; i < adev->sdma.num_instances; i++) { 399 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 400 if (enable) 401 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 402 else 403 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 404 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 405 } 406 } 407 408 /** 409 * sdma_v2_4_gfx_resume - setup and start the async dma engines 410 * 411 * @adev: amdgpu_device pointer 412 * 413 * Set up the gfx DMA ring buffers and enable them (VI). 414 * Returns 0 for success, error for failure. 415 */ 416 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 417 { 418 struct amdgpu_ring *ring; 419 u32 rb_cntl, ib_cntl; 420 u32 rb_bufsz; 421 u32 wb_offset; 422 int i, j, r; 423 424 for (i = 0; i < adev->sdma.num_instances; i++) { 425 ring = &adev->sdma.instance[i].ring; 426 wb_offset = (ring->rptr_offs * 4); 427 428 mutex_lock(&adev->srbm_mutex); 429 for (j = 0; j < 16; j++) { 430 vi_srbm_select(adev, 0, 0, 0, j); 431 /* SDMA GFX */ 432 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 433 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 434 } 435 vi_srbm_select(adev, 0, 0, 0, 0); 436 mutex_unlock(&adev->srbm_mutex); 437 438 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 439 adev->gfx.config.gb_addr_config & 0x70); 440 441 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 442 443 /* Set ring buffer size in dwords */ 444 rb_bufsz = order_base_2(ring->ring_size / 4); 445 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 447 #ifdef __BIG_ENDIAN 448 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 449 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 450 RPTR_WRITEBACK_SWAP_ENABLE, 1); 451 #endif 452 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 453 454 /* Initialize the ring buffer's read and write pointers */ 455 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 456 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 457 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 458 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 459 460 /* set the wb address whether it's enabled or not */ 461 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 462 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 463 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 464 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 465 466 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 467 468 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 469 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 470 471 ring->wptr = 0; 472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 473 474 /* enable DMA RB */ 475 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 476 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 477 478 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 479 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 480 #ifdef __BIG_ENDIAN 481 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 482 #endif 483 /* enable DMA IBs */ 484 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 485 486 ring->sched.ready = true; 487 } 488 489 sdma_v2_4_enable(adev, true); 490 for (i = 0; i < adev->sdma.num_instances; i++) { 491 ring = &adev->sdma.instance[i].ring; 492 r = amdgpu_ring_test_helper(ring); 493 if (r) 494 return r; 495 496 if (adev->mman.buffer_funcs_ring == ring) 497 amdgpu_ttm_set_buffer_funcs_status(adev, true); 498 } 499 500 return 0; 501 } 502 503 /** 504 * sdma_v2_4_rlc_resume - setup and start the async dma engines 505 * 506 * @adev: amdgpu_device pointer 507 * 508 * Set up the compute DMA queues and enable them (VI). 509 * Returns 0 for success, error for failure. 510 */ 511 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 512 { 513 /* XXX todo */ 514 return 0; 515 } 516 517 518 /** 519 * sdma_v2_4_start - setup and start the async dma engines 520 * 521 * @adev: amdgpu_device pointer 522 * 523 * Set up the DMA engines and enable them (VI). 524 * Returns 0 for success, error for failure. 525 */ 526 static int sdma_v2_4_start(struct amdgpu_device *adev) 527 { 528 int r; 529 530 /* halt the engine before programing */ 531 sdma_v2_4_enable(adev, false); 532 533 /* start the gfx rings and rlc compute queues */ 534 r = sdma_v2_4_gfx_resume(adev); 535 if (r) 536 return r; 537 r = sdma_v2_4_rlc_resume(adev); 538 if (r) 539 return r; 540 541 return 0; 542 } 543 544 /** 545 * sdma_v2_4_ring_test_ring - simple async dma engine test 546 * 547 * @ring: amdgpu_ring structure holding ring information 548 * 549 * Test the DMA engine by writing using it to write an 550 * value to memory. (VI). 551 * Returns 0 for success, error for failure. 552 */ 553 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 554 { 555 struct amdgpu_device *adev = ring->adev; 556 unsigned i; 557 unsigned index; 558 int r; 559 u32 tmp; 560 u64 gpu_addr; 561 562 r = amdgpu_device_wb_get(adev, &index); 563 if (r) 564 return r; 565 566 gpu_addr = adev->wb.gpu_addr + (index * 4); 567 tmp = 0xCAFEDEAD; 568 adev->wb.wb[index] = cpu_to_le32(tmp); 569 570 r = amdgpu_ring_alloc(ring, 5); 571 if (r) 572 goto error_free_wb; 573 574 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 575 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 576 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 577 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 578 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 579 amdgpu_ring_write(ring, 0xDEADBEEF); 580 amdgpu_ring_commit(ring); 581 582 for (i = 0; i < adev->usec_timeout; i++) { 583 tmp = le32_to_cpu(adev->wb.wb[index]); 584 if (tmp == 0xDEADBEEF) 585 break; 586 udelay(1); 587 } 588 589 if (i >= adev->usec_timeout) 590 r = -ETIMEDOUT; 591 592 error_free_wb: 593 amdgpu_device_wb_free(adev, index); 594 return r; 595 } 596 597 /** 598 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 599 * 600 * @ring: amdgpu_ring structure holding ring information 601 * 602 * Test a simple IB in the DMA ring (VI). 603 * Returns 0 on success, error on failure. 604 */ 605 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) 606 { 607 struct amdgpu_device *adev = ring->adev; 608 struct amdgpu_ib ib; 609 struct dma_fence *f = NULL; 610 unsigned index; 611 u32 tmp = 0; 612 u64 gpu_addr; 613 long r; 614 615 r = amdgpu_device_wb_get(adev, &index); 616 if (r) 617 return r; 618 619 gpu_addr = adev->wb.gpu_addr + (index * 4); 620 tmp = 0xCAFEDEAD; 621 adev->wb.wb[index] = cpu_to_le32(tmp); 622 memset(&ib, 0, sizeof(ib)); 623 r = amdgpu_ib_get(adev, NULL, 256, &ib); 624 if (r) 625 goto err0; 626 627 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 628 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 629 ib.ptr[1] = lower_32_bits(gpu_addr); 630 ib.ptr[2] = upper_32_bits(gpu_addr); 631 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 632 ib.ptr[4] = 0xDEADBEEF; 633 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 634 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 635 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 636 ib.length_dw = 8; 637 638 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 639 if (r) 640 goto err1; 641 642 r = dma_fence_wait_timeout(f, false, timeout); 643 if (r == 0) { 644 r = -ETIMEDOUT; 645 goto err1; 646 } else if (r < 0) { 647 goto err1; 648 } 649 tmp = le32_to_cpu(adev->wb.wb[index]); 650 if (tmp == 0xDEADBEEF) 651 r = 0; 652 else 653 r = -EINVAL; 654 655 err1: 656 amdgpu_ib_free(adev, &ib, NULL); 657 dma_fence_put(f); 658 err0: 659 amdgpu_device_wb_free(adev, index); 660 return r; 661 } 662 663 /** 664 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 665 * 666 * @ib: indirect buffer to fill with commands 667 * @pe: addr of the page entry 668 * @src: src addr to copy from 669 * @count: number of page entries to update 670 * 671 * Update PTEs by copying them from the GART using sDMA (CIK). 672 */ 673 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 674 uint64_t pe, uint64_t src, 675 unsigned count) 676 { 677 unsigned bytes = count * 8; 678 679 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 680 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 681 ib->ptr[ib->length_dw++] = bytes; 682 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 683 ib->ptr[ib->length_dw++] = lower_32_bits(src); 684 ib->ptr[ib->length_dw++] = upper_32_bits(src); 685 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 686 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 687 } 688 689 /** 690 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 691 * 692 * @ib: indirect buffer to fill with commands 693 * @pe: addr of the page entry 694 * @value: dst addr to write into pe 695 * @count: number of page entries to update 696 * @incr: increase next addr by incr bytes 697 * 698 * Update PTEs by writing them manually using sDMA (CIK). 699 */ 700 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 701 uint64_t value, unsigned count, 702 uint32_t incr) 703 { 704 unsigned ndw = count * 2; 705 706 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 707 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 708 ib->ptr[ib->length_dw++] = pe; 709 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 710 ib->ptr[ib->length_dw++] = ndw; 711 for (; ndw > 0; ndw -= 2) { 712 ib->ptr[ib->length_dw++] = lower_32_bits(value); 713 ib->ptr[ib->length_dw++] = upper_32_bits(value); 714 value += incr; 715 } 716 } 717 718 /** 719 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 720 * 721 * @ib: indirect buffer to fill with commands 722 * @pe: addr of the page entry 723 * @addr: dst addr to write into pe 724 * @count: number of page entries to update 725 * @incr: increase next addr by incr bytes 726 * @flags: access flags 727 * 728 * Update the page tables using sDMA (CIK). 729 */ 730 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 731 uint64_t addr, unsigned count, 732 uint32_t incr, uint64_t flags) 733 { 734 /* for physically contiguous pages (vram) */ 735 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 736 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 737 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 738 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 739 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 740 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 741 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 742 ib->ptr[ib->length_dw++] = incr; /* increment size */ 743 ib->ptr[ib->length_dw++] = 0; 744 ib->ptr[ib->length_dw++] = count; /* number of entries */ 745 } 746 747 /** 748 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw 749 * 750 * @ib: indirect buffer to fill with padding 751 * 752 */ 753 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 754 { 755 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 756 u32 pad_count; 757 int i; 758 759 pad_count = (-ib->length_dw) & 7; 760 for (i = 0; i < pad_count; i++) 761 if (sdma && sdma->burst_nop && (i == 0)) 762 ib->ptr[ib->length_dw++] = 763 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 764 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 765 else 766 ib->ptr[ib->length_dw++] = 767 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 768 } 769 770 /** 771 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline 772 * 773 * @ring: amdgpu_ring pointer 774 * 775 * Make sure all previous operations are completed (CIK). 776 */ 777 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 778 { 779 uint32_t seq = ring->fence_drv.sync_seq; 780 uint64_t addr = ring->fence_drv.gpu_addr; 781 782 /* wait for idle */ 783 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 784 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 785 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 786 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 787 amdgpu_ring_write(ring, addr & 0xfffffffc); 788 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 789 amdgpu_ring_write(ring, seq); /* reference */ 790 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 791 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 792 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 793 } 794 795 /** 796 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 797 * 798 * @ring: amdgpu_ring pointer 799 * @vm: amdgpu_vm pointer 800 * 801 * Update the page table base and flush the VM TLB 802 * using sDMA (VI). 803 */ 804 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 805 unsigned vmid, uint64_t pd_addr) 806 { 807 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 808 809 /* wait for flush */ 810 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 811 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 812 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 813 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 814 amdgpu_ring_write(ring, 0); 815 amdgpu_ring_write(ring, 0); /* reference */ 816 amdgpu_ring_write(ring, 0); /* mask */ 817 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 818 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 819 } 820 821 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, 822 uint32_t reg, uint32_t val) 823 { 824 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 825 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 826 amdgpu_ring_write(ring, reg); 827 amdgpu_ring_write(ring, val); 828 } 829 830 static int sdma_v2_4_early_init(void *handle) 831 { 832 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 833 834 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 835 836 sdma_v2_4_set_ring_funcs(adev); 837 sdma_v2_4_set_buffer_funcs(adev); 838 sdma_v2_4_set_vm_pte_funcs(adev); 839 sdma_v2_4_set_irq_funcs(adev); 840 841 return 0; 842 } 843 844 static int sdma_v2_4_sw_init(void *handle) 845 { 846 struct amdgpu_ring *ring; 847 int r, i; 848 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 849 850 /* SDMA trap event */ 851 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 852 &adev->sdma.trap_irq); 853 if (r) 854 return r; 855 856 /* SDMA Privileged inst */ 857 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 858 &adev->sdma.illegal_inst_irq); 859 if (r) 860 return r; 861 862 /* SDMA Privileged inst */ 863 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 864 &adev->sdma.illegal_inst_irq); 865 if (r) 866 return r; 867 868 r = sdma_v2_4_init_microcode(adev); 869 if (r) { 870 DRM_ERROR("Failed to load sdma firmware!\n"); 871 return r; 872 } 873 874 for (i = 0; i < adev->sdma.num_instances; i++) { 875 ring = &adev->sdma.instance[i].ring; 876 ring->ring_obj = NULL; 877 ring->use_doorbell = false; 878 snprintf(ring->name, sizeof ring->name, "sdma%d", i); 879 r = amdgpu_ring_init(adev, ring, 1024, 880 &adev->sdma.trap_irq, 881 (i == 0) ? 882 AMDGPU_SDMA_IRQ_INSTANCE0 : 883 AMDGPU_SDMA_IRQ_INSTANCE1); 884 if (r) 885 return r; 886 } 887 888 return r; 889 } 890 891 static int sdma_v2_4_sw_fini(void *handle) 892 { 893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 894 int i; 895 896 for (i = 0; i < adev->sdma.num_instances; i++) 897 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 898 899 sdma_v2_4_free_microcode(adev); 900 return 0; 901 } 902 903 static int sdma_v2_4_hw_init(void *handle) 904 { 905 int r; 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907 908 sdma_v2_4_init_golden_registers(adev); 909 910 r = sdma_v2_4_start(adev); 911 if (r) 912 return r; 913 914 return r; 915 } 916 917 static int sdma_v2_4_hw_fini(void *handle) 918 { 919 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 920 921 sdma_v2_4_enable(adev, false); 922 923 return 0; 924 } 925 926 static int sdma_v2_4_suspend(void *handle) 927 { 928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 929 930 return sdma_v2_4_hw_fini(adev); 931 } 932 933 static int sdma_v2_4_resume(void *handle) 934 { 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 936 937 return sdma_v2_4_hw_init(adev); 938 } 939 940 static bool sdma_v2_4_is_idle(void *handle) 941 { 942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 943 u32 tmp = RREG32(mmSRBM_STATUS2); 944 945 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 946 SRBM_STATUS2__SDMA1_BUSY_MASK)) 947 return false; 948 949 return true; 950 } 951 952 static int sdma_v2_4_wait_for_idle(void *handle) 953 { 954 unsigned i; 955 u32 tmp; 956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 957 958 for (i = 0; i < adev->usec_timeout; i++) { 959 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 960 SRBM_STATUS2__SDMA1_BUSY_MASK); 961 962 if (!tmp) 963 return 0; 964 udelay(1); 965 } 966 return -ETIMEDOUT; 967 } 968 969 static int sdma_v2_4_soft_reset(void *handle) 970 { 971 u32 srbm_soft_reset = 0; 972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 973 u32 tmp = RREG32(mmSRBM_STATUS2); 974 975 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 976 /* sdma0 */ 977 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 978 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 979 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 980 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 981 } 982 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 983 /* sdma1 */ 984 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 985 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 986 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 987 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 988 } 989 990 if (srbm_soft_reset) { 991 tmp = RREG32(mmSRBM_SOFT_RESET); 992 tmp |= srbm_soft_reset; 993 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 994 WREG32(mmSRBM_SOFT_RESET, tmp); 995 tmp = RREG32(mmSRBM_SOFT_RESET); 996 997 udelay(50); 998 999 tmp &= ~srbm_soft_reset; 1000 WREG32(mmSRBM_SOFT_RESET, tmp); 1001 tmp = RREG32(mmSRBM_SOFT_RESET); 1002 1003 /* Wait a little for things to settle down */ 1004 udelay(50); 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 1011 struct amdgpu_irq_src *src, 1012 unsigned type, 1013 enum amdgpu_interrupt_state state) 1014 { 1015 u32 sdma_cntl; 1016 1017 switch (type) { 1018 case AMDGPU_SDMA_IRQ_INSTANCE0: 1019 switch (state) { 1020 case AMDGPU_IRQ_STATE_DISABLE: 1021 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1022 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1023 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1024 break; 1025 case AMDGPU_IRQ_STATE_ENABLE: 1026 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1027 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1028 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1029 break; 1030 default: 1031 break; 1032 } 1033 break; 1034 case AMDGPU_SDMA_IRQ_INSTANCE1: 1035 switch (state) { 1036 case AMDGPU_IRQ_STATE_DISABLE: 1037 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1038 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1039 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1040 break; 1041 case AMDGPU_IRQ_STATE_ENABLE: 1042 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1043 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1044 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1045 break; 1046 default: 1047 break; 1048 } 1049 break; 1050 default: 1051 break; 1052 } 1053 return 0; 1054 } 1055 1056 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1057 struct amdgpu_irq_src *source, 1058 struct amdgpu_iv_entry *entry) 1059 { 1060 u8 instance_id, queue_id; 1061 1062 instance_id = (entry->ring_id & 0x3) >> 0; 1063 queue_id = (entry->ring_id & 0xc) >> 2; 1064 DRM_DEBUG("IH: SDMA trap\n"); 1065 switch (instance_id) { 1066 case 0: 1067 switch (queue_id) { 1068 case 0: 1069 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1070 break; 1071 case 1: 1072 /* XXX compute */ 1073 break; 1074 case 2: 1075 /* XXX compute */ 1076 break; 1077 } 1078 break; 1079 case 1: 1080 switch (queue_id) { 1081 case 0: 1082 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1083 break; 1084 case 1: 1085 /* XXX compute */ 1086 break; 1087 case 2: 1088 /* XXX compute */ 1089 break; 1090 } 1091 break; 1092 } 1093 return 0; 1094 } 1095 1096 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1097 struct amdgpu_irq_src *source, 1098 struct amdgpu_iv_entry *entry) 1099 { 1100 u8 instance_id, queue_id; 1101 1102 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1103 instance_id = (entry->ring_id & 0x3) >> 0; 1104 queue_id = (entry->ring_id & 0xc) >> 2; 1105 1106 if (instance_id <= 1 && queue_id == 0) 1107 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1108 return 0; 1109 } 1110 1111 static int sdma_v2_4_set_clockgating_state(void *handle, 1112 enum amd_clockgating_state state) 1113 { 1114 /* XXX handled via the smc on VI */ 1115 return 0; 1116 } 1117 1118 static int sdma_v2_4_set_powergating_state(void *handle, 1119 enum amd_powergating_state state) 1120 { 1121 return 0; 1122 } 1123 1124 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1125 .name = "sdma_v2_4", 1126 .early_init = sdma_v2_4_early_init, 1127 .late_init = NULL, 1128 .sw_init = sdma_v2_4_sw_init, 1129 .sw_fini = sdma_v2_4_sw_fini, 1130 .hw_init = sdma_v2_4_hw_init, 1131 .hw_fini = sdma_v2_4_hw_fini, 1132 .suspend = sdma_v2_4_suspend, 1133 .resume = sdma_v2_4_resume, 1134 .is_idle = sdma_v2_4_is_idle, 1135 .wait_for_idle = sdma_v2_4_wait_for_idle, 1136 .soft_reset = sdma_v2_4_soft_reset, 1137 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1138 .set_powergating_state = sdma_v2_4_set_powergating_state, 1139 }; 1140 1141 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1142 .type = AMDGPU_RING_TYPE_SDMA, 1143 .align_mask = 0xf, 1144 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1145 .support_64bit_ptrs = false, 1146 .get_rptr = sdma_v2_4_ring_get_rptr, 1147 .get_wptr = sdma_v2_4_ring_get_wptr, 1148 .set_wptr = sdma_v2_4_ring_set_wptr, 1149 .emit_frame_size = 1150 6 + /* sdma_v2_4_ring_emit_hdp_flush */ 1151 3 + /* hdp invalidate */ 1152 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ 1153 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ 1154 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ 1155 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ 1156 .emit_ib = sdma_v2_4_ring_emit_ib, 1157 .emit_fence = sdma_v2_4_ring_emit_fence, 1158 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, 1159 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1160 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1161 .test_ring = sdma_v2_4_ring_test_ring, 1162 .test_ib = sdma_v2_4_ring_test_ib, 1163 .insert_nop = sdma_v2_4_ring_insert_nop, 1164 .pad_ib = sdma_v2_4_ring_pad_ib, 1165 .emit_wreg = sdma_v2_4_ring_emit_wreg, 1166 }; 1167 1168 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1169 { 1170 int i; 1171 1172 for (i = 0; i < adev->sdma.num_instances; i++) { 1173 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; 1174 adev->sdma.instance[i].ring.me = i; 1175 } 1176 } 1177 1178 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1179 .set = sdma_v2_4_set_trap_irq_state, 1180 .process = sdma_v2_4_process_trap_irq, 1181 }; 1182 1183 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1184 .process = sdma_v2_4_process_illegal_inst_irq, 1185 }; 1186 1187 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1188 { 1189 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1190 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1191 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1192 } 1193 1194 /** 1195 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1196 * 1197 * @ring: amdgpu_ring structure holding ring information 1198 * @src_offset: src GPU address 1199 * @dst_offset: dst GPU address 1200 * @byte_count: number of bytes to xfer 1201 * 1202 * Copy GPU buffers using the DMA engine (VI). 1203 * Used by the amdgpu ttm implementation to move pages if 1204 * registered as the asic copy callback. 1205 */ 1206 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, 1207 uint64_t src_offset, 1208 uint64_t dst_offset, 1209 uint32_t byte_count) 1210 { 1211 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1212 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1213 ib->ptr[ib->length_dw++] = byte_count; 1214 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1215 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1216 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1217 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1218 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1219 } 1220 1221 /** 1222 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1223 * 1224 * @ring: amdgpu_ring structure holding ring information 1225 * @src_data: value to write to buffer 1226 * @dst_offset: dst GPU address 1227 * @byte_count: number of bytes to xfer 1228 * 1229 * Fill GPU buffers using the DMA engine (VI). 1230 */ 1231 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, 1232 uint32_t src_data, 1233 uint64_t dst_offset, 1234 uint32_t byte_count) 1235 { 1236 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1237 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1238 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1239 ib->ptr[ib->length_dw++] = src_data; 1240 ib->ptr[ib->length_dw++] = byte_count; 1241 } 1242 1243 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1244 .copy_max_bytes = 0x1fffff, 1245 .copy_num_dw = 7, 1246 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1247 1248 .fill_max_bytes = 0x1fffff, 1249 .fill_num_dw = 7, 1250 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1251 }; 1252 1253 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1254 { 1255 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1256 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1257 } 1258 1259 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1260 .copy_pte_num_dw = 7, 1261 .copy_pte = sdma_v2_4_vm_copy_pte, 1262 1263 .write_pte = sdma_v2_4_vm_write_pte, 1264 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1265 }; 1266 1267 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1268 { 1269 unsigned i; 1270 1271 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1272 for (i = 0; i < adev->sdma.num_instances; i++) { 1273 adev->vm_manager.vm_pte_scheds[i] = 1274 &adev->sdma.instance[i].ring.sched; 1275 } 1276 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1277 } 1278 1279 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = 1280 { 1281 .type = AMD_IP_BLOCK_TYPE_SDMA, 1282 .major = 2, 1283 .minor = 4, 1284 .rev = 0, 1285 .funcs = &sdma_v2_4_ip_funcs, 1286 }; 1287
Indexes created Thu Sep 25 16:09:42 GMT 2025