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      1 /*	$NetBSD: smu7_smumgr.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2015 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef _SMU7_SMUMANAGER_H
     27 #define _SMU7_SMUMANAGER_H
     28 
     29 
     30 #include <pp_endian.h>
     31 
     32 #define SMC_RAM_END 0x40000
     33 
     34 struct smu7_buffer_entry {
     35 	uint32_t data_size;
     36 	uint64_t mc_addr;
     37 	void *kaddr;
     38 	struct amdgpu_bo *handle;
     39 };
     40 
     41 struct smu7_smumgr {
     42 	struct smu7_buffer_entry smu_buffer;
     43 	struct smu7_buffer_entry header_buffer;
     44 	struct SMU_DRAMData_TOC *toc;
     45 
     46 	uint32_t                             soft_regs_start;
     47 	uint32_t                             dpm_table_start;
     48 	uint32_t                             mc_reg_table_start;
     49 	uint32_t                             fan_table_start;
     50 	uint32_t                             arb_table_start;
     51 	uint32_t                             ulv_setting_starts;
     52 	uint8_t                              security_hard_key;
     53 	uint32_t                             acpi_optimization;
     54 	uint32_t                             avfs_btc_param;
     55 };
     56 
     57 
     58 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
     59 				uint32_t *dest, uint32_t byte_count, uint32_t limit);
     60 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
     61 			const uint8_t *src, uint32_t byte_count, uint32_t limit);
     62 int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
     63 bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
     64 int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
     65 int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
     66 int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
     67 						uint32_t parameter);
     68 int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
     69 						uint16_t msg, uint32_t parameter);
     70 int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
     71 
     72 enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
     73 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
     74 						uint32_t *value, uint32_t limit);
     75 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
     76 						uint32_t value, uint32_t limit);
     77 
     78 int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
     79 int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
     80 int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
     81 int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
     82 int smu7_init(struct pp_hwmgr *hwmgr);
     83 int smu7_smu_fini(struct pp_hwmgr *hwmgr);
     84 
     85 int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr);
     86 
     87 #endif
     88