1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print 12 /// the PAL metadata. 13 // 14 //===----------------------------------------------------------------------===// 15 // 16 17 #include "AMDGPUPALMetadata.h" 18 #include "AMDGPUPTNote.h" 19 #include "SIDefines.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/IR/Constants.h" 23 #include "llvm/IR/Module.h" 24 #include "llvm/Support/AMDGPUMetadata.h" 25 #include "llvm/Support/EndianStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 // Read the PAL metadata from IR metadata, where it was put by the frontend. 31 void AMDGPUPALMetadata::readFromIR(Module &M) { 32 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack"); 33 if (NamedMD && NamedMD->getNumOperands()) { 34 // This is the new msgpack format for metadata. It is a NamedMD containing 35 // an MDTuple containing an MDString containing the msgpack data. 36 BlobType = ELF::NT_AMDGPU_METADATA; 37 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 38 if (MDN && MDN->getNumOperands()) { 39 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0))) 40 setFromMsgPackBlob(MDS->getString()); 41 } 42 return; 43 } 44 BlobType = ELF::NT_AMD_PAL_METADATA; 45 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata"); 46 if (!NamedMD || !NamedMD->getNumOperands()) { 47 // Emit msgpack metadata by default 48 BlobType = ELF::NT_AMDGPU_METADATA; 49 return; 50 } 51 // This is the old reg=value pair format for metadata. It is a NamedMD 52 // containing an MDTuple containing a number of MDNodes each of which is an 53 // integer value, and each two integer values forms a key=value pair that we 54 // store as Registers[key]=value in the map. 55 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 56 if (!Tuple) 57 return; 58 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { 59 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I)); 60 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1)); 61 if (!Key || !Val) 62 continue; 63 setRegister(Key->getZExtValue(), Val->getZExtValue()); 64 } 65 } 66 67 // Set PAL metadata from a binary blob from the applicable .note record. 68 // Returns false if bad format. Blob must remain valid for the lifetime of the 69 // Metadata. 70 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) { 71 BlobType = Type; 72 if (Type == ELF::NT_AMD_PAL_METADATA) 73 return setFromLegacyBlob(Blob); 74 return setFromMsgPackBlob(Blob); 75 } 76 77 // Set PAL metadata from legacy (array of key=value pairs) blob. 78 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) { 79 auto Data = reinterpret_cast<const uint32_t *>(Blob.data()); 80 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I) 81 setRegister(Data[I * 2], Data[I * 2 + 1]); 82 return true; 83 } 84 85 // Set PAL metadata from msgpack blob. 86 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) { 87 msgpack::Reader Reader(Blob); 88 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false); 89 } 90 91 // Given the calling convention, calculate the register number for rsrc1. In 92 // principle the register number could change in future hardware, but we know 93 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so 94 // we can use fixed values. 95 static unsigned getRsrc1Reg(CallingConv::ID CC) { 96 switch (CC) { 97 default: 98 return PALMD::R_2E12_COMPUTE_PGM_RSRC1; 99 case CallingConv::AMDGPU_LS: 100 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS; 101 case CallingConv::AMDGPU_HS: 102 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS; 103 case CallingConv::AMDGPU_ES: 104 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES; 105 case CallingConv::AMDGPU_GS: 106 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS; 107 case CallingConv::AMDGPU_VS: 108 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS; 109 case CallingConv::AMDGPU_PS: 110 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS; 111 } 112 } 113 114 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used 115 // with a constant offset to access any non-register shader-specific PAL 116 // metadata key. 117 static unsigned getScratchSizeKey(CallingConv::ID CC) { 118 switch (CC) { 119 case CallingConv::AMDGPU_PS: 120 return PALMD::Key::PS_SCRATCH_SIZE; 121 case CallingConv::AMDGPU_VS: 122 return PALMD::Key::VS_SCRATCH_SIZE; 123 case CallingConv::AMDGPU_GS: 124 return PALMD::Key::GS_SCRATCH_SIZE; 125 case CallingConv::AMDGPU_ES: 126 return PALMD::Key::ES_SCRATCH_SIZE; 127 case CallingConv::AMDGPU_HS: 128 return PALMD::Key::HS_SCRATCH_SIZE; 129 case CallingConv::AMDGPU_LS: 130 return PALMD::Key::LS_SCRATCH_SIZE; 131 default: 132 return PALMD::Key::CS_SCRATCH_SIZE; 133 } 134 } 135 136 // Set the rsrc1 register in the metadata for a particular shader stage. 137 // In fact this ORs the value into any previous setting of the register. 138 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { 139 setRegister(getRsrc1Reg(CC), Val); 140 } 141 142 // Set the rsrc2 register in the metadata for a particular shader stage. 143 // In fact this ORs the value into any previous setting of the register. 144 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { 145 setRegister(getRsrc1Reg(CC) + 1, Val); 146 } 147 148 // Set the SPI_PS_INPUT_ENA register in the metadata. 149 // In fact this ORs the value into any previous setting of the register. 150 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) { 151 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val); 152 } 153 154 // Set the SPI_PS_INPUT_ADDR register in the metadata. 155 // In fact this ORs the value into any previous setting of the register. 156 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) { 157 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val); 158 } 159 160 // Get a register from the metadata, or 0 if not currently set. 161 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { 162 auto Regs = getRegisters(); 163 auto It = Regs.find(MsgPackDoc.getNode(Reg)); 164 if (It == Regs.end()) 165 return 0; 166 auto N = It->second; 167 if (N.getKind() != msgpack::Type::UInt) 168 return 0; 169 return N.getUInt(); 170 } 171 172 // Set a register in the metadata. 173 // In fact this ORs the value into any previous setting of the register. 174 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) { 175 if (!isLegacy()) { 176 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 177 // is a PAL ABI pseudo-register in the old non-MsgPack format. 178 if (Reg >= 0x10000000) 179 return; 180 } 181 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 182 if (N.getKind() == msgpack::Type::UInt) 183 Val |= N.getUInt(); 184 N = N.getDocument()->getNode(Val); 185 } 186 187 // Set the entry point name for one shader. 188 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) { 189 if (isLegacy()) 190 return; 191 // Msgpack format. 192 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true); 193 } 194 195 // Set the number of used vgprs in the metadata. This is an optional 196 // advisory record for logging etc; wave dispatch actually uses the rsrc1 197 // register for the shader stage to determine the number of vgprs to 198 // allocate. 199 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) { 200 if (isLegacy()) { 201 // Old non-msgpack format. 202 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 203 PALMD::Key::VS_NUM_USED_VGPRS - 204 PALMD::Key::VS_SCRATCH_SIZE; 205 setRegister(NumUsedVgprsKey, Val); 206 return; 207 } 208 // Msgpack format. 209 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); 210 } 211 212 // Set the number of used sgprs in the metadata. This is an optional advisory 213 // record for logging etc; wave dispatch actually uses the rsrc1 register for 214 // the shader stage to determine the number of sgprs to allocate. 215 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) { 216 if (isLegacy()) { 217 // Old non-msgpack format. 218 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 219 PALMD::Key::VS_NUM_USED_SGPRS - 220 PALMD::Key::VS_SCRATCH_SIZE; 221 setRegister(NumUsedSgprsKey, Val); 222 return; 223 } 224 // Msgpack format. 225 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); 226 } 227 228 // Set the scratch size in the metadata. 229 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { 230 if (isLegacy()) { 231 // Old non-msgpack format. 232 setRegister(getScratchSizeKey(CC), Val); 233 return; 234 } 235 // Msgpack format. 236 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); 237 } 238 239 // Set the stack frame size of a function in the metadata. 240 void AMDGPUPALMetadata::setFunctionScratchSize(const MachineFunction &MF, 241 unsigned Val) { 242 auto Node = getShaderFunction(MF.getFunction().getName()); 243 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val); 244 } 245 246 // Set the hardware register bit in PAL metadata to enable wave32 on the 247 // shader of the given calling convention. 248 void AMDGPUPALMetadata::setWave32(unsigned CC) { 249 switch (CC) { 250 case CallingConv::AMDGPU_HS: 251 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1)); 252 break; 253 case CallingConv::AMDGPU_GS: 254 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1)); 255 break; 256 case CallingConv::AMDGPU_VS: 257 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1)); 258 break; 259 case CallingConv::AMDGPU_PS: 260 setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1)); 261 break; 262 case CallingConv::AMDGPU_CS: 263 setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, 264 S_00B800_CS_W32_EN(1)); 265 break; 266 } 267 } 268 269 // Convert a register number to name, for display by toString(). 270 // Returns nullptr if none. 271 static const char *getRegisterName(unsigned RegNum) { 272 // Table of registers. 273 static const struct RegInfo { 274 unsigned Num; 275 const char *Name; 276 } RegInfoTable[] = { 277 // Registers that code generation sets/modifies metadata for. 278 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"}, 279 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"}, 280 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"}, 281 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"}, 282 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"}, 283 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"}, 284 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"}, 285 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, 286 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, 287 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, 288 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"}, 289 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, 290 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, 291 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, 292 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, 293 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, 294 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, 295 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"}, 296 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"}, 297 298 // Registers not known to code generation. 299 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, 300 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"}, 301 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"}, 302 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"}, 303 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"}, 304 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"}, 305 306 {0xa1c3, "SPI_SHADER_POS_FORMAT"}, 307 {0xa1b1, "SPI_VS_OUT_CONFIG"}, 308 {0xa207, "PA_CL_VS_OUT_CNTL"}, 309 {0xa204, "PA_CL_CLIP_CNTL"}, 310 {0xa206, "PA_CL_VTE_CNTL"}, 311 {0xa2f9, "PA_SU_VTX_CNTL"}, 312 {0xa293, "PA_SC_MODE_CNTL_1"}, 313 {0xa2a1, "VGT_PRIMITIVEID_EN"}, 314 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"}, 315 {0x2e18, "COMPUTE_TMPRING_SIZE"}, 316 {0xa1b5, "SPI_INTERP_CONTROL_0"}, 317 {0xa1ba, "SPI_TMPRING_SIZE"}, 318 {0xa1c4, "SPI_SHADER_Z_FORMAT"}, 319 {0xa1c5, "SPI_SHADER_COL_FORMAT"}, 320 {0xa203, "DB_SHADER_CONTROL"}, 321 {0xa08f, "CB_SHADER_MASK"}, 322 {0xa191, "SPI_PS_INPUT_CNTL_0"}, 323 {0xa192, "SPI_PS_INPUT_CNTL_1"}, 324 {0xa193, "SPI_PS_INPUT_CNTL_2"}, 325 {0xa194, "SPI_PS_INPUT_CNTL_3"}, 326 {0xa195, "SPI_PS_INPUT_CNTL_4"}, 327 {0xa196, "SPI_PS_INPUT_CNTL_5"}, 328 {0xa197, "SPI_PS_INPUT_CNTL_6"}, 329 {0xa198, "SPI_PS_INPUT_CNTL_7"}, 330 {0xa199, "SPI_PS_INPUT_CNTL_8"}, 331 {0xa19a, "SPI_PS_INPUT_CNTL_9"}, 332 {0xa19b, "SPI_PS_INPUT_CNTL_10"}, 333 {0xa19c, "SPI_PS_INPUT_CNTL_11"}, 334 {0xa19d, "SPI_PS_INPUT_CNTL_12"}, 335 {0xa19e, "SPI_PS_INPUT_CNTL_13"}, 336 {0xa19f, "SPI_PS_INPUT_CNTL_14"}, 337 {0xa1a0, "SPI_PS_INPUT_CNTL_15"}, 338 {0xa1a1, "SPI_PS_INPUT_CNTL_16"}, 339 {0xa1a2, "SPI_PS_INPUT_CNTL_17"}, 340 {0xa1a3, "SPI_PS_INPUT_CNTL_18"}, 341 {0xa1a4, "SPI_PS_INPUT_CNTL_19"}, 342 {0xa1a5, "SPI_PS_INPUT_CNTL_20"}, 343 {0xa1a6, "SPI_PS_INPUT_CNTL_21"}, 344 {0xa1a7, "SPI_PS_INPUT_CNTL_22"}, 345 {0xa1a8, "SPI_PS_INPUT_CNTL_23"}, 346 {0xa1a9, "SPI_PS_INPUT_CNTL_24"}, 347 {0xa1aa, "SPI_PS_INPUT_CNTL_25"}, 348 {0xa1ab, "SPI_PS_INPUT_CNTL_26"}, 349 {0xa1ac, "SPI_PS_INPUT_CNTL_27"}, 350 {0xa1ad, "SPI_PS_INPUT_CNTL_28"}, 351 {0xa1ae, "SPI_PS_INPUT_CNTL_29"}, 352 {0xa1af, "SPI_PS_INPUT_CNTL_30"}, 353 {0xa1b0, "SPI_PS_INPUT_CNTL_31"}, 354 355 {0xa2ce, "VGT_GS_MAX_VERT_OUT"}, 356 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"}, 357 {0xa290, "VGT_GS_MODE"}, 358 {0xa291, "VGT_GS_ONCHIP_CNTL"}, 359 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"}, 360 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"}, 361 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"}, 362 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"}, 363 {0xa298, "VGT_GSVS_RING_OFFSET_1"}, 364 {0xa299, "VGT_GSVS_RING_OFFSET_2"}, 365 {0xa29a, "VGT_GSVS_RING_OFFSET_3"}, 366 367 {0xa2e4, "VGT_GS_INSTANCE_CNT"}, 368 {0xa297, "VGT_GS_PER_VS"}, 369 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, 370 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, 371 372 {0xa2ad, "VGT_REUSE_OFF"}, 373 {0xa1b8, "SPI_BARYC_CNTL"}, 374 375 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"}, 376 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"}, 377 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"}, 378 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"}, 379 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"}, 380 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"}, 381 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"}, 382 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"}, 383 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"}, 384 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"}, 385 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"}, 386 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"}, 387 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"}, 388 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"}, 389 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"}, 390 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"}, 391 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"}, 392 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"}, 393 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"}, 394 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"}, 395 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"}, 396 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"}, 397 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"}, 398 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"}, 399 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"}, 400 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"}, 401 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"}, 402 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"}, 403 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"}, 404 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"}, 405 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, 406 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, 407 408 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"}, 409 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"}, 410 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"}, 411 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"}, 412 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"}, 413 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"}, 414 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"}, 415 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"}, 416 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"}, 417 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"}, 418 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"}, 419 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"}, 420 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"}, 421 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"}, 422 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"}, 423 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"}, 424 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"}, 425 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"}, 426 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"}, 427 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"}, 428 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"}, 429 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"}, 430 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"}, 431 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"}, 432 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"}, 433 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"}, 434 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"}, 435 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"}, 436 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"}, 437 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"}, 438 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"}, 439 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"}, 440 441 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, 442 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, 443 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, 444 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"}, 445 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"}, 446 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"}, 447 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"}, 448 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"}, 449 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"}, 450 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"}, 451 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"}, 452 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"}, 453 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"}, 454 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"}, 455 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"}, 456 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"}, 457 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"}, 458 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"}, 459 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"}, 460 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"}, 461 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"}, 462 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"}, 463 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"}, 464 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"}, 465 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"}, 466 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"}, 467 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"}, 468 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"}, 469 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"}, 470 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"}, 471 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"}, 472 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"}, 473 474 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"}, 475 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"}, 476 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"}, 477 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"}, 478 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"}, 479 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"}, 480 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"}, 481 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"}, 482 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"}, 483 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"}, 484 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"}, 485 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"}, 486 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"}, 487 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"}, 488 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"}, 489 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"}, 490 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"}, 491 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"}, 492 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"}, 493 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"}, 494 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"}, 495 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"}, 496 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"}, 497 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"}, 498 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"}, 499 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"}, 500 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"}, 501 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"}, 502 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"}, 503 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"}, 504 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"}, 505 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"}, 506 507 {0x2e40, "COMPUTE_USER_DATA_0"}, 508 {0x2e41, "COMPUTE_USER_DATA_1"}, 509 {0x2e42, "COMPUTE_USER_DATA_2"}, 510 {0x2e43, "COMPUTE_USER_DATA_3"}, 511 {0x2e44, "COMPUTE_USER_DATA_4"}, 512 {0x2e45, "COMPUTE_USER_DATA_5"}, 513 {0x2e46, "COMPUTE_USER_DATA_6"}, 514 {0x2e47, "COMPUTE_USER_DATA_7"}, 515 {0x2e48, "COMPUTE_USER_DATA_8"}, 516 {0x2e49, "COMPUTE_USER_DATA_9"}, 517 {0x2e4a, "COMPUTE_USER_DATA_10"}, 518 {0x2e4b, "COMPUTE_USER_DATA_11"}, 519 {0x2e4c, "COMPUTE_USER_DATA_12"}, 520 {0x2e4d, "COMPUTE_USER_DATA_13"}, 521 {0x2e4e, "COMPUTE_USER_DATA_14"}, 522 {0x2e4f, "COMPUTE_USER_DATA_15"}, 523 524 {0x2e07, "COMPUTE_NUM_THREAD_X"}, 525 {0x2e08, "COMPUTE_NUM_THREAD_Y"}, 526 {0x2e09, "COMPUTE_NUM_THREAD_Z"}, 527 {0xa2db, "VGT_TF_PARAM"}, 528 {0xa2d6, "VGT_LS_HS_CONFIG"}, 529 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"}, 530 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"}, 531 {0xa2f8, "PA_SC_AA_CONFIG"}, 532 {0xa310, "PA_SC_SHADER_CONTROL"}, 533 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, 534 535 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"}, 536 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"}, 537 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"}, 538 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"}, 539 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"}, 540 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"}, 541 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"}, 542 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"}, 543 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"}, 544 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"}, 545 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"}, 546 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"}, 547 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"}, 548 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"}, 549 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"}, 550 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"}, 551 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"}, 552 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"}, 553 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"}, 554 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"}, 555 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"}, 556 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"}, 557 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"}, 558 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"}, 559 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"}, 560 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"}, 561 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"}, 562 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"}, 563 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"}, 564 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"}, 565 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"}, 566 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"}, 567 568 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"}, 569 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"}, 570 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"}, 571 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"}, 572 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"}, 573 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"}, 574 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"}, 575 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"}, 576 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"}, 577 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"}, 578 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"}, 579 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"}, 580 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"}, 581 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"}, 582 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"}, 583 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"}, 584 585 {0xa2aa, "IA_MULTI_VGT_PARAM"}, 586 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, 587 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"}, 588 {0xa2e5, "VGT_STRMOUT_CONFIG"}, 589 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"}, 590 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"}, 591 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"}, 592 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"}, 593 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"}, 594 595 {0x2e28, "COMPUTE_PGM_RSRC3"}, 596 {0x2e2a, "COMPUTE_SHADER_CHKSUM"}, 597 {0x2e24, "COMPUTE_USER_ACCUM_0"}, 598 {0x2e25, "COMPUTE_USER_ACCUM_1"}, 599 {0x2e26, "COMPUTE_USER_ACCUM_2"}, 600 {0x2e27, "COMPUTE_USER_ACCUM_3"}, 601 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"}, 602 {0xa2d3, "GE_NGG_SUBGRP_CNTL"}, 603 {0xc25f, "GE_STEREO_CNTL"}, 604 {0xc262, "GE_USER_VGPR_EN"}, 605 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"}, 606 {0xa210, "PA_STEREO_CNTL"}, 607 {0xa1c2, "SPI_SHADER_IDX_FORMAT"}, 608 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"}, 609 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"}, 610 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"}, 611 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"}, 612 {0x2c88, "SPI_SHADER_PGM_LO_GS"}, 613 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"}, 614 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"}, 615 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"}, 616 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"}, 617 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"}, 618 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"}, 619 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"}, 620 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"}, 621 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"}, 622 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"}, 623 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"}, 624 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"}, 625 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"}, 626 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"}, 627 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"}, 628 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"}, 629 630 {0, nullptr}}; 631 auto Entry = RegInfoTable; 632 for (; Entry->Num && Entry->Num != RegNum; ++Entry) 633 ; 634 return Entry->Name; 635 } 636 637 // Convert the accumulated PAL metadata into an asm directive. 638 void AMDGPUPALMetadata::toString(std::string &String) { 639 String.clear(); 640 if (!BlobType) 641 return; 642 raw_string_ostream Stream(String); 643 if (isLegacy()) { 644 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil) 645 return; 646 // Old linear reg=val format. 647 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' '; 648 auto Regs = getRegisters(); 649 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { 650 if (I != Regs.begin()) 651 Stream << ','; 652 unsigned Reg = I->first.getUInt(); 653 unsigned Val = I->second.getUInt(); 654 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val); 655 } 656 Stream << '\n'; 657 return; 658 } 659 660 // New msgpack-based format -- output as YAML (with unsigned numbers in hex), 661 // but first change the registers map to use names. 662 MsgPackDoc.setHexMode(); 663 auto &RegsObj = refRegisters(); 664 auto OrigRegs = RegsObj.getMap(); 665 RegsObj = MsgPackDoc.getMapNode(); 666 for (auto I : OrigRegs) { 667 auto Key = I.first; 668 if (const char *RegName = getRegisterName(Key.getUInt())) { 669 std::string KeyName = Key.toString(); 670 KeyName += " ("; 671 KeyName += RegName; 672 KeyName += ')'; 673 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true); 674 } 675 RegsObj.getMap()[Key] = I.second; 676 } 677 678 // Output as YAML. 679 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n'; 680 MsgPackDoc.toYAML(Stream); 681 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n'; 682 683 // Restore original registers map. 684 RegsObj = OrigRegs; 685 } 686 687 // Convert the accumulated PAL metadata into a binary blob for writing as 688 // a .note record of the specified AMD type. Returns an empty blob if 689 // there is no PAL metadata, 690 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) { 691 if (Type == ELF::NT_AMD_PAL_METADATA) 692 toLegacyBlob(Blob); 693 else if (Type) 694 toMsgPackBlob(Blob); 695 } 696 697 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) { 698 Blob.clear(); 699 auto Registers = getRegisters(); 700 if (Registers.getMap().empty()) 701 return; 702 raw_string_ostream OS(Blob); 703 support::endian::Writer EW(OS, support::endianness::little); 704 for (auto I : Registers.getMap()) { 705 EW.write(uint32_t(I.first.getUInt())); 706 EW.write(uint32_t(I.second.getUInt())); 707 } 708 } 709 710 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) { 711 Blob.clear(); 712 MsgPackDoc.writeToBlob(Blob); 713 } 714 715 // Set PAL metadata from YAML text. Returns false if failed. 716 bool AMDGPUPALMetadata::setFromString(StringRef S) { 717 BlobType = ELF::NT_AMDGPU_METADATA; 718 if (!MsgPackDoc.fromYAML(S)) 719 return false; 720 721 // In the registers map, some keys may be of the form "0xa191 722 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a 723 // string. We need to turn it into a number. 724 auto &RegsObj = refRegisters(); 725 auto OrigRegs = RegsObj; 726 RegsObj = MsgPackDoc.getMapNode(); 727 Registers = RegsObj.getMap(); 728 bool Ok = true; 729 for (auto I : OrigRegs.getMap()) { 730 auto Key = I.first; 731 if (Key.getKind() == msgpack::Type::String) { 732 StringRef S = Key.getString(); 733 uint64_t Val; 734 if (S.consumeInteger(0, Val)) { 735 Ok = false; 736 errs() << "Unrecognized PAL metadata register key '" << S << "'\n"; 737 continue; 738 } 739 Key = MsgPackDoc.getNode(uint64_t(Val)); 740 } 741 Registers.getMap()[Key] = I.second; 742 } 743 return Ok; 744 } 745 746 // Reference (create if necessary) the node for the registers map. 747 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() { 748 auto &N = 749 MsgPackDoc.getRoot() 750 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 751 .getArray(/*Convert=*/true)[0] 752 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")]; 753 N.getMap(/*Convert=*/true); 754 return N; 755 } 756 757 // Get (create if necessary) the registers map. 758 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { 759 if (Registers.isEmpty()) 760 Registers = refRegisters(); 761 return Registers.getMap(); 762 } 763 764 // Reference (create if necessary) the node for the shader functions map. 765 msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() { 766 auto &N = 767 MsgPackDoc.getRoot() 768 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 769 .getArray(/*Convert=*/true)[0] 770 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")]; 771 N.getMap(/*Convert=*/true); 772 return N; 773 } 774 775 // Get (create if necessary) the shader functions map. 776 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() { 777 if (ShaderFunctions.isEmpty()) 778 ShaderFunctions = refShaderFunctions(); 779 return ShaderFunctions.getMap(); 780 } 781 782 // Get (create if necessary) a function in the shader functions map. 783 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) { 784 auto Functions = getShaderFunctions(); 785 return Functions[Name].getMap(/*Convert=*/true); 786 } 787 788 // Return the PAL metadata hardware shader stage name. 789 static const char *getStageName(CallingConv::ID CC) { 790 switch (CC) { 791 case CallingConv::AMDGPU_PS: 792 return ".ps"; 793 case CallingConv::AMDGPU_VS: 794 return ".vs"; 795 case CallingConv::AMDGPU_GS: 796 return ".gs"; 797 case CallingConv::AMDGPU_ES: 798 return ".es"; 799 case CallingConv::AMDGPU_HS: 800 return ".hs"; 801 case CallingConv::AMDGPU_LS: 802 return ".ls"; 803 case CallingConv::AMDGPU_Gfx: 804 llvm_unreachable("Callable shader has no hardware stage"); 805 default: 806 return ".cs"; 807 } 808 } 809 810 // Get (create if necessary) the .hardware_stages entry for the given calling 811 // convention. 812 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) { 813 if (HwStages.isEmpty()) 814 HwStages = MsgPackDoc.getRoot() 815 .getMap(/*Convert=*/true)["amdpal.pipelines"] 816 .getArray(/*Convert=*/true)[0] 817 .getMap(/*Convert=*/true)[".hardware_stages"] 818 .getMap(/*Convert=*/true); 819 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true); 820 } 821 822 // Get .note record vendor name of metadata blob to be emitted. 823 const char *AMDGPUPALMetadata::getVendor() const { 824 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3; 825 } 826 827 // Get .note record type of metadata blob to be emitted: 828 // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or 829 // ELF::NT_AMDGPU_METADATA (MsgPack format), or 830 // 0 (no PAL metadata). 831 unsigned AMDGPUPALMetadata::getType() const { 832 return BlobType; 833 } 834 835 // Return whether the blob type is legacy PAL metadata. 836 bool AMDGPUPALMetadata::isLegacy() const { 837 return BlobType == ELF::NT_AMD_PAL_METADATA; 838 } 839 840 // Set legacy PAL metadata format. 841 void AMDGPUPALMetadata::setLegacy() { 842 BlobType = ELF::NT_AMD_PAL_METADATA; 843 } 844 845 // Erase all PAL metadata. 846 void AMDGPUPALMetadata::reset() { 847 MsgPackDoc.clear(); 848 Registers = MsgPackDoc.getEmptyNode(); 849 HwStages = MsgPackDoc.getEmptyNode(); 850 } 851
Indexes created Mon Jun 15 00:25:07 UTC 2026