1 /* $NetBSD: pic_openpic.c,v 1.20 2022/02/23 21:54:40 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pic_openpic.c,v 1.20 2022/02/23 21:54:40 andvar Exp $"); 31 32 #ifdef _KERNEL_OPT 33 #include "opt_multiprocessor.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/kmem.h> 38 #include <sys/kernel.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <machine/pio.h> 43 #include <powerpc/openpic.h> 44 45 #include <powerpc/pic/picvar.h> 46 47 static void opic_enable_irq(struct pic_ops *, int, int); 48 static void opic_disable_irq(struct pic_ops *, int); 49 static void opic_establish_irq(struct pic_ops*, int, int, int); 50 51 struct pic_ops * 52 setup_openpic(void *addr, int passthrough) 53 { 54 struct openpic_ops *opicops; 55 struct pic_ops *pic; 56 int irq; 57 u_int x; 58 59 openpic_base = addr; 60 opicops = kmem_alloc(sizeof(*opicops), KM_SLEEP); 61 pic = &opicops->pic; 62 63 x = openpic_read(OPENPIC_FEATURE); 64 if (((x & 0x07ff0000) >> 16) == 0) 65 panic("setup_openpic() called on distributed openpic"); 66 67 aprint_normal("OpenPIC Version 1.%d: " 68 "Supports %d CPUs and %d interrupt sources.\n", 69 x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1); 70 71 pic->pic_numintrs = IPI_VECTOR + 1; 72 pic->pic_cookie = addr; 73 pic->pic_enable_irq = opic_enable_irq; 74 pic->pic_reenable_irq = opic_enable_irq; 75 pic->pic_disable_irq = opic_disable_irq; 76 pic->pic_get_irq = opic_get_irq; 77 pic->pic_ack_irq = opic_ack_irq; 78 pic->pic_establish_irq = opic_establish_irq; 79 pic->pic_finish_setup = opic_finish_setup; 80 opicops->isu = NULL; 81 opicops->nrofisus = 0; /* internal only */ 82 opicops->flags = 0; /* no flags (yet) */ 83 opicops->irq_per = NULL; /* internal ISU only */ 84 strcpy(pic->pic_name, "openpic"); 85 pic_add(pic); 86 87 /* 88 * the following sequence should make the same effects as openpic 89 * controller reset by writing a one at the self-clearing 90 * OPENPIC_CONFIG_RESET bit. Please check the document of your 91 * OpenPIC compliant interrupt controller and see whether #else 92 * portion can work as described. 93 */ 94 #if 1 95 openpic_set_priority(0, 15); 96 97 for (irq = 0; irq < (pic->pic_numintrs - 1); irq++) { 98 /* make sure to keep disabled */ 99 openpic_write(OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK); 100 /* send all interrupts to CPU 0 */ 101 openpic_write(OPENPIC_IDEST(irq), 1 << 0); 102 } 103 104 x = openpic_read(OPENPIC_CONFIG); 105 if (passthrough) 106 x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 107 else 108 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 109 openpic_write(OPENPIC_CONFIG, x); 110 111 openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff); 112 113 openpic_set_priority(0, 0); 114 115 /* clear all pending interrupts */ 116 for (irq = 0; irq < pic->pic_numintrs; irq++) { 117 openpic_read_irq(0); 118 openpic_eoi(0); 119 } 120 #else 121 irq = 0; 122 openpic_write(OPENPIC_CONFIG, OPENPIC_CONFIG_RESET); 123 do { 124 x = openpic_read(OPENPIC_CONFIG); 125 } while (x & OPENPIC_CONFIG_RESET); /* S1C bit */ 126 if (passthrough) 127 x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 128 else 129 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 130 openpic_write(OPENPIC_CONFIG, x); 131 openpic_set_priority(0, 0); 132 #endif 133 134 #if 0 135 printf("timebase freq=%d\n", openpic_read(0x10f0)); 136 #endif 137 return pic; 138 } 139 140 static void 141 opic_establish_irq(struct pic_ops *pic, int irq, int type, int pri) 142 { 143 int realpri = uimax(1, uimin(15, pri)); 144 uint32_t x; 145 146 x = irq; 147 x |= OPENPIC_IMASK; 148 149 if (type == IST_EDGE_RISING || type == IST_LEVEL_HIGH) 150 x |= OPENPIC_POLARITY_POSITIVE; 151 else 152 x |= OPENPIC_POLARITY_NEGATIVE; 153 154 if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING) 155 x |= OPENPIC_SENSE_EDGE; 156 else 157 x |= OPENPIC_SENSE_LEVEL; 158 159 x |= realpri << OPENPIC_PRIORITY_SHIFT; 160 #ifdef MULTIPROCESSOR 161 if (irq < IPI_VECTOR) 162 #endif 163 openpic_write(OPENPIC_SRC_VECTOR(irq), x); 164 165 aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq, 166 realpri); 167 } 168 169 static void 170 opic_enable_irq(struct pic_ops *pic, int irq, int type) 171 { 172 u_int x; 173 #ifdef MULTIPROCESSOR 174 if (irq == IPI_VECTOR) return; 175 #endif 176 x = openpic_read(OPENPIC_SRC_VECTOR(irq)); 177 x &= ~OPENPIC_IMASK; 178 openpic_write(OPENPIC_SRC_VECTOR(irq), x); 179 } 180 181 static void 182 opic_disable_irq(struct pic_ops *pic, int irq) 183 { 184 u_int x; 185 186 #ifdef MULTIPROCESSOR 187 if (irq == IPI_VECTOR) return; 188 #endif 189 x = openpic_read(OPENPIC_SRC_VECTOR(irq)); 190 x |= OPENPIC_IMASK; 191 openpic_write(OPENPIC_SRC_VECTOR(irq), x); 192 } 193
Indexes created Sun Sep 21 20:09:37 GMT 2025