1 /* $NetBSD: clk_mgr_internal.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DAL_CLK_MGR_INTERNAL_H__ 29 #define __DAL_CLK_MGR_INTERNAL_H__ 30 31 #include "clk_mgr.h" 32 #include "dc.h" 33 34 /* 35 * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also 36 * used in resource, perhaps this should be defined somewhere more common. 37 */ 38 #include "resource.h" 39 40 41 /* Starting DID for each range */ 42 enum dentist_base_divider_id { 43 DENTIST_BASE_DID_1 = 0x08, 44 DENTIST_BASE_DID_2 = 0x40, 45 DENTIST_BASE_DID_3 = 0x60, 46 DENTIST_BASE_DID_4 = 0x7e, 47 DENTIST_MAX_DID = 0x7f 48 }; 49 50 /* Starting point and step size for each divider range.*/ 51 enum dentist_divider_range { 52 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */ 53 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */ 54 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */ 55 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */ 56 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */ 57 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */ 58 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */ 59 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */ 60 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4 61 }; 62 63 /* 64 *************************************************************************************** 65 ****************** Clock Manager Private Macros and Defines *************************** 66 *************************************************************************************** 67 */ 68 69 /* Macros */ 70 71 #define TO_CLK_MGR_INTERNAL(clk_mgr)\ 72 container_of(clk_mgr, struct clk_mgr_internal, base) 73 74 #define CTX \ 75 clk_mgr->base.ctx 76 #define DC_LOGGER \ 77 clk_mgr->ctx->logger 78 79 80 81 82 #define CLK_BASE(inst) \ 83 CLK_BASE_INNER(inst) 84 85 #define CLK_SRI(reg_name, block, inst)\ 86 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 87 mm ## block ## _ ## inst ## _ ## reg_name 88 89 #define CLK_COMMON_REG_LIST_DCE_BASE() \ 90 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ 91 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL 92 93 #define CLK_COMMON_REG_LIST_DCN_BASE() \ 94 SR(DENTIST_DISPCLK_CNTL) 95 96 #define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \ 97 .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \ 98 .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \ 99 .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67 100 101 #define CLK_REG_LIST_NV10() \ 102 SR(DENTIST_DISPCLK_CNTL), \ 103 CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ 104 CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) 105 106 #define CLK_SF(reg_name, field_name, post_fix)\ 107 .field_name = reg_name ## __ ## field_name ## post_fix 108 109 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 110 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ 111 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) 112 113 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 114 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ 115 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) 116 117 #define CLK_MASK_SH_LIST_RV1(mask_sh) \ 118 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 119 CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\ 120 CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ 121 CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh), 122 123 #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \ 124 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 125 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ 126 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh) 127 128 #define CLK_MASK_SH_LIST_NV10(mask_sh) \ 129 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ 130 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\ 131 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh) 132 133 #define CLK_REG_FIELD_LIST(type) \ 134 type DPREFCLK_SRC_SEL; \ 135 type DENTIST_DPREFCLK_WDIVIDER; \ 136 type DENTIST_DISPCLK_WDIVIDER; \ 137 type DENTIST_DISPCLK_CHG_DONE; 138 139 /* 140 *************************************************************************************** 141 ****************** Clock Manager Private Structures *********************************** 142 *************************************************************************************** 143 */ 144 #define CLK20_REG_FIELD_LIST(type) \ 145 type DENTIST_DPPCLK_WDIVIDER; \ 146 type DENTIST_DPPCLK_CHG_DONE; \ 147 type FbMult_int; \ 148 type FbMult_frac; 149 150 #define VBIOS_SMU_REG_FIELD_LIST(type) \ 151 type CONTENT; 152 153 struct clk_mgr_shift { 154 CLK_REG_FIELD_LIST(uint8_t) 155 CLK20_REG_FIELD_LIST(uint8_t) 156 VBIOS_SMU_REG_FIELD_LIST(uint32_t) 157 }; 158 159 struct clk_mgr_mask { 160 CLK_REG_FIELD_LIST(uint32_t) 161 CLK20_REG_FIELD_LIST(uint32_t) 162 VBIOS_SMU_REG_FIELD_LIST(uint32_t) 163 }; 164 165 struct clk_mgr_registers { 166 uint32_t DPREFCLK_CNTL; 167 uint32_t DENTIST_DISPCLK_CNTL; 168 169 uint32_t CLK3_CLK2_DFS_CNTL; 170 uint32_t CLK3_CLK_PLL_REQ; 171 172 uint32_t MP1_SMN_C2PMSG_67; 173 uint32_t MP1_SMN_C2PMSG_83; 174 uint32_t MP1_SMN_C2PMSG_91; 175 }; 176 177 enum clock_type { 178 clock_type_dispclk = 1, 179 clock_type_dcfclk, 180 clock_type_socclk, 181 clock_type_pixelclk, 182 clock_type_phyclk, 183 clock_type_dppclk, 184 clock_type_fclk, 185 clock_type_dcfdsclk, 186 clock_type_dscclk, 187 clock_type_uclk, 188 clock_type_dramclk, 189 }; 190 191 192 struct state_dependent_clocks { 193 int display_clk_khz; 194 int pixel_clk_khz; 195 }; 196 197 struct clk_mgr_internal { 198 struct clk_mgr base; 199 int smu_ver; 200 struct pp_smu_funcs *pp_smu; 201 struct clk_mgr_internal_funcs *funcs; 202 203 struct dccg *dccg; 204 205 /* 206 * For backwards compatbility with previous implementation 207 * TODO: remove these after everything transitions to new pattern 208 * Rationale is that clk registers change a lot across DCE versions 209 * and a shared data structure doesn't really make sense. 210 */ 211 const struct clk_mgr_registers *regs; 212 const struct clk_mgr_shift *clk_mgr_shift; 213 const struct clk_mgr_mask *clk_mgr_mask; 214 215 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; 216 217 /*TODO: figure out which of the below fields should be here vs in asic specific portion */ 218 /* Cache the status of DFS-bypass feature*/ 219 bool dfs_bypass_enabled; 220 /* True if the DFS-bypass feature is enabled and active. */ 221 bool dfs_bypass_active; 222 223 uint32_t dfs_ref_freq_khz; 224 /* 225 * Cache the display clock returned by VBIOS if DFS-bypass is enabled. 226 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency 227 */ 228 int dfs_bypass_disp_clk; 229 230 /** 231 * @ss_on_dprefclk: 232 * 233 * True if spread spectrum is enabled on the DP ref clock. 234 */ 235 bool ss_on_dprefclk; 236 237 /** 238 * @xgmi_enabled: 239 * 240 * True if xGMI is enabled. On VG20, both audio and display clocks need 241 * to be adjusted with the WAFL link's SS info if xGMI is enabled. 242 */ 243 bool xgmi_enabled; 244 245 /** 246 * @dprefclk_ss_percentage: 247 * 248 * DPREFCLK SS percentage (if down-spread enabled). 249 * 250 * Note that if XGMI is enabled, the SS info (percentage and divider) 251 * from the WAFL link is used instead. This is decided during 252 * dce_clk_mgr initialization. 253 */ 254 int dprefclk_ss_percentage; 255 256 /** 257 * @dprefclk_ss_divider: 258 * 259 * DPREFCLK SS percentage Divider (100 or 1000). 260 */ 261 int dprefclk_ss_divider; 262 263 enum dm_pp_clocks_state max_clks_state; 264 enum dm_pp_clocks_state cur_min_clks_state; 265 }; 266 267 struct clk_mgr_internal_funcs { 268 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 269 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr); 270 }; 271 272 273 /* 274 *************************************************************************************** 275 ****************** Clock Manager Level Helper functions ******************************* 276 *************************************************************************************** 277 */ 278 279 280 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) 281 { 282 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); 283 } 284 285 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) 286 { 287 if (cur_support != calc_support) { 288 if (calc_support == true && safe_to_lower) 289 return true; 290 else if (calc_support == false && !safe_to_lower) 291 return true; 292 } 293 294 return false; 295 } 296 297 int clk_mgr_helper_get_active_display_cnt( 298 struct dc *dc, 299 struct dc_state *context); 300 301 302 303 #endif //__DAL_CLK_MGR_INTERNAL_H__ 304
Indexes created Sun Sep 21 20:09:37 GMT 2025