1 /* $NetBSD: siisata.c,v 1.51 2024/02/02 22:00:33 andvar Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.51 2024/02/02 22:00:33 andvar Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 void siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 int siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 int siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 void siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static int siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 static void siisata_channel_recover(struct ata_channel *, int, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 int siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 .bustype_type = SCSIPI_BUSTYPE_ATA, 188 .ata_bio = siisata_ata_bio, 189 .ata_reset_drive = siisata_reset_drive, 190 .ata_reset_channel = siisata_reset_channel, 191 .ata_exec_command = siisata_exec_command, 192 .ata_get_params = ata_get_params, 193 .ata_addref = siisata_ata_addref, 194 .ata_delref = siisata_ata_delref, 195 .ata_killpending = siisata_killpending, 196 .ata_recovery = siisata_channel_recover, 197 }; 198 199 #if NATAPIBUS > 0 200 static const struct scsipi_bustype siisata_atapi_bustype = { 201 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 202 .bustype_cmd = atapi_scsipi_cmd, 203 .bustype_interpret_sense = atapi_interpret_sense, 204 .bustype_printaddr = atapi_print_addr, 205 .bustype_kill_pending = siisata_atapi_kill_pending, 206 .bustype_async_event_xfer_mode = NULL, 207 }; 208 #endif /* NATAPIBUS */ 209 210 211 void 212 siisata_attach(struct siisata_softc *sc) 213 { 214 int i; 215 216 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 217 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 218 219 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 220 sc->sc_atac.atac_pio_cap = 4; 221 sc->sc_atac.atac_dma_cap = 2; 222 sc->sc_atac.atac_udma_cap = 6; 223 sc->sc_atac.atac_channels = sc->sc_chanarray; 224 sc->sc_atac.atac_probe = siisata_probe_drive; 225 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 226 sc->sc_atac.atac_set_modes = siisata_setup_channel; 227 #if NATAPIBUS > 0 228 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 229 #endif 230 231 /* come out of reset state */ 232 GRWRITE(sc, GR_GC, 0); 233 234 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 235 siisata_attach_port(sc, i); 236 } 237 238 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 239 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 240 return; 241 } 242 243 static void 244 siisata_disable_port_interrupt(struct ata_channel *chp) 245 { 246 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 247 248 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 249 } 250 251 static void 252 siisata_enable_port_interrupt(struct ata_channel *chp) 253 { 254 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 255 256 /* clear any interrupts */ 257 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 258 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 259 /* and enable CmdErrr+CmdCmpl interrupting */ 260 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 261 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 262 } 263 264 static int 265 siisata_init_port(struct siisata_softc *sc, int port) 266 { 267 struct siisata_channel *schp; 268 struct ata_channel *chp; 269 int error; 270 271 schp = &sc->sc_channels[port]; 272 chp = (struct ata_channel *)schp; 273 274 /* 275 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 276 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 277 */ 278 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 279 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 280 /* initialize port */ 281 error = siisata_reinit_port(chp, -1); 282 /* enable CmdErrr+CmdCmpl interrupting */ 283 siisata_enable_port_interrupt(chp); 284 /* enable port interrupt */ 285 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 286 287 return error; 288 } 289 290 static void 291 siisata_attach_port(struct siisata_softc *sc, int port) 292 { 293 int j; 294 int dmasize; 295 int error; 296 void *prbp; 297 struct siisata_channel *schp; 298 struct ata_channel *chp; 299 300 schp = &sc->sc_channels[port]; 301 chp = (struct ata_channel *)schp; 302 sc->sc_chanarray[port] = chp; 303 chp->ch_channel = port; 304 chp->ch_atac = &sc->sc_atac; 305 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 306 if (chp->ch_queue == NULL) { 307 aprint_error_dev(sc->sc_atac.atac_dev, 308 "port %d: can't allocate memory " 309 "for command queue\n", chp->ch_channel); 310 return; 311 } 312 313 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 314 315 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 316 __func__, dmasize), DEBUG_FUNCS); 317 318 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 319 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 320 if (error) { 321 aprint_error_dev(sc->sc_atac.atac_dev, 322 "unable to allocate PRB table memory, " 323 "error=%d\n", error); 324 return; 325 } 326 327 error = bus_dmamem_map(sc->sc_dmat, 328 &schp->sch_prb_seg, schp->sch_prb_nseg, 329 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 330 if (error) { 331 aprint_error_dev(sc->sc_atac.atac_dev, 332 "unable to map PRB table memory, " 333 "error=%d\n", error); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 340 BUS_DMA_NOWAIT, &schp->sch_prbd); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to create PRB table map, " 344 "error=%d\n", error); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 352 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 353 if (error) { 354 aprint_error_dev(sc->sc_atac.atac_dev, 355 "unable to load PRB table map, " 356 "error=%d\n", error); 357 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 358 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 359 bus_dmamem_free(sc->sc_dmat, 360 &schp->sch_prb_seg, schp->sch_prb_nseg); 361 return; 362 } 363 364 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 365 schp->sch_prb[j] = (struct siisata_prb *) 366 ((char *)prbp + SIISATA_CMD_SIZE * j); 367 schp->sch_bus_prb[j] = 368 schp->sch_prbd->dm_segs[0].ds_addr + 369 SIISATA_CMD_SIZE * j; 370 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 371 SIISATA_NSGE, MAXPHYS, 0, 372 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 373 &schp->sch_datad[j]); 374 if (error) { 375 aprint_error_dev(sc->sc_atac.atac_dev, 376 "couldn't create xfer DMA map, error=%d\n", 377 error); 378 return; 379 } 380 } 381 382 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 383 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 384 aprint_error_dev(sc->sc_atac.atac_dev, 385 "couldn't map port %d SStatus regs\n", 386 chp->ch_channel); 387 return; 388 } 389 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 390 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 391 aprint_error_dev(sc->sc_atac.atac_dev, 392 "couldn't map port %d SControl regs\n", 393 chp->ch_channel); 394 return; 395 } 396 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 397 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 398 aprint_error_dev(sc->sc_atac.atac_dev, 399 "couldn't map port %d SError regs\n", 400 chp->ch_channel); 401 return; 402 } 403 404 (void)siisata_init_port(sc, port); 405 406 ata_channel_attach(chp); 407 408 return; 409 } 410 411 void 412 siisata_childdetached(struct siisata_softc *sc, device_t child) 413 { 414 struct ata_channel *chp; 415 416 for (int i = 0; i < sc->sc_atac.atac_nchannels; i++) { 417 chp = sc->sc_chanarray[i]; 418 419 if (child == chp->atabus) 420 chp->atabus = NULL; 421 } 422 } 423 424 int 425 siisata_detach(struct siisata_softc *sc, int flags) 426 { 427 struct atac_softc *atac = &sc->sc_atac; 428 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 429 struct siisata_channel *schp; 430 struct ata_channel *chp; 431 int i, j, error; 432 433 if (adapt->adapt_refcnt != 0) 434 return EBUSY; 435 436 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 437 schp = &sc->sc_channels[i]; 438 chp = sc->sc_chanarray[i]; 439 440 if (chp->atabus != NULL) { 441 if ((error = config_detach(chp->atabus, flags)) != 0) 442 return error; 443 444 KASSERT(chp->atabus == NULL); 445 } 446 447 if (chp->ch_flags & ATACH_DETACHED) 448 continue; 449 450 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 451 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 452 453 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 454 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 455 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 456 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 457 bus_dmamem_free(sc->sc_dmat, 458 &schp->sch_prb_seg, schp->sch_prb_nseg); 459 460 ata_channel_detach(chp); 461 } 462 463 /* leave the chip in reset */ 464 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 465 466 return 0; 467 } 468 469 void 470 siisata_resume(struct siisata_softc *sc) 471 { 472 /* come out of reset state */ 473 GRWRITE(sc, GR_GC, 0); 474 475 for (int port = 0; port < sc->sc_atac.atac_nchannels; port++) { 476 int error; 477 478 error = siisata_init_port(sc, port); 479 if (error) { 480 struct siisata_channel *schp = &sc->sc_channels[port]; 481 struct ata_channel *chp = (struct ata_channel *)schp; 482 483 ata_channel_lock(chp); 484 siisata_reset_channel(chp, AT_POLL); 485 ata_channel_unlock(chp); 486 } 487 } 488 } 489 490 int 491 siisata_intr(void *v) 492 { 493 struct siisata_softc *sc = v; 494 uint32_t is; 495 int i, r = 0; 496 while ((is = GRREAD(sc, GR_GIS))) { 497 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 498 SIISATANAME(sc), __func__, is), DEBUG_INTR); 499 r = 1; 500 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 501 if (is & GR_GIS_PXIS(i)) 502 siisata_intr_port(&sc->sc_channels[i]); 503 } 504 return r; 505 } 506 507 static void 508 siisata_intr_port(struct siisata_channel *schp) 509 { 510 struct siisata_softc *sc = 511 (struct siisata_softc *)schp->ata_channel.ch_atac; 512 struct ata_channel *chp = &schp->ata_channel; 513 struct ata_xfer *xfer = NULL; 514 uint32_t pss, pis, tfd = 0; 515 bool recover = false; 516 517 /* get slot status, clearing completion interrupt */ 518 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 519 520 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 521 SIISATANAME(sc), __func__, chp->ch_channel, pss), 522 DEBUG_INTR); 523 524 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 525 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 526 goto process; 527 } 528 529 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 530 531 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 532 533 if (pis & PR_PIS_CMDERRR) { 534 uint32_t ec; 535 536 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 537 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 538 539 /* emulate a CRC error by default */ 540 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 541 542 if (ec <= PR_PCE_DATAFISERROR) { 543 if (ec == PR_PCE_DEVICEERROR && 544 (chp->ch_flags & ATACH_NCQ) == 0 && 545 (xfer = ata_queue_get_active_xfer(chp)) != NULL) { 546 /* read in specific information about error */ 547 uint32_t prbfis = bus_space_read_stream_4( 548 sc->sc_prt, sc->sc_prh, 549 PRSX(chp->ch_channel, xfer->c_slot, 550 PRSO_FIS)); 551 552 /* get status and error */ 553 int ntfd = satafis_rdh_parse(chp, 554 (uint8_t *)&prbfis); 555 556 if (ATACH_ST(ntfd) & WDCS_ERR) 557 tfd = ntfd; 558 } 559 560 /* 561 * We don't expect the recovery to trigger error, 562 * but handle this just in case. 563 */ 564 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 565 recover = true; 566 else { 567 aprint_error_dev(sc->sc_atac.atac_dev, 568 "error ec %x while recovering\n", ec); 569 570 /* Command will be marked as errored out */ 571 pss = 0; 572 } 573 } else { 574 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 575 " on port %d (ctx 0x%x), resetting\n", 576 ec, chp->ch_channel, 577 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 578 579 /* okay, we have a "Fatal Error" */ 580 ata_channel_lock(chp); 581 siisata_device_reset(chp); 582 ata_channel_unlock(chp); 583 } 584 } 585 586 /* clear some (ok, all) ints */ 587 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 588 589 if (__predict_false(recover)) 590 ata_channel_freeze(chp); 591 592 process: 593 if (xfer != NULL) { 594 xfer->ops->c_intr(chp, xfer, tfd); 595 } else { 596 /* 597 * For NCQ, HBA halts processing when error is notified, 598 * and any further D2H FISes are ignored until the error 599 * condition is cleared. Hence if a command is inactive, 600 * it means it actually already finished successfully. 601 * Note: active slots can change as c_intr() callback 602 * can activate another command(s), so must only process 603 * commands active before we start processing. 604 */ 605 uint32_t aslots = ata_queue_active(chp); 606 607 for (int slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 608 if ((aslots & __BIT(slot)) != 0 && 609 (pss & PR_PXSS(slot)) == 0) { 610 xfer = ata_queue_hwslot_to_xfer(chp, slot); 611 xfer->ops->c_intr(chp, xfer, 0); 612 } 613 } 614 } 615 616 if (__predict_false(recover)) { 617 ata_channel_lock(chp); 618 ata_channel_thaw_locked(chp); 619 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 620 ata_channel_unlock(chp); 621 } 622 } 623 624 /* Recover channel after transfer aborted */ 625 void 626 siisata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 627 { 628 struct siisata_channel *schp = (struct siisata_channel *)chp; 629 struct siisata_softc *sc = 630 (struct siisata_softc *)schp->ata_channel.ch_atac; 631 int drive; 632 633 ata_channel_lock_owned(chp); 634 635 if (chp->ch_ndrives > PMP_PORT_CTL) { 636 /* Get PM port number for the device in error */ 637 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 638 drive = PRO_PCR_PMP(pcr); 639 } else 640 drive = 0; 641 642 /* 643 * If BSY or DRQ bits are set, must execute COMRESET to return 644 * device to idle state. Otherwise, commands can be reissued 645 * after reinitialization of port. After that, need to execute 646 * READ LOG EXT for NCQ to unblock device processing if COMRESET 647 * was not done. 648 */ 649 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 650 siisata_device_reset(chp); 651 goto out; 652 } 653 654 KASSERT(drive >= 0); 655 (void)siisata_reinit_port(chp, drive); 656 657 ata_recovery_resume(chp, drive, tfd, flags); 658 659 out: 660 /* Drive unblocked, back to normal operation */ 661 return; 662 } 663 664 void 665 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 666 { 667 struct ata_channel *chp = drvp->chnl_softc; 668 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 669 struct siisata_channel *schp = (struct siisata_channel *)chp; 670 struct siisata_prb *prb; 671 uint8_t c_slot; 672 uint32_t pss, pis; 673 int i; 674 bool timed_out; 675 676 ata_channel_lock_owned(chp); 677 678 if (siisata_reinit_port(chp, drvp->drive)) 679 siisata_reset_channel(chp, flags); 680 681 /* get a slot for running the command on */ 682 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 683 panic("%s: %s: failed to get xfer for reset, port %d\n", 684 device_xname(sc->sc_atac.atac_dev), 685 __func__, chp->ch_channel); 686 /* NOTREACHED */ 687 } 688 689 prb = schp->sch_prb[c_slot]; 690 memset(prb, 0, SIISATA_CMD_SIZE); 691 prb->prb_control = 692 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 693 KASSERT(drvp->drive <= PMP_PORT_CTL); 694 prb->prb_fis[rhd_c] = drvp->drive; 695 696 siisata_disable_port_interrupt(chp); 697 698 siisata_activate_prb(schp, c_slot); 699 700 timed_out = true; 701 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 702 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 703 if ((pss & PR_PXSS(c_slot)) == 0) { 704 timed_out = false; 705 break; 706 } 707 if (pss & PR_PSS_ATTENTION) 708 break; 709 ata_delay(chp, 10, "siiprb", flags); 710 } 711 712 siisata_deactivate_prb(schp, c_slot); 713 714 if ((pss & PR_PSS_ATTENTION) != 0) { 715 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 716 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 717 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 718 719 if (slot != c_slot) 720 device_printf(sc->sc_atac.atac_dev, "%s port %d " 721 "drive %d slot %d c_slot %d", __func__, 722 chp->ch_channel, drvp->drive, slot, c_slot); 723 724 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 725 PR_PIS_CMDERRR); 726 } 727 728 siisata_enable_port_interrupt(chp); 729 730 if (timed_out) { 731 /* timeout */ 732 siisata_device_reset(chp); /* XXX is this right? */ 733 if (sigp) 734 *sigp = 0xffffffff; 735 } else { 736 /* read the signature out of the FIS */ 737 if (sigp) { 738 *sigp = 0; 739 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 740 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 741 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 742 PRSO_FIS+0xc)) & 0xff; 743 } 744 } 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 void 750 siisata_reset_channel(struct ata_channel *chp, int flags) 751 { 752 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 753 struct siisata_channel *schp = (struct siisata_channel *)chp; 754 755 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", SIISATANAME(sc), __func__, 756 chp->ch_channel), DEBUG_FUNCS); 757 758 ata_channel_lock_owned(chp); 759 760 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 761 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 762 aprint_error("%s port %d: reset failed\n", 763 SIISATANAME(sc), chp->ch_channel); 764 /* XXX and then ? */ 765 } 766 767 siisata_device_reset(chp); 768 769 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 770 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 771 772 return; 773 } 774 775 int 776 siisata_ata_addref(struct ata_drive_datas *drvp) 777 { 778 return 0; 779 } 780 781 void 782 siisata_ata_delref(struct ata_drive_datas *drvp) 783 { 784 return; 785 } 786 787 void 788 siisata_killpending(struct ata_drive_datas *drvp) 789 { 790 return; 791 } 792 793 void 794 siisata_probe_drive(struct ata_channel *chp) 795 { 796 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 797 struct siisata_channel *schp = (struct siisata_channel *)chp; 798 int i; 799 uint32_t sig; 800 struct siisata_prb *prb; 801 bool timed_out; 802 uint8_t c_slot; 803 804 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 805 __func__, chp->ch_channel), DEBUG_FUNCS); 806 807 ata_channel_lock(chp); 808 809 /* get a slot for running the command on */ 810 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 811 aprint_error_dev(sc->sc_atac.atac_dev, 812 "%s: failed to get xfer port %d\n", 813 __func__, chp->ch_channel); 814 ata_channel_unlock(chp); 815 return; 816 } 817 818 /* 819 * disable port interrupt as we're polling for PHY up and 820 * prb completion 821 */ 822 siisata_disable_port_interrupt(chp); 823 824 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 825 schp->sch_sstatus, AT_WAIT)) { 826 case SStatus_DET_DEV: 827 /* clear any interrupts */ 828 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 829 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 830 831 /* wait for ready */ 832 timed_out = 1; 833 for (i = 0; i < ATA_DELAY / 10; i++) { 834 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 835 PR_PS_PORT_READY) { 836 timed_out = 0; 837 break; 838 } 839 840 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 841 } 842 if (timed_out) { 843 aprint_error_dev(sc->sc_atac.atac_dev, 844 "timed out waiting for PORT_READY on port %d, " 845 "reinitializing\n", chp->ch_channel); 846 if (siisata_reinit_port(chp, -1)) 847 siisata_reset_channel(chp, AT_WAIT); 848 } 849 850 prb = schp->sch_prb[c_slot]; 851 memset(prb, 0, SIISATA_CMD_SIZE); 852 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 853 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 854 855 siisata_activate_prb(schp, c_slot); 856 857 timed_out = 1; 858 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 859 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 860 PR_PXSS(c_slot)) == 0) { 861 /* prb completed */ 862 timed_out = 0; 863 break; 864 } 865 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 866 PR_PIS_CMDERRR) { 867 /* we got an error; handle as timeout */ 868 break; 869 } 870 871 ata_delay(chp, 10, "siiprb", AT_WAIT); 872 } 873 874 siisata_deactivate_prb(schp, c_slot); 875 876 if (timed_out) { 877 aprint_error_dev(sc->sc_atac.atac_dev, 878 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 879 "resetting\n", chp->ch_channel, 880 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 881 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 882 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 883 if (siisata_reinit_port(chp, -1)) 884 siisata_reset_channel(chp, AT_WAIT); 885 break; 886 } 887 888 /* read the signature out of the FIS */ 889 sig = 0; 890 sig |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 891 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 892 sig |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 893 PRSO_FIS+0xc)) & 0xff; 894 895 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 896 __func__, sig), DEBUG_PROBE); 897 898 if (sig == 0x96690101) 899 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 900 PR_PC_PMP_ENABLE); 901 sata_interpret_sig(chp, 0, sig); 902 break; 903 default: 904 break; 905 } 906 907 siisata_enable_port_interrupt(chp); 908 909 ata_queue_free_slot(chp, c_slot); 910 911 ata_channel_unlock(chp); 912 913 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 914 __func__, chp->ch_channel), DEBUG_PROBE); 915 return; 916 } 917 918 void 919 siisata_setup_channel(struct ata_channel *chp) 920 { 921 return; 922 } 923 924 static const struct ata_xfer_ops siisata_cmd_xfer_ops = { 925 .c_start = siisata_cmd_start, 926 .c_intr = siisata_cmd_complete, 927 .c_poll = siisata_cmd_poll, 928 .c_abort = siisata_cmd_abort, 929 .c_kill_xfer = siisata_cmd_kill_xfer, 930 }; 931 932 void 933 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 934 { 935 struct ata_channel *chp = drvp->chnl_softc; 936 struct ata_command *ata_c = &xfer->c_ata_c; 937 938 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 939 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 940 DEBUG_FUNCS); 941 942 if (ata_c->flags & AT_POLL) 943 xfer->c_flags |= C_POLL; 944 if (ata_c->flags & AT_WAIT) 945 xfer->c_flags |= C_WAIT; 946 xfer->c_drive = drvp->drive; 947 xfer->c_databuf = ata_c->data; 948 xfer->c_bcount = ata_c->bcount; 949 xfer->ops = &siisata_cmd_xfer_ops; 950 951 ata_exec_xfer(chp, xfer); 952 953 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 954 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 955 DEBUG_FUNCS); 956 } 957 958 int 959 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 960 { 961 struct siisata_channel *schp = (struct siisata_channel *)chp; 962 struct ata_command *ata_c = &xfer->c_ata_c; 963 struct siisata_prb *prb; 964 965 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 966 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 967 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 968 DEBUG_FUNCS|DEBUG_XFERS); 969 970 ata_channel_lock_owned(chp); 971 972 prb = schp->sch_prb[xfer->c_slot]; 973 memset(prb, 0, SIISATA_CMD_SIZE); 974 975 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 976 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 977 prb->prb_fis[rhd_c] |= xfer->c_drive; 978 979 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 980 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 981 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 982 } 983 984 if (siisata_dma_setup(chp, xfer->c_slot, 985 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 986 ata_c->bcount, 987 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 988 ata_c->flags |= AT_DF; 989 return ATASTART_ABORT; 990 } 991 992 if (xfer->c_flags & C_POLL) { 993 /* polled command, disable interrupts */ 994 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 995 siisata_disable_port_interrupt(chp); 996 } 997 998 /* go for it */ 999 siisata_activate_prb(schp, xfer->c_slot); 1000 1001 if ((ata_c->flags & AT_POLL) == 0) { 1002 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1003 ata_timeout, chp); 1004 return ATASTART_STARTED; 1005 } else 1006 return ATASTART_POLL; 1007 } 1008 1009 int 1010 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1011 { 1012 struct siisata_channel *schp = (struct siisata_channel *)chp; 1013 1014 /* 1015 * polled command 1016 */ 1017 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1018 if (xfer->c_ata_c.flags & AT_DONE) 1019 break; 1020 siisata_intr_port(schp); 1021 DELAY(100); 1022 } 1023 1024 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1025 ata_timeout(xfer); 1026 } 1027 1028 /* reenable interrupts */ 1029 siisata_enable_port_interrupt(chp); 1030 1031 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1032 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1033 DEBUG_FUNCS); 1034 1035 return ATAPOLL_DONE; 1036 } 1037 1038 void 1039 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1040 { 1041 siisata_cmd_complete(chp, xfer, 0); 1042 } 1043 1044 void 1045 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1046 int reason) 1047 { 1048 struct ata_command *ata_c = &xfer->c_ata_c; 1049 struct siisata_channel *schp = (struct siisata_channel *)chp; 1050 bool deactivate = true; 1051 1052 switch (reason) { 1053 case KILL_GONE_INACTIVE: 1054 deactivate = false; 1055 /* FALLTHROUGH */ 1056 case KILL_GONE: 1057 ata_c->flags |= AT_GONE; 1058 break; 1059 case KILL_RESET: 1060 ata_c->flags |= AT_RESET; 1061 break; 1062 case KILL_REQUEUE: 1063 panic("%s: not supposed to be requeued\n", __func__); 1064 break; 1065 default: 1066 panic("%s: port %d: unknown reason %d", 1067 __func__, chp->ch_channel, reason); 1068 } 1069 1070 siisata_cmd_done_end(chp, xfer); 1071 1072 if (deactivate) { 1073 siisata_deactivate_prb(schp, xfer->c_slot); 1074 ata_deactivate_xfer(chp, xfer); 1075 } 1076 } 1077 1078 int 1079 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1080 { 1081 struct siisata_channel *schp = (struct siisata_channel *)chp; 1082 struct ata_command *ata_c = &xfer->c_ata_c; 1083 #ifdef SIISATA_DEBUG 1084 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1085 #endif 1086 1087 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1088 SIISATANAME(sc), __func__, 1089 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1090 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1091 DEBUG_FUNCS|DEBUG_XFERS); 1092 1093 if (ata_waitdrain_xfer_check(chp, xfer)) 1094 return 0; 1095 1096 if (xfer->c_flags & C_TIMEOU) 1097 ata_c->flags |= AT_TIMEOU; 1098 1099 if (ATACH_ST(tfd) & WDCS_BSY) { 1100 ata_c->flags |= AT_TIMEOU; 1101 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1102 ata_c->r_error = ATACH_ERR(tfd); 1103 ata_c->flags |= AT_ERROR; 1104 } 1105 1106 siisata_cmd_done(chp, xfer, tfd); 1107 1108 siisata_deactivate_prb(schp, xfer->c_slot); 1109 ata_deactivate_xfer(chp, xfer); 1110 1111 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1112 atastart(chp); 1113 1114 return 0; 1115 } 1116 1117 void 1118 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1119 { 1120 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1121 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1122 struct siisata_channel *schp = (struct siisata_channel *)chp; 1123 struct ata_command *ata_c = &xfer->c_ata_c; 1124 uint16_t *idwordbuf; 1125 int i; 1126 1127 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1128 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1129 1130 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1131 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1132 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1133 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1134 BUS_DMASYNC_POSTWRITE); 1135 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1136 } 1137 1138 if (ata_c->flags & AT_READREG) { 1139 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1140 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1141 fis, __arraycount(fis)); 1142 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1143 } 1144 1145 /* correct the endianness of IDENTIFY data */ 1146 if (ata_c->r_command == WDCC_IDENTIFY || 1147 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1148 idwordbuf = xfer->c_databuf; 1149 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1150 idwordbuf[i] = le16toh(idwordbuf[i]); 1151 } 1152 } 1153 1154 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1155 ata_c->flags |= AT_XFDONE; 1156 1157 siisata_cmd_done_end(chp, xfer); 1158 } 1159 1160 static void 1161 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1162 { 1163 struct ata_command *ata_c = &xfer->c_ata_c; 1164 1165 ata_c->flags |= AT_DONE; 1166 } 1167 1168 static const struct ata_xfer_ops siisata_bio_xfer_ops = { 1169 .c_start = siisata_bio_start, 1170 .c_intr = siisata_bio_complete, 1171 .c_poll = siisata_bio_poll, 1172 .c_abort = siisata_bio_abort, 1173 .c_kill_xfer = siisata_bio_kill_xfer, 1174 }; 1175 1176 void 1177 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1178 { 1179 struct ata_channel *chp = drvp->chnl_softc; 1180 struct ata_bio *ata_bio = &xfer->c_bio; 1181 1182 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1183 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1184 DEBUG_FUNCS); 1185 1186 if (ata_bio->flags & ATA_POLL) 1187 xfer->c_flags |= C_POLL; 1188 xfer->c_drive = drvp->drive; 1189 xfer->c_databuf = ata_bio->databuf; 1190 xfer->c_bcount = ata_bio->bcount; 1191 xfer->ops = &siisata_bio_xfer_ops; 1192 ata_exec_xfer(chp, xfer); 1193 } 1194 1195 int 1196 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1197 { 1198 struct siisata_channel *schp = (struct siisata_channel *)chp; 1199 struct siisata_prb *prb; 1200 struct ata_bio *ata_bio = &xfer->c_bio; 1201 1202 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1203 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1204 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1205 1206 ata_channel_lock_owned(chp); 1207 1208 prb = schp->sch_prb[xfer->c_slot]; 1209 memset(prb, 0, SIISATA_CMD_SIZE); 1210 1211 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1212 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1213 prb->prb_fis[rhd_c] |= xfer->c_drive; 1214 1215 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1216 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1217 ata_bio->error = ERR_DMA; 1218 ata_bio->r_error = 0; 1219 return ATASTART_ABORT; 1220 } 1221 1222 if (xfer->c_flags & C_POLL) { 1223 /* polled command, disable interrupts */ 1224 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1225 siisata_disable_port_interrupt(chp); 1226 } 1227 1228 siisata_activate_prb(schp, xfer->c_slot); 1229 1230 if ((ata_bio->flags & ATA_POLL) == 0) { 1231 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1232 ata_timeout, chp); 1233 return ATASTART_STARTED; 1234 } else 1235 return ATASTART_POLL; 1236 } 1237 1238 int 1239 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1240 { 1241 struct siisata_channel *schp = (struct siisata_channel *)chp; 1242 1243 /* 1244 * polled command 1245 */ 1246 for (int i = 0; i < ATA_DELAY * 10; i++) { 1247 if (xfer->c_bio.flags & ATA_ITSDONE) 1248 break; 1249 siisata_intr_port(schp); 1250 DELAY(100); 1251 } 1252 1253 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1254 ata_timeout(xfer); 1255 } 1256 1257 siisata_enable_port_interrupt(chp); 1258 1259 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1260 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1261 DEBUG_FUNCS); 1262 1263 return ATAPOLL_DONE; 1264 } 1265 1266 void 1267 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1268 { 1269 siisata_cmd_complete(chp, xfer, 0); 1270 } 1271 1272 void 1273 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1274 int reason) 1275 { 1276 struct siisata_channel *schp = (struct siisata_channel *)chp; 1277 struct ata_bio *ata_bio = &xfer->c_bio; 1278 int drive = xfer->c_drive; 1279 bool deactivate = true; 1280 1281 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1282 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1283 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1284 1285 ata_bio->flags |= ATA_ITSDONE; 1286 switch (reason) { 1287 case KILL_GONE_INACTIVE: 1288 deactivate = false; 1289 /* FALLTHROUGH */ 1290 case KILL_GONE: 1291 ata_bio->error = ERR_NODEV; 1292 break; 1293 case KILL_RESET: 1294 ata_bio->error = ERR_RESET; 1295 break; 1296 case KILL_REQUEUE: 1297 ata_bio->error = REQUEUE; 1298 break; 1299 default: 1300 panic("%s: port %d: unknown reason %d", 1301 __func__, chp->ch_channel, reason); 1302 } 1303 ata_bio->r_error = WDCE_ABRT; 1304 1305 if (deactivate) { 1306 siisata_deactivate_prb(schp, xfer->c_slot); 1307 ata_deactivate_xfer(chp, xfer); 1308 } 1309 1310 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1311 } 1312 1313 int 1314 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1315 { 1316 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1317 struct siisata_channel *schp = (struct siisata_channel *)chp; 1318 struct ata_bio *ata_bio = &xfer->c_bio; 1319 int drive = xfer->c_drive; 1320 1321 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1322 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1323 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1324 1325 if (ata_waitdrain_xfer_check(chp, xfer)) 1326 return 0; 1327 1328 if (xfer->c_flags & C_TIMEOU) { 1329 ata_bio->error = TIMEOUT; 1330 } 1331 1332 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1333 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1334 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1335 BUS_DMASYNC_POSTWRITE); 1336 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1337 1338 ata_bio->flags |= ATA_ITSDONE; 1339 if (ATACH_ST(tfd) & WDCS_DWF) { 1340 ata_bio->error = ERR_DF; 1341 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1342 ata_bio->error = ERROR; 1343 ata_bio->r_error = ATACH_ERR(tfd); 1344 } else if (ATACH_ST(tfd) & WDCS_CORR) 1345 ata_bio->flags |= ATA_CORR; 1346 1347 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1348 ata_bio->bcount), DEBUG_XFERS); 1349 if (ata_bio->error == NOERROR) { 1350 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1351 ata_bio->bcount -= 1352 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1353 else 1354 ata_bio->bcount = 0; 1355 } 1356 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1357 1358 siisata_deactivate_prb(schp, xfer->c_slot); 1359 ata_deactivate_xfer(chp, xfer); 1360 1361 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1362 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1363 atastart(chp); 1364 return 0; 1365 } 1366 1367 static int 1368 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1369 size_t count, int op) 1370 { 1371 1372 int error, seg; 1373 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1374 struct siisata_channel *schp = (struct siisata_channel *)chp; 1375 1376 struct siisata_prb *prbp; 1377 1378 prbp = schp->sch_prb[slot]; 1379 1380 if (data == NULL) { 1381 goto end; 1382 } 1383 1384 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1385 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1386 if (error) { 1387 aprint_error("%s port %d: " 1388 "failed to load xfer in slot %d: error %d\n", 1389 SIISATANAME(sc), chp->ch_channel, slot, error); 1390 return error; 1391 } 1392 1393 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1394 schp->sch_datad[slot]->dm_mapsize, 1395 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1396 1397 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1398 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1399 DEBUG_FUNCS | DEBUG_DEBUG); 1400 1401 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1402 prbp->prb_sge[seg].sge_da = 1403 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1404 prbp->prb_sge[seg].sge_dc = 1405 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1406 prbp->prb_sge[seg].sge_flags = htole32(0); 1407 } 1408 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1409 end: 1410 return 0; 1411 } 1412 1413 static void 1414 siisata_activate_prb(struct siisata_channel *schp, int slot) 1415 { 1416 struct siisata_softc *sc; 1417 bus_size_t offset; 1418 uint64_t pprb; 1419 1420 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1421 1422 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1423 1424 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1425 1426 pprb = schp->sch_bus_prb[slot]; 1427 1428 PRWRITE(sc, offset + 0, pprb >> 0); 1429 PRWRITE(sc, offset + 4, pprb >> 32); 1430 } 1431 1432 static void 1433 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1434 { 1435 struct siisata_softc *sc; 1436 1437 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1438 1439 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1440 } 1441 1442 static int 1443 siisata_reinit_port(struct ata_channel *chp, int drive) 1444 { 1445 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1446 int ps; 1447 int error = 0; 1448 1449 if (chp->ch_ndrives > 1) { 1450 /* 1451 * Proper recovery would SET this bit, which makes it 1452 * not possible to submit new commands and resume execution 1453 * on non-errored drives, then wait for those commands, 1454 * to finish, and only then clear the bit and reset the state. 1455 * For now this is okay, since we never queue commands for 1456 * more than one drive. 1457 * XXX FIS-based switching 1458 */ 1459 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1460 1461 for (int i = 0; i < chp->ch_ndrives; i++) { 1462 if (drive >= 0 && i != drive) 1463 continue; 1464 1465 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1466 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1467 } 1468 } 1469 1470 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1471 for (int i = 0; i < ATA_DELAY * 100; i++) { 1472 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1473 if ((ps & PR_PS_PORT_READY) != 0) 1474 break; 1475 1476 DELAY(10); 1477 } 1478 if ((ps & PR_PS_PORT_READY) == 0) { 1479 printf("%s: timeout waiting for port to be ready\n", __func__); 1480 error = EBUSY; 1481 } 1482 1483 if (chp->ch_ndrives > 1) 1484 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1485 1486 return error; 1487 } 1488 1489 static void 1490 siisata_device_reset(struct ata_channel *chp) 1491 { 1492 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1493 int ps; 1494 1495 ata_channel_lock_owned(chp); 1496 1497 /* 1498 * This is always called after siisata_reinit_port(), so don't 1499 * need to deal with RESUME and clearing device error state. 1500 */ 1501 1502 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1503 1504 for (int i = 0; i < ATA_DELAY * 100; i++) { 1505 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1506 if ((ps & PR_PS_PORT_READY) != 0) 1507 break; 1508 1509 DELAY(10); 1510 } 1511 if ((ps & PR_PS_PORT_READY) == 0) { 1512 printf("%s: timeout waiting for port to be ready\n", __func__); 1513 siisata_reset_channel(chp, AT_POLL); 1514 } 1515 1516 ata_kill_active(chp, KILL_RESET, 0); 1517 } 1518 1519 1520 #if NATAPIBUS > 0 1521 void 1522 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1523 { 1524 struct ata_channel *chp = ata_sc->sc_chan; 1525 struct atac_softc *atac = chp->ch_atac; 1526 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1527 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1528 1529 /* 1530 * Fill in the scsipi_adapter. 1531 */ 1532 adapt->adapt_dev = atac->atac_dev; 1533 adapt->adapt_nchannels = atac->atac_nchannels; 1534 adapt->adapt_request = siisata_atapi_scsipi_request; 1535 adapt->adapt_minphys = siisata_atapi_minphys; 1536 atac->atac_atapi_adapter.atapi_probe_device = 1537 siisata_atapi_probe_device; 1538 1539 /* 1540 * Fill in the scsipi_channel. 1541 */ 1542 memset(chan, 0, sizeof(*chan)); 1543 chan->chan_adapter = adapt; 1544 chan->chan_bustype = &siisata_atapi_bustype; 1545 chan->chan_channel = chp->ch_channel; 1546 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1547 chan->chan_openings = 1; 1548 chan->chan_max_periph = 1; 1549 chan->chan_ntargets = 1; 1550 chan->chan_nluns = 1; 1551 1552 chp->atapibus = config_found(ata_sc->sc_dev, chan, atapiprint, 1553 CFARGS(.iattr = "atapi")); 1554 } 1555 1556 void 1557 siisata_atapi_minphys(struct buf *bp) 1558 { 1559 if (bp->b_bcount > MAXPHYS) 1560 bp->b_bcount = MAXPHYS; 1561 minphys(bp); 1562 } 1563 1564 /* 1565 * Kill off all pending xfers for a periph. 1566 * 1567 * Must be called at splbio(). 1568 */ 1569 void 1570 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1571 { 1572 struct atac_softc *atac = 1573 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1574 struct ata_channel *chp = 1575 atac->atac_channels[periph->periph_channel->chan_channel]; 1576 1577 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1578 } 1579 1580 void 1581 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1582 int reason) 1583 { 1584 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1585 struct siisata_channel *schp = (struct siisata_channel *)chp; 1586 bool deactivate = true; 1587 1588 /* remove this command from xfer queue */ 1589 switch (reason) { 1590 case KILL_GONE_INACTIVE: 1591 deactivate = false; 1592 /* FALLTHROUGH */ 1593 case KILL_GONE: 1594 sc_xfer->error = XS_DRIVER_STUFFUP; 1595 break; 1596 case KILL_RESET: 1597 sc_xfer->error = XS_RESET; 1598 break; 1599 case KILL_REQUEUE: 1600 sc_xfer->error = XS_REQUEUE; 1601 break; 1602 default: 1603 panic("%s: port %d: unknown reason %d", 1604 __func__, chp->ch_channel, reason); 1605 } 1606 1607 if (deactivate) { 1608 siisata_deactivate_prb(schp, xfer->c_slot); 1609 ata_deactivate_xfer(chp, xfer); 1610 } 1611 1612 ata_free_xfer(chp, xfer); 1613 scsipi_done(sc_xfer); 1614 } 1615 1616 void 1617 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1618 { 1619 struct scsipi_channel *chan = sc->sc_channel; 1620 struct scsipi_periph *periph; 1621 struct ataparams ids; 1622 struct ataparams *id = &ids; 1623 struct siisata_softc *siic = 1624 device_private(chan->chan_adapter->adapt_dev); 1625 struct atac_softc *atac = &siic->sc_atac; 1626 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1627 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1628 struct scsipibus_attach_args sa; 1629 char serial_number[21], model[41], firmware_revision[9]; 1630 int s; 1631 1632 /* skip if already attached */ 1633 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1634 return; 1635 1636 /* if no ATAPI device detected at attach time, skip */ 1637 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1638 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1639 target), DEBUG_PROBE); 1640 return; 1641 } 1642 1643 /* Some ATAPI devices need a bit more time after software reset. */ 1644 DELAY(5000); 1645 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1646 #ifdef ATAPI_DEBUG_PROBE 1647 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1648 device_xname(sc->sc_dev), target, 1649 id->atap_config & ATAPI_CFG_CMD_MASK, 1650 id->atap_config & ATAPI_CFG_DRQ_MASK); 1651 #endif 1652 periph = scsipi_alloc_periph(M_WAITOK); 1653 periph->periph_dev = NULL; 1654 periph->periph_channel = chan; 1655 periph->periph_switch = &atapi_probe_periphsw; 1656 periph->periph_target = target; 1657 periph->periph_lun = 0; 1658 periph->periph_quirks = PQUIRK_ONLYBIG; 1659 1660 #ifdef SCSIPI_DEBUG 1661 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1662 SCSIPI_DEBUG_TARGET == target) 1663 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1664 #endif 1665 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1666 if (id->atap_config & ATAPI_CFG_REMOV) 1667 periph->periph_flags |= PERIPH_REMOVABLE; 1668 sa.sa_periph = periph; 1669 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1670 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1671 T_REMOV : T_FIXED; 1672 strnvisx(model, sizeof(model), id->atap_model, 40, 1673 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1674 strnvisx(serial_number, sizeof(serial_number), 1675 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1676 strnvisx(firmware_revision, sizeof(firmware_revision), 1677 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1678 sa.sa_inqbuf.vendor = model; 1679 sa.sa_inqbuf.product = serial_number; 1680 sa.sa_inqbuf.revision = firmware_revision; 1681 1682 /* 1683 * Determine the operating mode capabilities of the device. 1684 */ 1685 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1686 == ATAPI_CFG_CMD_16) { 1687 periph->periph_cap |= PERIPH_CAP_CMD16; 1688 1689 /* configure port for packet length */ 1690 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1691 PR_PC_PACKET_LENGTH); 1692 } else { 1693 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1694 PR_PC_PACKET_LENGTH); 1695 } 1696 1697 /* XXX This is gross. */ 1698 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1699 1700 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1701 1702 if (drvp->drv_softc) 1703 ata_probe_caps(drvp); 1704 else { 1705 s = splbio(); 1706 drvp->drive_type &= ATA_DRIVET_NONE; 1707 splx(s); 1708 } 1709 } else { 1710 s = splbio(); 1711 drvp->drive_type &= ATA_DRIVET_NONE; 1712 splx(s); 1713 } 1714 } 1715 1716 static const struct ata_xfer_ops siisata_atapi_xfer_ops = { 1717 .c_start = siisata_atapi_start, 1718 .c_intr = siisata_atapi_complete, 1719 .c_poll = siisata_atapi_poll, 1720 .c_abort = siisata_atapi_abort, 1721 .c_kill_xfer = siisata_atapi_kill_xfer, 1722 }; 1723 1724 void 1725 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1726 scsipi_adapter_req_t req, void *arg) 1727 { 1728 struct scsipi_adapter *adapt = chan->chan_adapter; 1729 struct scsipi_periph *periph; 1730 struct scsipi_xfer *sc_xfer; 1731 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1732 struct atac_softc *atac = &sc->sc_atac; 1733 struct ata_xfer *xfer; 1734 int channel = chan->chan_channel; 1735 int drive, s; 1736 1737 switch (req) { 1738 case ADAPTER_REQ_RUN_XFER: 1739 sc_xfer = arg; 1740 periph = sc_xfer->xs_periph; 1741 drive = periph->periph_target; 1742 1743 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1744 device_xname(atac->atac_dev), channel, drive), 1745 DEBUG_XFERS); 1746 1747 if (!device_is_active(atac->atac_dev)) { 1748 sc_xfer->error = XS_DRIVER_STUFFUP; 1749 scsipi_done(sc_xfer); 1750 return; 1751 } 1752 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1753 if (xfer == NULL) { 1754 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1755 scsipi_done(sc_xfer); 1756 return; 1757 } 1758 1759 if (sc_xfer->xs_control & XS_CTL_POLL) 1760 xfer->c_flags |= C_POLL; 1761 xfer->c_drive = drive; 1762 xfer->c_flags |= C_ATAPI; 1763 xfer->c_databuf = sc_xfer->data; 1764 xfer->c_bcount = sc_xfer->datalen; 1765 xfer->ops = &siisata_atapi_xfer_ops; 1766 xfer->c_scsipi = sc_xfer; 1767 xfer->c_atapi.c_dscpoll = 0; 1768 s = splbio(); 1769 ata_exec_xfer(atac->atac_channels[channel], xfer); 1770 #ifdef DIAGNOSTIC 1771 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1772 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1773 panic("%s: polled command not done", __func__); 1774 #endif 1775 splx(s); 1776 return; 1777 1778 default: 1779 /* Not supported, nothing to do. */ 1780 ; 1781 } 1782 } 1783 1784 int 1785 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1786 { 1787 struct siisata_channel *schp = (struct siisata_channel *)chp; 1788 struct siisata_prb *prbp; 1789 1790 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1791 1792 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1793 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1794 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1795 DEBUG_XFERS); 1796 1797 ata_channel_lock_owned(chp); 1798 1799 prbp = schp->sch_prb[xfer->c_slot]; 1800 memset(prbp, 0, SIISATA_CMD_SIZE); 1801 1802 /* fill in direction for ATAPI command */ 1803 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1804 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1805 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1806 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1807 1808 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1809 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1810 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1811 1812 /* copy over ATAPI command */ 1813 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1814 1815 if (siisata_dma_setup(chp, xfer->c_slot, 1816 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1817 xfer->c_databuf : NULL, 1818 xfer->c_bcount, 1819 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1820 BUS_DMA_READ : BUS_DMA_WRITE) 1821 ) { 1822 sc_xfer->error = XS_DRIVER_STUFFUP; 1823 return ATASTART_ABORT; 1824 } 1825 1826 if (xfer->c_flags & C_POLL) { 1827 /* polled command, disable interrupts */ 1828 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1829 siisata_disable_port_interrupt(chp); 1830 } 1831 1832 siisata_activate_prb(schp, xfer->c_slot); 1833 1834 if ((xfer->c_flags & C_POLL) == 0) { 1835 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1836 ata_timeout, chp); 1837 return ATASTART_STARTED; 1838 } else 1839 return ATASTART_POLL; 1840 } 1841 1842 int 1843 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1844 { 1845 struct siisata_channel *schp = (struct siisata_channel *)chp; 1846 1847 /* 1848 * polled command 1849 */ 1850 for (int i = 0; i < ATA_DELAY * 10; i++) { 1851 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1852 break; 1853 siisata_intr_port(schp); 1854 DELAY(100); 1855 } 1856 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1857 ata_timeout(xfer); 1858 } 1859 /* reenable interrupts */ 1860 siisata_enable_port_interrupt(chp); 1861 1862 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1863 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1864 DEBUG_FUNCS); 1865 1866 return ATAPOLL_DONE; 1867 } 1868 1869 void 1870 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1871 { 1872 siisata_atapi_complete(chp, xfer, 0); 1873 } 1874 1875 int 1876 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1877 int tfd) 1878 { 1879 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1880 struct siisata_channel *schp = (struct siisata_channel *)chp; 1881 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1882 1883 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1884 DEBUG_INTR); 1885 1886 if (ata_waitdrain_xfer_check(chp, xfer)) 1887 return 0; 1888 1889 if (xfer->c_flags & C_TIMEOU) { 1890 sc_xfer->error = XS_TIMEOUT; 1891 } 1892 1893 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1894 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1895 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1896 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1897 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1898 1899 sc_xfer->resid = sc_xfer->datalen; 1900 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1901 PRSO_RTC)); 1902 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1903 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1904 if ((ATACH_ST(tfd) & WDCS_ERR) && 1905 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1906 sc_xfer->resid == sc_xfer->datalen)) { 1907 sc_xfer->error = XS_SHORTSENSE; 1908 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1909 if ((sc_xfer->xs_periph->periph_quirks & 1910 PQUIRK_NOSENSE) == 0) { 1911 /* request sense */ 1912 sc_xfer->error = XS_BUSY; 1913 sc_xfer->status = SCSI_CHECK; 1914 } 1915 } 1916 1917 siisata_deactivate_prb(schp, xfer->c_slot); 1918 ata_deactivate_xfer(chp, xfer); 1919 1920 ata_free_xfer(chp, xfer); 1921 scsipi_done(sc_xfer); 1922 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1923 atastart(chp); 1924 return 0; 1925 } 1926 1927 #endif /* NATAPIBUS */ 1928
Indexes created Fri Sep 26 08:10:20 GMT 2025