1 /* $NetBSD: nbio_7_4_0_smn.h,v 1.2 2021/12/18 23:45:20 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _nbio_7_4_0_SMN_HEADER 25 #define _nbio_7_4_0_SMN_HEADER 26 27 // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk 28 // base address: 0x10100000 29 #define smnBIFL_RAS_CENTRAL_STATUS 0x10139040 30 31 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 32 #define smnCPM_CONTROL 0x11180460 33 #define smnPCIE_CNTL2 0x11180070 34 #define smnPCIE_CI_CNTL 0x11180080 35 36 #define smnPCIE_PERF_COUNT_CNTL 0x11180200 37 #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204 38 #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208 39 #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c 40 #define smnPCIE_PERF_CNTL_TXCLK2 0x11180210 41 #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180214 42 #define smnPCIE_PERF_COUNT1_TXCLK2 0x11180218 43 #define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c 44 #define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220 45 #define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224 46 #define smnPCIE_PERF_CNTL_TXCLK4 0x11180228 47 #define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c 48 #define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230 49 #define smnPCIE_PERF_CNTL_SCLK1 0x11180234 50 #define smnPCIE_PERF_COUNT0_SCLK1 0x11180238 51 #define smnPCIE_PERF_COUNT1_SCLK1 0x1118023c 52 #define smnPCIE_PERF_CNTL_SCLK2 0x11180240 53 #define smnPCIE_PERF_COUNT0_SCLK2 0x11180244 54 #define smnPCIE_PERF_COUNT1_SCLK2 0x11180248 55 #define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x1118024c 56 #define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x11180250 57 58 #define smnPCIE_RX_NUM_NAK 0x11180038 59 #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c 60 61 // addressBlock: nbio_iohub_nb_misc_misc_cfgdec 62 // base address: 0x13a10000 63 #define smnIOHC_INTERRUPT_EOI 0x13a10120 64 65 // addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec 66 // base address: 0x13a20000 67 #define smnRAS_GLOBAL_STATUS_LO 0x13a20020 68 #define smnRAS_GLOBAL_STATUS_HI 0x13a20024 69 70 #endif // _nbio_7_4_0_SMN_HEADER 71
Indexes created Tue Sep 30 11:09:46 GMT 2025