1 /* $NetBSD: amdgpu_dpm.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __AMDGPU_DPM_H__ 26 #define __AMDGPU_DPM_H__ 27 28 enum amdgpu_int_thermal_type { 29 THERMAL_TYPE_NONE, 30 THERMAL_TYPE_EXTERNAL, 31 THERMAL_TYPE_EXTERNAL_GPIO, 32 THERMAL_TYPE_RV6XX, 33 THERMAL_TYPE_RV770, 34 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 35 THERMAL_TYPE_EVERGREEN, 36 THERMAL_TYPE_SUMO, 37 THERMAL_TYPE_NI, 38 THERMAL_TYPE_SI, 39 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 40 THERMAL_TYPE_CI, 41 THERMAL_TYPE_KV, 42 }; 43 44 enum amdgpu_dpm_auto_throttle_src { 45 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 46 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 47 }; 48 49 enum amdgpu_dpm_event_src { 50 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 51 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 52 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 53 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 54 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 55 }; 56 57 struct amdgpu_ps { 58 u32 caps; /* vbios flags */ 59 u32 class; /* vbios flags */ 60 u32 class2; /* vbios flags */ 61 /* UVD clocks */ 62 u32 vclk; 63 u32 dclk; 64 /* VCE clocks */ 65 u32 evclk; 66 u32 ecclk; 67 bool vce_active; 68 enum amd_vce_level vce_level; 69 /* asic priv */ 70 void *ps_priv; 71 }; 72 73 struct amdgpu_dpm_thermal { 74 /* thermal interrupt work */ 75 struct work_struct work; 76 /* low temperature threshold */ 77 int min_temp; 78 /* high temperature threshold */ 79 int max_temp; 80 /* edge max emergency(shutdown) temp */ 81 int max_edge_emergency_temp; 82 /* hotspot low temperature threshold */ 83 int min_hotspot_temp; 84 /* hotspot high temperature critical threshold */ 85 int max_hotspot_crit_temp; 86 /* hotspot max emergency(shutdown) temp */ 87 int max_hotspot_emergency_temp; 88 /* memory low temperature threshold */ 89 int min_mem_temp; 90 /* memory high temperature critical threshold */ 91 int max_mem_crit_temp; 92 /* memory max emergency(shutdown) temp */ 93 int max_mem_emergency_temp; 94 /* was last interrupt low to high or high to low */ 95 bool high_to_low; 96 /* interrupt source */ 97 struct amdgpu_irq_src irq; 98 }; 99 100 enum amdgpu_clk_action 101 { 102 AMDGPU_SCLK_UP = 1, 103 AMDGPU_SCLK_DOWN 104 }; 105 106 struct amdgpu_blacklist_clocks 107 { 108 u32 sclk; 109 u32 mclk; 110 enum amdgpu_clk_action action; 111 }; 112 113 struct amdgpu_clock_and_voltage_limits { 114 u32 sclk; 115 u32 mclk; 116 u16 vddc; 117 u16 vddci; 118 }; 119 120 struct amdgpu_clock_array { 121 u32 count; 122 u32 *values; 123 }; 124 125 struct amdgpu_clock_voltage_dependency_entry { 126 u32 clk; 127 u16 v; 128 }; 129 130 struct amdgpu_clock_voltage_dependency_table { 131 u32 count; 132 struct amdgpu_clock_voltage_dependency_entry *entries; 133 }; 134 135 union amdgpu_cac_leakage_entry { 136 struct { 137 u16 vddc; 138 u32 leakage; 139 }; 140 struct { 141 u16 vddc1; 142 u16 vddc2; 143 u16 vddc3; 144 }; 145 }; 146 147 struct amdgpu_cac_leakage_table { 148 u32 count; 149 union amdgpu_cac_leakage_entry *entries; 150 }; 151 152 struct amdgpu_phase_shedding_limits_entry { 153 u16 voltage; 154 u32 sclk; 155 u32 mclk; 156 }; 157 158 struct amdgpu_phase_shedding_limits_table { 159 u32 count; 160 struct amdgpu_phase_shedding_limits_entry *entries; 161 }; 162 163 struct amdgpu_uvd_clock_voltage_dependency_entry { 164 u32 vclk; 165 u32 dclk; 166 u16 v; 167 }; 168 169 struct amdgpu_uvd_clock_voltage_dependency_table { 170 u8 count; 171 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 172 }; 173 174 struct amdgpu_vce_clock_voltage_dependency_entry { 175 u32 ecclk; 176 u32 evclk; 177 u16 v; 178 }; 179 180 struct amdgpu_vce_clock_voltage_dependency_table { 181 u8 count; 182 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 183 }; 184 185 struct amdgpu_ppm_table { 186 u8 ppm_design; 187 u16 cpu_core_number; 188 u32 platform_tdp; 189 u32 small_ac_platform_tdp; 190 u32 platform_tdc; 191 u32 small_ac_platform_tdc; 192 u32 apu_tdp; 193 u32 dgpu_tdp; 194 u32 dgpu_ulv_power; 195 u32 tj_max; 196 }; 197 198 struct amdgpu_cac_tdp_table { 199 u16 tdp; 200 u16 configurable_tdp; 201 u16 tdc; 202 u16 battery_power_limit; 203 u16 small_power_limit; 204 u16 low_cac_leakage; 205 u16 high_cac_leakage; 206 u16 maximum_power_delivery_limit; 207 }; 208 209 struct amdgpu_dpm_dynamic_state { 210 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 211 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 212 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 213 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 214 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 215 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 216 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 217 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 218 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 219 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 220 struct amdgpu_clock_array valid_sclk_values; 221 struct amdgpu_clock_array valid_mclk_values; 222 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 223 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 224 u32 mclk_sclk_ratio; 225 u32 sclk_mclk_delta; 226 u16 vddc_vddci_delta; 227 u16 min_vddc_for_pcie_gen2; 228 struct amdgpu_cac_leakage_table cac_leakage_table; 229 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 230 struct amdgpu_ppm_table *ppm_table; 231 struct amdgpu_cac_tdp_table *cac_tdp_table; 232 }; 233 234 struct amdgpu_dpm_fan { 235 u16 t_min; 236 u16 t_med; 237 u16 t_high; 238 u16 pwm_min; 239 u16 pwm_med; 240 u16 pwm_high; 241 u8 t_hyst; 242 u32 cycle_delay; 243 u16 t_max; 244 u8 control_mode; 245 u16 default_max_fan_pwm; 246 u16 default_fan_output_sensitivity; 247 u16 fan_output_sensitivity; 248 bool ucode_fan_control; 249 }; 250 251 enum amdgpu_pcie_gen { 252 AMDGPU_PCIE_GEN1 = 0, 253 AMDGPU_PCIE_GEN2 = 1, 254 AMDGPU_PCIE_GEN3 = 2, 255 AMDGPU_PCIE_GEN_INVALID = 0xffff 256 }; 257 258 #define amdgpu_dpm_pre_set_power_state(adev) \ 259 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle)) 260 261 #define amdgpu_dpm_set_power_state(adev) \ 262 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle)) 263 264 #define amdgpu_dpm_post_set_power_state(adev) \ 265 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle)) 266 267 #define amdgpu_dpm_display_configuration_changed(adev) \ 268 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle)) 269 270 #define amdgpu_dpm_print_power_state(adev, ps) \ 271 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps))) 272 273 #define amdgpu_dpm_vblank_too_short(adev) \ 274 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle)) 275 276 #define amdgpu_dpm_enable_bapm(adev, e) \ 277 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 278 279 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 280 ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m))) 281 282 #define amdgpu_dpm_get_fan_control_mode(adev) \ 283 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle)) 284 285 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 286 ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s))) 287 288 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 289 ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s))) 290 291 #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ 292 ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s)) 293 294 #define amdgpu_dpm_set_fan_speed_rpm(adev, s) \ 295 ((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s)) 296 297 #define amdgpu_dpm_force_performance_level(adev, l) \ 298 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l))) 299 300 #define amdgpu_dpm_get_current_power_state(adev) \ 301 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)) 302 303 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 304 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)) 305 306 #define amdgpu_dpm_get_pp_table(adev, table) \ 307 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)) 308 309 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 310 ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)) 311 312 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 313 ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)) 314 315 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 316 ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)) 317 318 #define amdgpu_dpm_get_sclk_od(adev) \ 319 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)) 320 321 #define amdgpu_dpm_set_sclk_od(adev, value) \ 322 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)) 323 324 #define amdgpu_dpm_get_mclk_od(adev) \ 325 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) 326 327 #define amdgpu_dpm_set_mclk_od(adev, value) \ 328 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) 329 330 #define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \ 331 ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state)) 332 333 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ 334 ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) 335 336 #define amdgpu_dpm_get_vce_clock_state(adev, i) \ 337 ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i))) 338 339 #define amdgpu_dpm_get_performance_level(adev) \ 340 ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)) 341 342 #define amdgpu_dpm_reset_power_profile_state(adev, request) \ 343 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ 344 (adev)->powerplay.pp_handle, request)) 345 346 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \ 347 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ 348 (adev)->powerplay.pp_handle, msg_id)) 349 350 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \ 351 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\ 352 (adev)->powerplay.pp_handle, buf)) 353 354 #define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \ 355 ((adev)->powerplay.pp_funcs->set_power_profile_mode(\ 356 (adev)->powerplay.pp_handle, parameter, size)) 357 358 #define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \ 359 ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\ 360 (adev)->powerplay.pp_handle, type, parameter, size)) 361 362 #define amdgpu_dpm_enable_mgpu_fan_boost(adev) \ 363 ((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\ 364 (adev)->powerplay.pp_handle)) 365 366 #define amdgpu_dpm_get_ppfeature_status(adev, buf) \ 367 ((adev)->powerplay.pp_funcs->get_ppfeature_status(\ 368 (adev)->powerplay.pp_handle, (buf))) 369 370 #define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \ 371 ((adev)->powerplay.pp_funcs->set_ppfeature_status(\ 372 (adev)->powerplay.pp_handle, (ppfeatures))) 373 374 struct amdgpu_dpm { 375 struct amdgpu_ps *ps; 376 /* number of valid power states */ 377 int num_ps; 378 /* current power state that is active */ 379 struct amdgpu_ps *current_ps; 380 /* requested power state */ 381 struct amdgpu_ps *requested_ps; 382 /* boot up power state */ 383 struct amdgpu_ps *boot_ps; 384 /* default uvd power state */ 385 struct amdgpu_ps *uvd_ps; 386 /* vce requirements */ 387 u32 num_of_vce_states; 388 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 389 enum amd_vce_level vce_level; 390 enum amd_pm_state_type state; 391 enum amd_pm_state_type user_state; 392 enum amd_pm_state_type last_state; 393 enum amd_pm_state_type last_user_state; 394 u32 platform_caps; 395 u32 voltage_response_time; 396 u32 backbias_response_time; 397 void *priv; 398 u32 new_active_crtcs; 399 int new_active_crtc_count; 400 u32 current_active_crtcs; 401 int current_active_crtc_count; 402 struct amdgpu_dpm_dynamic_state dyn_state; 403 struct amdgpu_dpm_fan fan; 404 u32 tdp_limit; 405 u32 near_tdp_limit; 406 u32 near_tdp_limit_adjusted; 407 u32 sq_ramping_threshold; 408 u32 cac_leakage; 409 u16 tdp_od_limit; 410 u32 tdp_adjustment; 411 u16 load_line_slope; 412 bool power_control; 413 /* special states active */ 414 bool thermal_active; 415 bool uvd_active; 416 bool vce_active; 417 /* thermal handling */ 418 struct amdgpu_dpm_thermal thermal; 419 /* forced levels */ 420 enum amd_dpm_forced_level forced_level; 421 }; 422 423 struct amdgpu_pm { 424 struct mutex mutex; 425 u32 current_sclk; 426 u32 current_mclk; 427 u32 default_sclk; 428 u32 default_mclk; 429 struct amdgpu_i2c_chan *i2c_bus; 430 /* internal thermal controller on rv6xx+ */ 431 enum amdgpu_int_thermal_type int_thermal_type; 432 struct device *int_hwmon_dev; 433 /* fan control parameters */ 434 bool no_fan; 435 u8 fan_pulses_per_revolution; 436 u8 fan_min_rpm; 437 u8 fan_max_rpm; 438 /* dpm */ 439 bool dpm_enabled; 440 bool sysfs_initialized; 441 struct amdgpu_dpm dpm; 442 const struct firmware *fw; /* SMC firmware */ 443 uint32_t fw_version; 444 uint32_t pcie_gen_mask; 445 uint32_t pcie_mlw_mask; 446 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 447 uint32_t smu_prv_buffer_size; 448 struct amdgpu_bo *smu_prv_buffer; 449 bool ac_power; 450 /* powerplay feature */ 451 uint32_t pp_feature; 452 453 }; 454 455 #define R600_SSTU_DFLT 0 456 #define R600_SST_DFLT 0x00C8 457 458 /* XXX are these ok? */ 459 #define R600_TEMP_RANGE_MIN (90 * 1000) 460 #define R600_TEMP_RANGE_MAX (120 * 1000) 461 462 #define FDO_PWM_MODE_STATIC 1 463 #define FDO_PWM_MODE_STATIC_RPM 5 464 465 enum amdgpu_td { 466 AMDGPU_TD_AUTO, 467 AMDGPU_TD_UP, 468 AMDGPU_TD_DOWN, 469 }; 470 471 enum amdgpu_display_watermark { 472 AMDGPU_DISPLAY_WATERMARK_LOW = 0, 473 AMDGPU_DISPLAY_WATERMARK_HIGH = 1, 474 }; 475 476 enum amdgpu_display_gap 477 { 478 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 479 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, 480 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, 481 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, 482 }; 483 484 void amdgpu_dpm_print_class_info(u32 class, u32 class2); 485 void amdgpu_dpm_print_cap_info(u32 caps); 486 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 487 struct amdgpu_ps *rps); 488 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 489 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); 490 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev); 491 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 492 void *data, uint32_t *size); 493 494 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); 495 496 int amdgpu_get_platform_caps(struct amdgpu_device *adev); 497 498 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 499 void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 500 501 void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 502 503 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, 504 u32 sys_mask, 505 enum amdgpu_pcie_gen asic_gen, 506 enum amdgpu_pcie_gen default_gen); 507 508 struct amd_vce_state* 509 amdgpu_get_vce_clock_state(void *handle, u32 idx); 510 511 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 512 uint32_t block_type, bool gate); 513 514 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 515 516 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 517 518 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 519 uint32_t pstate); 520 521 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 522 enum PP_SMC_POWER_PROFILE type, 523 bool en); 524 525 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); 526 527 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); 528 529 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); 530 531 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 532 enum pp_mp1_state mp1_state); 533 534 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); 535 536 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); 537 538 #endif 539
Indexes created Sun Sep 21 19:09:51 GMT 2025