1 /* $NetBSD: amdgpu_smu.h,v 1.3 2021/12/19 12:21:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef __AMDGPU_SMU_H__ 25 #define __AMDGPU_SMU_H__ 26 27 #include "amdgpu.h" 28 #include "kgd_pp_interface.h" 29 #include "dm_pp_interface.h" 30 #include "dm_pp_smu.h" 31 #include "smu_types.h" 32 33 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 34 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 35 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 36 37 struct smu_hw_power_state { 38 unsigned int magic; 39 }; 40 41 struct smu_power_state; 42 43 enum smu_state_ui_label { 44 SMU_STATE_UI_LABEL_NONE, 45 SMU_STATE_UI_LABEL_BATTERY, 46 SMU_STATE_UI_TABEL_MIDDLE_LOW, 47 SMU_STATE_UI_LABEL_BALLANCED, 48 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 49 SMU_STATE_UI_LABEL_PERFORMANCE, 50 SMU_STATE_UI_LABEL_BACO, 51 }; 52 53 enum smu_state_classification_flag { 54 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 55 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 56 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 57 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 58 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 59 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 60 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 61 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 62 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 63 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 64 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 65 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 66 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 67 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 68 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 69 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 70 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 71 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 72 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 73 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 74 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 75 }; 76 77 struct smu_state_classification_block { 78 enum smu_state_ui_label ui_label; 79 enum smu_state_classification_flag flags; 80 int bios_index; 81 bool temporary_state; 82 bool to_be_deleted; 83 }; 84 85 struct smu_state_pcie_block { 86 unsigned int lanes; 87 }; 88 89 enum smu_refreshrate_source { 90 SMU_REFRESHRATE_SOURCE_EDID, 91 SMU_REFRESHRATE_SOURCE_EXPLICIT 92 }; 93 94 struct smu_state_display_block { 95 bool disable_frame_modulation; 96 bool limit_refreshrate; 97 enum smu_refreshrate_source refreshrate_source; 98 int explicit_refreshrate; 99 int edid_refreshrate_index; 100 bool enable_vari_bright; 101 }; 102 103 struct smu_state_memroy_block { 104 bool dll_off; 105 uint8_t m3arb; 106 uint8_t unused[3]; 107 }; 108 109 struct smu_state_software_algorithm_block { 110 bool disable_load_balancing; 111 bool enable_sleep_for_timestamps; 112 }; 113 114 struct smu_temperature_range { 115 int min; 116 int max; 117 int edge_emergency_max; 118 int hotspot_min; 119 int hotspot_crit_max; 120 int hotspot_emergency_max; 121 int mem_min; 122 int mem_crit_max; 123 int mem_emergency_max; 124 }; 125 126 struct smu_state_validation_block { 127 bool single_display_only; 128 bool disallow_on_dc; 129 uint8_t supported_power_levels; 130 }; 131 132 struct smu_uvd_clocks { 133 uint32_t vclk; 134 uint32_t dclk; 135 }; 136 137 /** 138 * Structure to hold a SMU Power State. 139 */ 140 struct smu_power_state { 141 uint32_t id; 142 struct list_head ordered_list; 143 struct list_head all_states_list; 144 145 struct smu_state_classification_block classification; 146 struct smu_state_validation_block validation; 147 struct smu_state_pcie_block pcie; 148 struct smu_state_display_block display; 149 struct smu_state_memroy_block memory; 150 struct smu_temperature_range temperatures; 151 struct smu_state_software_algorithm_block software; 152 struct smu_uvd_clocks uvd_clocks; 153 struct smu_hw_power_state hardware; 154 }; 155 156 enum smu_power_src_type 157 { 158 SMU_POWER_SOURCE_AC, 159 SMU_POWER_SOURCE_DC, 160 SMU_POWER_SOURCE_COUNT, 161 }; 162 163 enum smu_memory_pool_size 164 { 165 SMU_MEMORY_POOL_SIZE_ZERO = 0, 166 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 167 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 168 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 169 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 170 }; 171 172 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 173 do { \ 174 tables[table_id].size = s; \ 175 tables[table_id].align = a; \ 176 tables[table_id].domain = d; \ 177 } while (0) 178 179 struct smu_table { 180 uint64_t size; 181 uint32_t align; 182 uint8_t domain; 183 uint64_t mc_address; 184 void *cpu_addr; 185 struct amdgpu_bo *bo; 186 }; 187 188 enum smu_perf_level_designation { 189 PERF_LEVEL_ACTIVITY, 190 PERF_LEVEL_POWER_CONTAINMENT, 191 }; 192 193 struct smu_performance_level { 194 uint32_t core_clock; 195 uint32_t memory_clock; 196 uint32_t vddc; 197 uint32_t vddci; 198 uint32_t non_local_mem_freq; 199 uint32_t non_local_mem_width; 200 }; 201 202 struct smu_clock_info { 203 uint32_t min_mem_clk; 204 uint32_t max_mem_clk; 205 uint32_t min_eng_clk; 206 uint32_t max_eng_clk; 207 uint32_t min_bus_bandwidth; 208 uint32_t max_bus_bandwidth; 209 }; 210 211 struct smu_bios_boot_up_values 212 { 213 uint32_t revision; 214 uint32_t gfxclk; 215 uint32_t uclk; 216 uint32_t socclk; 217 uint32_t dcefclk; 218 uint32_t eclk; 219 uint32_t vclk; 220 uint32_t dclk; 221 uint16_t vddc; 222 uint16_t vddci; 223 uint16_t mvddc; 224 uint16_t vdd_gfx; 225 uint8_t cooling_id; 226 uint32_t pp_table_id; 227 uint32_t format_revision; 228 uint32_t content_revision; 229 uint32_t fclk; 230 }; 231 232 enum smu_table_id 233 { 234 SMU_TABLE_PPTABLE = 0, 235 SMU_TABLE_WATERMARKS, 236 SMU_TABLE_CUSTOM_DPM, 237 SMU_TABLE_DPMCLOCKS, 238 SMU_TABLE_AVFS, 239 SMU_TABLE_AVFS_PSM_DEBUG, 240 SMU_TABLE_AVFS_FUSE_OVERRIDE, 241 SMU_TABLE_PMSTATUSLOG, 242 SMU_TABLE_SMU_METRICS, 243 SMU_TABLE_DRIVER_SMU_CONFIG, 244 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 245 SMU_TABLE_OVERDRIVE, 246 SMU_TABLE_I2C_COMMANDS, 247 SMU_TABLE_PACE, 248 SMU_TABLE_COUNT, 249 }; 250 251 struct smu_table_context 252 { 253 const void *power_play_table; 254 uint32_t power_play_table_size; 255 void *hardcode_pptable; 256 unsigned long metrics_time; 257 void *metrics_table; 258 void *clocks_table; 259 void *watermarks_table; 260 261 void *max_sustainable_clocks; 262 struct smu_bios_boot_up_values boot_values; 263 void *driver_pptable; 264 struct smu_table *tables; 265 /* 266 * The driver table is just a staging buffer for 267 * uploading/downloading content from the SMU. 268 * 269 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 270 * SMU_MSG_TransferTableDram2Smu instructs SMU 271 * which content driver is interested. 272 */ 273 struct smu_table driver_table; 274 struct smu_table memory_pool; 275 uint8_t thermal_controller_type; 276 277 void *overdrive_table; 278 void *boot_overdrive_table; 279 }; 280 281 struct smu_dpm_context { 282 uint32_t dpm_context_size; 283 void *dpm_context; 284 void *golden_dpm_context; 285 bool enable_umd_pstate; 286 enum amd_dpm_forced_level dpm_level; 287 enum amd_dpm_forced_level saved_dpm_level; 288 enum amd_dpm_forced_level requested_dpm_level; 289 struct smu_power_state *dpm_request_power_state; 290 struct smu_power_state *dpm_current_power_state; 291 struct mclock_latency_table *mclk_latency_table; 292 }; 293 294 struct smu_power_gate { 295 bool uvd_gated; 296 bool vce_gated; 297 bool vcn_gated; 298 bool jpeg_gated; 299 }; 300 301 struct smu_power_context { 302 void *power_context; 303 uint32_t power_context_size; 304 struct smu_power_gate power_gate; 305 }; 306 307 308 #define SMU_FEATURE_MAX (64) 309 struct smu_feature 310 { 311 uint32_t feature_num; 312 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 313 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 314 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX); 315 struct mutex mutex; 316 }; 317 318 struct smu_clocks { 319 uint32_t engine_clock; 320 uint32_t memory_clock; 321 uint32_t bus_bandwidth; 322 uint32_t engine_clock_in_sr; 323 uint32_t dcef_clock; 324 uint32_t dcef_clock_in_sr; 325 }; 326 327 #define MAX_REGULAR_DPM_NUM 16 328 struct mclk_latency_entries { 329 uint32_t frequency; 330 uint32_t latency; 331 }; 332 struct mclock_latency_table { 333 uint32_t count; 334 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 335 }; 336 337 enum smu_reset_mode 338 { 339 SMU_RESET_MODE_0, 340 SMU_RESET_MODE_1, 341 SMU_RESET_MODE_2, 342 }; 343 344 enum smu_baco_state 345 { 346 SMU_BACO_STATE_ENTER = 0, 347 SMU_BACO_STATE_EXIT, 348 }; 349 350 struct smu_baco_context 351 { 352 struct mutex mutex; 353 uint32_t state; 354 bool platform_support; 355 }; 356 357 #define WORKLOAD_POLICY_MAX 7 358 struct smu_context 359 { 360 struct amdgpu_device *adev; 361 struct amdgpu_irq_src *irq_source; 362 363 const struct pptable_funcs *ppt_funcs; 364 struct mutex mutex; 365 struct mutex sensor_lock; 366 struct mutex metrics_lock; 367 uint64_t pool_size; 368 369 struct smu_table_context smu_table; 370 struct smu_dpm_context smu_dpm; 371 struct smu_power_context smu_power; 372 struct smu_feature smu_feature; 373 struct amd_pp_display_configuration *display_config; 374 struct smu_baco_context smu_baco; 375 void *od_settings; 376 377 uint32_t pstate_sclk; 378 uint32_t pstate_mclk; 379 380 bool od_enabled; 381 uint32_t power_limit; 382 uint32_t default_power_limit; 383 384 /* soft pptable */ 385 uint32_t ppt_offset_bytes; 386 uint32_t ppt_size_bytes; 387 uint8_t *ppt_start_addr; 388 389 bool support_power_containment; 390 bool disable_watermark; 391 392 #define WATERMARKS_EXIST (1 << 0) 393 #define WATERMARKS_LOADED (1 << 1) 394 uint32_t watermarks_bitmap; 395 uint32_t hard_min_uclk_req_from_dal; 396 bool disable_uclk_switch; 397 398 uint32_t workload_mask; 399 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 400 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 401 uint32_t power_profile_mode; 402 uint32_t default_power_profile_mode; 403 bool pm_enabled; 404 bool is_apu; 405 406 uint32_t smc_if_version; 407 408 bool uploading_custom_pp_table; 409 }; 410 411 struct i2c_adapter; 412 413 struct pptable_funcs { 414 int (*alloc_dpm_context)(struct smu_context *smu); 415 int (*store_powerplay_table)(struct smu_context *smu); 416 int (*check_powerplay_table)(struct smu_context *smu); 417 int (*append_powerplay_table)(struct smu_context *smu); 418 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index); 419 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index); 420 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index); 421 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index); 422 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index); 423 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile); 424 int (*run_btc)(struct smu_context *smu); 425 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 426 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 427 int (*set_default_dpm_table)(struct smu_context *smu); 428 int (*set_power_state)(struct smu_context *smu); 429 int (*populate_umd_state_clk)(struct smu_context *smu); 430 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 431 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 432 int (*set_default_od8_settings)(struct smu_context *smu); 433 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type); 434 int (*set_od_percentage)(struct smu_context *smu, 435 enum smu_clk_type clk_type, 436 uint32_t value); 437 int (*od_edit_dpm_table)(struct smu_context *smu, 438 enum PP_OD_DPM_TABLE_COMMAND type, 439 long *input, uint32_t size); 440 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 441 enum smu_clk_type clk_type, 442 struct 443 pp_clock_levels_with_latency 444 *clocks); 445 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 446 enum amd_pp_clock_type type, 447 struct 448 pp_clock_levels_with_voltage 449 *clocks); 450 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 451 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 452 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable); 453 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable); 454 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 455 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 456 void *data, uint32_t *size); 457 int (*pre_display_config_changed)(struct smu_context *smu); 458 int (*display_config_changed)(struct smu_context *smu); 459 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 460 int (*notify_smc_display_config)(struct smu_context *smu); 461 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest); 462 int (*unforce_dpm_levels)(struct smu_context *smu); 463 int (*get_profiling_clk_mask)(struct smu_context *smu, 464 enum amd_dpm_forced_level level, 465 uint32_t *sclk_mask, 466 uint32_t *mclk_mask, 467 uint32_t *soc_mask); 468 int (*set_cpu_power_state)(struct smu_context *smu); 469 bool (*is_dpm_running)(struct smu_context *smu); 470 int (*tables_init)(struct smu_context *smu, struct smu_table *tables); 471 int (*set_thermal_fan_table)(struct smu_context *smu); 472 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); 473 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 474 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, 475 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); 476 int (*get_current_clk_freq_by_table)(struct smu_context *smu, 477 enum smu_clk_type clk_type, 478 uint32_t *value); 479 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 480 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 481 int (*set_default_od_settings)(struct smu_context *smu, bool initialize); 482 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 483 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 484 void (*dump_pptable)(struct smu_context *smu); 485 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default); 486 int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type, 487 uint32_t dpm_level, uint32_t *freq); 488 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 489 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); 490 int (*i2c_eeprom_init)(struct i2c_adapter *control); 491 void (*i2c_eeprom_fini)(struct i2c_adapter *control); 492 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 493 int (*init_microcode)(struct smu_context *smu); 494 int (*load_microcode)(struct smu_context *smu); 495 int (*init_smc_tables)(struct smu_context *smu); 496 int (*fini_smc_tables)(struct smu_context *smu); 497 int (*init_power)(struct smu_context *smu); 498 int (*fini_power)(struct smu_context *smu); 499 int (*check_fw_status)(struct smu_context *smu); 500 int (*setup_pptable)(struct smu_context *smu); 501 int (*get_vbios_bootup_values)(struct smu_context *smu); 502 int (*get_clk_info_from_vbios)(struct smu_context *smu); 503 int (*check_pptable)(struct smu_context *smu); 504 int (*parse_pptable)(struct smu_context *smu); 505 int (*populate_smc_tables)(struct smu_context *smu); 506 int (*check_fw_version)(struct smu_context *smu); 507 int (*powergate_sdma)(struct smu_context *smu, bool gate); 508 int (*powergate_vcn)(struct smu_context *smu, bool gate); 509 int (*powergate_jpeg)(struct smu_context *smu, bool gate); 510 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 511 int (*write_pptable)(struct smu_context *smu); 512 int (*set_min_dcef_deep_sleep)(struct smu_context *smu); 513 int (*set_driver_table_location)(struct smu_context *smu); 514 int (*set_tool_table_location)(struct smu_context *smu); 515 int (*notify_memory_pool_location)(struct smu_context *smu); 516 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu); 517 int (*system_features_control)(struct smu_context *smu, bool en); 518 int (*send_smc_msg_with_param)(struct smu_context *smu, 519 enum smu_message_type msg, uint32_t param); 520 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg); 521 int (*init_display_count)(struct smu_context *smu, uint32_t count); 522 int (*set_allowed_mask)(struct smu_context *smu); 523 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 524 int (*notify_display_change)(struct smu_context *smu); 525 int (*set_power_limit)(struct smu_context *smu, uint32_t n); 526 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value); 527 int (*init_max_sustainable_clocks)(struct smu_context *smu); 528 int (*start_thermal_control)(struct smu_context *smu); 529 int (*stop_thermal_control)(struct smu_context *smu); 530 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk); 531 int (*set_active_display_count)(struct smu_context *smu, uint32_t count); 532 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time, 533 bool cc6_disable, bool pstate_disable, 534 bool pstate_switch_disable); 535 int (*get_clock_by_type)(struct smu_context *smu, 536 enum amd_pp_clock_type type, 537 struct amd_pp_clocks *clocks); 538 int (*get_max_high_clocks)(struct smu_context *smu, 539 struct amd_pp_simple_clock_info *clocks); 540 int (*display_clock_voltage_request)(struct smu_context *smu, struct 541 pp_display_clock_request 542 *clock_req); 543 int (*get_dal_power_level)(struct smu_context *smu, 544 struct amd_pp_simple_clock_info *clocks); 545 int (*get_perf_level)(struct smu_context *smu, 546 enum smu_perf_level_designation designation, 547 struct smu_performance_level *level); 548 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu, 549 struct smu_clock_info *clocks); 550 int (*notify_smu_enable_pwe)(struct smu_context *smu); 551 int (*conv_power_profile_to_pplib_workload)(int power_profile); 552 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 553 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 554 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed); 555 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 556 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 557 int (*gfx_off_control)(struct smu_context *smu, bool enable); 558 int (*register_irq_handler)(struct smu_context *smu); 559 int (*set_azalia_d3_pme)(struct smu_context *smu); 560 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 561 bool (*baco_is_support)(struct smu_context *smu); 562 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 563 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 564 int (*baco_enter)(struct smu_context *smu); 565 int (*baco_exit)(struct smu_context *smu); 566 int (*mode2_reset)(struct smu_context *smu); 567 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 568 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 569 int (*override_pcie_parameters)(struct smu_context *smu); 570 uint32_t (*get_pptable_power_limit)(struct smu_context *smu); 571 int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu); 572 }; 573 574 int smu_load_microcode(struct smu_context *smu); 575 576 int smu_check_fw_status(struct smu_context *smu); 577 578 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 579 580 #define smu_i2c_eeprom_init(smu, control) \ 581 ((smu)->ppt_funcs->i2c_eeprom_init ? (smu)->ppt_funcs->i2c_eeprom_init((control)) : -EINVAL) 582 #define smu_i2c_eeprom_fini(smu, control) \ 583 ((smu)->ppt_funcs->i2c_eeprom_fini ? (smu)->ppt_funcs->i2c_eeprom_fini((control)) : -EINVAL) 584 585 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed); 586 587 int smu_get_power_limit(struct smu_context *smu, 588 uint32_t *limit, 589 bool def, 590 bool lock_needed); 591 592 int smu_set_power_limit(struct smu_context *smu, uint32_t limit); 593 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 594 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type); 595 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value); 596 597 int smu_od_edit_dpm_table(struct smu_context *smu, 598 enum PP_OD_DPM_TABLE_COMMAND type, 599 long *input, uint32_t size); 600 601 int smu_read_sensor(struct smu_context *smu, 602 enum amd_pp_sensors sensor, 603 void *data, uint32_t *size); 604 int smu_get_power_profile_mode(struct smu_context *smu, char *buf); 605 606 int smu_set_power_profile_mode(struct smu_context *smu, 607 long *param, 608 uint32_t param_size, 609 bool lock_needed); 610 int smu_get_fan_control_mode(struct smu_context *smu); 611 int smu_set_fan_control_mode(struct smu_context *smu, int value); 612 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed); 613 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); 614 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed); 615 616 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk); 617 int smu_set_active_display_count(struct smu_context *smu, uint32_t count); 618 619 int smu_get_clock_by_type(struct smu_context *smu, 620 enum amd_pp_clock_type type, 621 struct amd_pp_clocks *clocks); 622 623 int smu_get_max_high_clocks(struct smu_context *smu, 624 struct amd_pp_simple_clock_info *clocks); 625 626 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 627 enum smu_clk_type clk_type, 628 struct pp_clock_levels_with_latency *clocks); 629 630 int smu_get_clock_by_type_with_voltage(struct smu_context *smu, 631 enum amd_pp_clock_type type, 632 struct pp_clock_levels_with_voltage *clocks); 633 634 int smu_display_clock_voltage_request(struct smu_context *smu, 635 struct pp_display_clock_request *clock_req); 636 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch); 637 int smu_notify_smu_enable_pwe(struct smu_context *smu); 638 639 int smu_set_xgmi_pstate(struct smu_context *smu, 640 uint32_t pstate); 641 642 int smu_set_azalia_d3_pme(struct smu_context *smu); 643 644 bool smu_baco_is_support(struct smu_context *smu); 645 646 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state); 647 648 int smu_baco_enter(struct smu_context *smu); 649 int smu_baco_exit(struct smu_context *smu); 650 651 int smu_mode2_reset(struct smu_context *smu); 652 653 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, 654 uint16_t *size, uint8_t *frev, uint8_t *crev, 655 uint8_t **addr); 656 657 extern const struct amd_ip_funcs smu_ip_funcs; 658 659 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 660 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 661 662 extern int smu_feature_init_dpm(struct smu_context *smu); 663 664 extern int smu_feature_is_enabled(struct smu_context *smu, 665 enum smu_feature_mask mask); 666 extern int smu_feature_set_enabled(struct smu_context *smu, 667 enum smu_feature_mask mask, bool enable); 668 extern int smu_feature_is_supported(struct smu_context *smu, 669 enum smu_feature_mask mask); 670 extern int smu_feature_set_supported(struct smu_context *smu, 671 enum smu_feature_mask mask, bool enable); 672 673 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument, 674 void *table_data, bool drv2smu); 675 676 bool is_support_sw_smu(struct amdgpu_device *adev); 677 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev); 678 int smu_reset(struct smu_context *smu); 679 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, 680 void *data, uint32_t *size); 681 int smu_sys_get_pp_table(struct smu_context *smu, const void **table); 682 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size); 683 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info); 684 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu); 685 int smu_write_watermarks_table(struct smu_context *smu); 686 int smu_set_watermarks_for_clock_ranges( 687 struct smu_context *smu, 688 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); 689 690 /* smu to display interface */ 691 extern int smu_display_configuration_change(struct smu_context *smu, const 692 struct amd_pp_display_configuration 693 *display_config); 694 extern int smu_get_current_clocks(struct smu_context *smu, 695 struct amd_pp_clock_info *clocks); 696 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate); 697 extern int smu_handle_task(struct smu_context *smu, 698 enum amd_dpm_forced_level level, 699 enum amd_pp_task task_id, 700 bool lock_needed); 701 int smu_switch_power_profile(struct smu_context *smu, 702 enum PP_SMC_POWER_PROFILE type, 703 bool en); 704 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version); 705 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, 706 uint16_t level, uint32_t *value); 707 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, 708 uint32_t *value); 709 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 710 uint32_t *min, uint32_t *max, bool lock_needed); 711 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 712 uint32_t min, uint32_t max); 713 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 714 uint32_t min, uint32_t max); 715 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type, 716 uint32_t *min_value, uint32_t *max_value); 717 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); 718 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); 719 int smu_set_display_count(struct smu_context *smu, uint32_t count); 720 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); 721 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type); 722 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature); 723 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf); 724 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); 725 int smu_force_clk_levels(struct smu_context *smu, 726 enum smu_clk_type clk_type, 727 uint32_t mask, 728 bool lock_needed); 729 int smu_set_mp1_state(struct smu_context *smu, 730 enum pp_mp1_state mp1_state); 731 int smu_set_df_cstate(struct smu_context *smu, 732 enum pp_df_cstate state); 733 734 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 735 struct pp_smu_nv_clock_table *max_clocks); 736 737 int smu_get_uclk_dpm_states(struct smu_context *smu, 738 unsigned int *clock_values_in_khz, 739 unsigned int *num_states); 740 741 int smu_get_dpm_clock_table(struct smu_context *smu, 742 struct dpm_clocks *clock_table); 743 744 uint32_t smu_get_pptable_power_limit(struct smu_context *smu); 745 746 #endif 747
Indexes created Sun Sep 21 15:09:59 GMT 2025