1 /* $NetBSD: bus_defs.h,v 1.2 2019/09/23 16:17:57 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _SPARC_BUS_DEFS_H_ 65 #define _SPARC_BUS_DEFS_H_ 66 67 /* 68 * Bus address and size types 69 */ 70 typedef u_long bus_space_handle_t; 71 72 #define PRIxBSH "lx" 73 74 typedef uint64_t bus_addr_t; 75 typedef u_long bus_size_t; 76 77 #define PRIxBUSADDR PRIx64 78 #define PRIxBUSSIZE "lx" 79 #define PRIuBUSSIZE "lu" 80 81 #define SPARC_BUS_SPACE 0 82 83 /* bus_addr_t is extended to 64-bits and has the iospace encoded in it */ 84 #define BUS_ADDR_IOSPACE(x) ((x)>>32) 85 #define BUS_ADDR_PADDR(x) ((x)&0xffffffff) 86 #define BUS_ADDR(io, pa) \ 87 ((((uint64_t)(uint32_t)(io))<<32) | (uint32_t)(pa)) 88 89 #define __BUS_SPACE_HAS_STREAM_METHODS 1 90 91 /* 92 * Access methods for bus resources and address space. 93 */ 94 typedef struct sparc_bus_space_tag *bus_space_tag_t; 95 96 struct sparc_bus_space_tag { 97 void *cookie; 98 bus_space_tag_t parent; 99 100 /* 101 * Windows onto the parent bus that this tag maps. If ranges 102 * is non-NULL, the address will be translated, and recursively 103 * mapped via the parent tag. 104 */ 105 struct openprom_range *ranges; 106 int nranges; 107 108 int (*sparc_bus_map)( 109 bus_space_tag_t, 110 bus_addr_t, 111 bus_size_t, 112 int, /*flags*/ 113 vaddr_t, /*preferred vaddr*/ 114 bus_space_handle_t *); 115 int (*sparc_bus_unmap)( 116 bus_space_tag_t, 117 bus_space_handle_t, 118 bus_size_t); 119 int (*sparc_bus_subregion)( 120 bus_space_tag_t, 121 bus_space_handle_t, 122 bus_size_t, /*offset*/ 123 bus_size_t, /*size*/ 124 bus_space_handle_t *); 125 126 void (*sparc_bus_barrier)( 127 bus_space_tag_t, 128 bus_space_handle_t, 129 bus_size_t, /*offset*/ 130 bus_size_t, /*size*/ 131 int); /*flags*/ 132 133 paddr_t (*sparc_bus_mmap)( 134 bus_space_tag_t, 135 bus_addr_t, 136 off_t, 137 int, /*prot*/ 138 int); /*flags*/ 139 140 void *(*sparc_intr_establish)( 141 bus_space_tag_t, 142 int, /*bus-specific intr*/ 143 int, /*device class level, 144 see machine/intr.h*/ 145 int (*)(void *), /*handler*/ 146 void *, /*handler arg*/ 147 void (*)(void)); /*optional fast vector*/ 148 149 uint8_t (*sparc_read_1)( 150 bus_space_tag_t space, 151 bus_space_handle_t handle, 152 bus_size_t offset); 153 154 uint16_t (*sparc_read_2)( 155 bus_space_tag_t space, 156 bus_space_handle_t handle, 157 bus_size_t offset); 158 159 uint32_t (*sparc_read_4)( 160 bus_space_tag_t space, 161 bus_space_handle_t handle, 162 bus_size_t offset); 163 164 uint64_t (*sparc_read_8)( 165 bus_space_tag_t space, 166 bus_space_handle_t handle, 167 bus_size_t offset); 168 169 void (*sparc_write_1)( 170 bus_space_tag_t space, 171 bus_space_handle_t handle, 172 bus_size_t offset, 173 uint8_t value); 174 175 void (*sparc_write_2)( 176 bus_space_tag_t space, 177 bus_space_handle_t handle, 178 bus_size_t offset, 179 uint16_t value); 180 181 void (*sparc_write_4)( 182 bus_space_tag_t space, 183 bus_space_handle_t handle, 184 bus_size_t offset, 185 uint32_t value); 186 187 void (*sparc_write_8)( 188 bus_space_tag_t space, 189 bus_space_handle_t handle, 190 bus_size_t offset, 191 uint64_t value); 192 }; 193 194 /* flags for bus space map functions */ 195 #define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */ 196 #define BUS_SPACE_MAP_BUS2 0x0200 197 #define BUS_SPACE_MAP_BUS3 0x0400 198 #define BUS_SPACE_MAP_LARGE 0x0800 /* map outside IODEV range */ 199 200 201 /* flags for bus_space_barrier() */ 202 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 203 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 204 205 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 206 207 /* 208 * Flags used in various bus DMA methods. 209 */ 210 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 211 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 212 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 213 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 214 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 215 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 216 #define BUS_DMA_BUS2 0x020 217 #define BUS_DMA_BUS3 0x040 218 #define BUS_DMA_BUS4 0x080 219 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 220 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 221 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 222 223 /* For devices that have a 24-bit address space */ 224 #define BUS_DMA_24BIT BUS_DMA_BUS1 225 226 /* Internal flag: current DVMA address is equal to the KVA buffer address */ 227 #define _BUS_DMA_DIRECTMAP BUS_DMA_BUS2 228 229 /* Forwards needed by prototypes below. */ 230 struct mbuf; 231 struct uio; 232 233 /* 234 * Operations performed by bus_dmamap_sync(). 235 */ 236 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 237 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 238 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 239 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 240 241 typedef struct sparc_bus_dma_tag *bus_dma_tag_t; 242 typedef struct sparc_bus_dmamap *bus_dmamap_t; 243 244 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 245 246 /* 247 * bus_dma_segment_t 248 * 249 * Describes a single contiguous DMA transaction. Values 250 * are suitable for programming into DMA registers. 251 */ 252 struct sparc_bus_dma_segment { 253 bus_addr_t ds_addr; /* DVMA address */ 254 bus_size_t ds_len; /* length of transfer */ 255 bus_size_t _ds_sgsize; /* size of allocated DVMA segment */ 256 void *_ds_mlist; /* page list when dmamem_alloc'ed */ 257 vaddr_t _ds_va; /* VA when dmamem_map'ed */ 258 }; 259 typedef struct sparc_bus_dma_segment bus_dma_segment_t; 260 261 262 /* 263 * bus_dma_tag_t 264 * 265 * A machine-dependent opaque type describing the implementation of 266 * DMA for a given bus. 267 */ 268 struct sparc_bus_dma_tag { 269 void *_cookie; /* cookie used in the guts */ 270 271 /* 272 * DMA mapping methods. 273 */ 274 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 275 bus_size_t, bus_size_t, int, bus_dmamap_t *); 276 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 277 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 278 bus_size_t, struct proc *, int); 279 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 280 struct mbuf *, int); 281 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 282 struct uio *, int); 283 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 284 bus_dma_segment_t *, int, bus_size_t, int); 285 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 286 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 287 bus_addr_t, bus_size_t, int); 288 289 /* 290 * DMA memory utility functions. 291 */ 292 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 293 bus_size_t, bus_dma_segment_t *, int, int *, int); 294 void (*_dmamem_free)(bus_dma_tag_t, 295 bus_dma_segment_t *, int); 296 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 297 int, size_t, void **, int); 298 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 299 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 300 int, off_t, int, int); 301 }; 302 303 /* 304 * bus_dmamap_t 305 * 306 * Describes a DMA mapping. 307 */ 308 struct sparc_bus_dmamap { 309 /* 310 * PRIVATE MEMBERS: not for use by machine-independent code. 311 */ 312 bus_size_t _dm_size; /* largest DMA transfer mappable */ 313 int _dm_segcnt; /* number of segs this map can map */ 314 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 315 bus_size_t _dm_boundary; /* don't cross this */ 316 int _dm_flags; /* misc. flags */ 317 318 void *_dm_cookie; /* cookie for bus-specific functions */ 319 320 u_long _dm_align; /* DVMA alignment; must be a 321 multiple of the page size */ 322 u_long _dm_ex_start; /* constraints on DVMA map */ 323 u_long _dm_ex_end; /* allocations; used by the VME bus 324 driver and by the IOMMU driver 325 when mapping 24-bit devices */ 326 327 /* 328 * PUBLIC MEMBERS: these are used by machine-independent code. 329 */ 330 bus_size_t dm_maxsegsz; /* largest possible segment */ 331 bus_size_t dm_mapsize; /* size of the mapping */ 332 int dm_nsegs; /* # valid segments in mapping */ 333 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 334 }; 335 336 #endif /* _SPARC_BUS_DEFS_H_ */ 337
Indexes created Sat Sep 20 22:09:52 GMT 2025