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    Searched defs:spll (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_clocks.c 47 struct radeon_pll *spll = &rdev->clock.spll; local in function:radeon_legacy_get_engine_clock
53 fb_div *= spll->reference_freq;
116 struct radeon_pll *spll = &rdev->clock.spll; local in function:radeon_read_clocks_OF
155 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
156 spll->reference_div = mpll->reference_div =
191 struct radeon_pll *spll = &rdev->clock.spll; local in function:radeon_get_clock_info
219 if (spll->reference_div < 2
360 struct radeon_pll *spll = &rdev->clock.spll; local in function:calc_eng_mem_clock
    [all...]
radeon_combios.c 744 struct radeon_pll *spll = &rdev->clock.spll; local in function:radeon_combios_get_clock_info
771 spll->reference_freq = RBIOS16(pll_info + 0x1a);
772 spll->reference_div = RBIOS16(pll_info + 0x1c);
773 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
774 spll->pll_out_max = RBIOS32(pll_info + 0x22);
777 spll->pll_in_min = RBIOS32(pll_info + 0x48);
778 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
781 spll->pll_in_min = 40;
782 spll->pll_in_max = 500
    [all...]
radeon_atombios.c 1143 struct radeon_pll *spll = &rdev->clock.spll; local in function:radeon_atom_get_clock_info
1196 spll->reference_freq =
1199 spll->reference_freq =
1201 spll->reference_div = 0;
1203 spll->pll_out_min =
1205 spll->pll_out_max =
1209 if (spll->pll_out_min == 0) {
1211 spll->pll_out_min = 64800;
1213 spll->pll_out_min = 20000
    [all...]
radeon.h 283 struct radeon_pll spll; member in struct:radeon_clock
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_nv40.c 41 u32 spll; member in struct:nv40_clk
180 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
183 clk->spll = 0x00000000;
198 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atomfirmware.c 350 struct amdgpu_pll *spll = &adev->clock.spll; local in function:amdgpu_atomfirmware_get_clock_info
388 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
390 spll->reference_div = 0;
391 spll->min_post_div = 1;
392 spll->max_post_div = 1;
393 spll->min_ref_div = 2;
394 spll->max_ref_div = 0xff;
395 spll->min_feedback_div = 4;
396 spll->max_feedback_div = 0xff
    [all...]
amdgpu_atombios.c 577 struct amdgpu_pll *spll = &adev->clock.spll; local in function:amdgpu_atombios_get_clock_info
623 spll->reference_freq =
625 spll->reference_div = 0;
627 spll->pll_out_min =
629 spll->pll_out_max =
633 if (spll->pll_out_min == 0)
634 spll->pll_out_min = 64800;
636 spll->pll_in_min =
638 spll->pll_in_max
    [all...]
amdgpu.h 342 struct amdgpu_pll spll; member in struct:amdgpu_clock
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 80 * @DPLL_ID_SPLL: HSW and BDW SPLL
179 u32 spll; member in struct:intel_dpll_hw_state

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