1 /* $NetBSD: grph_object_ctrl_defs.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__ 29 #define __DAL_GRPH_OBJECT_CTRL_DEFS_H__ 30 31 #include "grph_object_defs.h" 32 33 /* 34 * ##################################################### 35 * ##################################################### 36 * 37 * These defines shared between asic_control/bios_parser and other 38 * DAL components 39 * 40 * ##################################################### 41 * ##################################################### 42 */ 43 44 enum display_output_bit_depth { 45 PANEL_UNDEFINE = 0, 46 PANEL_6BIT_COLOR = 1, 47 PANEL_8BIT_COLOR = 2, 48 PANEL_10BIT_COLOR = 3, 49 PANEL_12BIT_COLOR = 4, 50 PANEL_16BIT_COLOR = 5, 51 }; 52 53 54 /* Device type as abstracted by ATOM BIOS */ 55 enum dal_device_type { 56 DEVICE_TYPE_UNKNOWN = 0, 57 DEVICE_TYPE_LCD, 58 DEVICE_TYPE_CRT, 59 DEVICE_TYPE_DFP, 60 DEVICE_TYPE_CV, 61 DEVICE_TYPE_TV, 62 DEVICE_TYPE_CF, 63 DEVICE_TYPE_WIRELESS 64 }; 65 66 /* Device ID as abstracted by ATOM BIOS */ 67 struct device_id { 68 enum dal_device_type device_type:16; 69 uint32_t enum_id:16; /* 1 based enum */ 70 uint16_t raw_device_tag; 71 }; 72 73 struct graphics_object_i2c_info { 74 struct gpio_info { 75 uint32_t clk_mask_register_index; 76 uint32_t clk_en_register_index; 77 uint32_t clk_y_register_index; 78 uint32_t clk_a_register_index; 79 uint32_t data_mask_register_index; 80 uint32_t data_en_register_index; 81 uint32_t data_y_register_index; 82 uint32_t data_a_register_index; 83 84 uint32_t clk_mask_shift; 85 uint32_t clk_en_shift; 86 uint32_t clk_y_shift; 87 uint32_t clk_a_shift; 88 uint32_t data_mask_shift; 89 uint32_t data_en_shift; 90 uint32_t data_y_shift; 91 uint32_t data_a_shift; 92 } gpio_info; 93 94 bool i2c_hw_assist; 95 uint32_t i2c_line; 96 uint32_t i2c_engine_id; 97 uint32_t i2c_slave_address; 98 }; 99 100 struct graphics_object_hpd_info { 101 uint8_t hpd_int_gpio_uid; 102 uint8_t hpd_active; 103 }; 104 105 struct connector_device_tag_info { 106 uint32_t acpi_device; 107 struct device_id dev_id; 108 }; 109 110 struct device_timing { 111 struct misc_info { 112 uint32_t HORIZONTAL_CUT_OFF:1; 113 /* 0=Active High, 1=Active Low */ 114 uint32_t H_SYNC_POLARITY:1; 115 /* 0=Active High, 1=Active Low */ 116 uint32_t V_SYNC_POLARITY:1; 117 uint32_t VERTICAL_CUT_OFF:1; 118 uint32_t H_REPLICATION_BY2:1; 119 uint32_t V_REPLICATION_BY2:1; 120 uint32_t COMPOSITE_SYNC:1; 121 uint32_t INTERLACE:1; 122 uint32_t DOUBLE_CLOCK:1; 123 uint32_t RGB888:1; 124 uint32_t GREY_LEVEL:2; 125 uint32_t SPATIAL:1; 126 uint32_t TEMPORAL:1; 127 uint32_t API_ENABLED:1; 128 } misc_info; 129 130 uint32_t pixel_clk; /* in KHz */ 131 uint32_t horizontal_addressable; 132 uint32_t horizontal_blanking_time; 133 uint32_t vertical_addressable; 134 uint32_t vertical_blanking_time; 135 uint32_t horizontal_sync_offset; 136 uint32_t horizontal_sync_width; 137 uint32_t vertical_sync_offset; 138 uint32_t vertical_sync_width; 139 uint32_t horizontal_border; 140 uint32_t vertical_border; 141 }; 142 143 struct supported_refresh_rate { 144 uint32_t REFRESH_RATE_30HZ:1; 145 uint32_t REFRESH_RATE_40HZ:1; 146 uint32_t REFRESH_RATE_48HZ:1; 147 uint32_t REFRESH_RATE_50HZ:1; 148 uint32_t REFRESH_RATE_60HZ:1; 149 }; 150 151 struct embedded_panel_info { 152 struct device_timing lcd_timing; 153 uint32_t ss_id; 154 struct supported_refresh_rate supported_rr; 155 uint32_t drr_enabled; 156 uint32_t min_drr_refresh_rate; 157 bool realtek_eDPToLVDS; 158 }; 159 160 struct dc_firmware_info { 161 struct pll_info { 162 uint32_t crystal_frequency; /* in KHz */ 163 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */ 164 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */ 165 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */ 166 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */ 167 } pll_info; 168 169 struct firmware_feature { 170 uint32_t memory_clk_ss_percentage; 171 uint32_t engine_clk_ss_percentage; 172 } feature; 173 174 uint32_t default_display_engine_pll_frequency; /* in KHz */ 175 uint32_t external_clock_source_frequency_for_dp; /* in KHz */ 176 uint32_t smu_gpu_pll_output_freq; /* in KHz */ 177 uint8_t min_allowed_bl_level; 178 uint8_t remote_display_config; 179 uint32_t default_memory_clk; /* in KHz */ 180 uint32_t default_engine_clk; /* in KHz */ 181 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */ 182 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */ 183 bool oem_i2c_present; 184 uint8_t oem_i2c_obj_id; 185 186 }; 187 188 struct step_and_delay_info { 189 uint32_t step; 190 uint32_t delay; 191 uint32_t recommended_ref_div; 192 }; 193 194 struct spread_spectrum_info { 195 struct spread_spectrum_type { 196 bool CENTER_MODE:1; 197 bool EXTERNAL:1; 198 bool STEP_AND_DELAY_INFO:1; 199 } type; 200 201 /* in unit of 0.01% (spreadPercentageDivider = 100), 202 otherwise in 0.001% units (spreadPercentageDivider = 1000); */ 203 uint32_t spread_spectrum_percentage; 204 uint32_t spread_percentage_divider; /* 100 or 1000 */ 205 uint32_t spread_spectrum_range; /* modulation freq (HZ)*/ 206 207 union { 208 struct step_and_delay_info step_and_delay_info; 209 /* For mem/engine/uvd, Clock Out frequence (VCO ), 210 in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock, 211 for DP, it is link clock ( 270000 or 162000 ) */ 212 uint32_t target_clock_range; /* in KHz */ 213 }; 214 215 }; 216 217 struct graphics_object_encoder_cap_info { 218 uint32_t dp_hbr2_cap:1; 219 uint32_t dp_hbr2_validated:1; 220 /* 221 * TODO: added MST and HDMI 6G capable flags 222 */ 223 uint32_t reserved:15; 224 }; 225 226 struct din_connector_info { 227 uint32_t gpio_id; 228 bool gpio_tv_active_state; 229 }; 230 231 /* Invalid channel mapping */ 232 enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 }; 233 234 /** 235 * DDI PHY channel mapping reflecting XBAR setting 236 */ 237 union ddi_channel_mapping { 238 struct mapping { 239 uint8_t lane0:2; /* Mapping for lane 0 */ 240 uint8_t lane1:2; /* Mapping for lane 1 */ 241 uint8_t lane2:2; /* Mapping for lane 2 */ 242 uint8_t lane3:2; /* Mapping for lane 3 */ 243 } mapping; 244 uint8_t raw; 245 }; 246 247 /** 248 * Transmitter output configuration description 249 */ 250 struct transmitter_configuration_info { 251 /* DDI PHY ID for the transmitter */ 252 enum transmitter transmitter_phy_id; 253 /* DDI PHY channel mapping reflecting crossbar setting */ 254 union ddi_channel_mapping output_channel_mapping; 255 }; 256 257 struct transmitter_configuration { 258 /* Configuration for the primary transmitter */ 259 struct transmitter_configuration_info primary_transmitter_config; 260 /* Secondary transmitter configuration for Dual-link DVI */ 261 struct transmitter_configuration_info secondary_transmitter_config; 262 }; 263 264 /* These size should be sufficient to store info coming from BIOS */ 265 #define NUMBER_OF_UCHAR_FOR_GUID 16 266 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 267 #define NUMBER_OF_CSR_M3_ARB 10 268 #define NUMBER_OF_DISP_CLK_VOLTAGE 4 269 #define NUMBER_OF_AVAILABLE_SCLK 5 270 271 struct i2c_reg_info { 272 unsigned char i2c_reg_index; 273 unsigned char i2c_reg_val; 274 }; 275 276 struct ext_hdmi_settings { 277 unsigned char slv_addr; 278 unsigned char reg_num; 279 struct i2c_reg_info reg_settings[9]; 280 unsigned char reg_num_6g; 281 struct i2c_reg_info reg_settings_6g[3]; 282 }; 283 284 285 /* V6 */ 286 struct integrated_info { 287 struct clock_voltage_caps { 288 /* The Voltage Index indicated by FUSE, same voltage index 289 shared with SCLK DPM fuse table */ 290 uint32_t voltage_index; 291 /* Maximum clock supported with specified voltage index */ 292 uint32_t max_supported_clk; /* in KHz */ 293 } disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE]; 294 295 struct display_connection_info { 296 struct external_display_path { 297 /* A bit vector to show what devices are supported */ 298 uint32_t device_tag; 299 /* 16bit device ACPI id. */ 300 uint32_t device_acpi_enum; 301 /* A physical connector for displays to plug in, 302 using object connector definitions */ 303 struct graphics_object_id device_connector_id; 304 /* An index into external AUX/DDC channel LUT */ 305 uint8_t ext_aux_ddc_lut_index; 306 /* An index into external HPD pin LUT */ 307 uint8_t ext_hpd_pin_lut_index; 308 /* external encoder object id */ 309 struct graphics_object_id ext_encoder_obj_id; 310 /* XBAR mapping of the PHY channels */ 311 union ddi_channel_mapping channel_mapping; 312 313 unsigned short caps; 314 } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; 315 316 uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID]; 317 uint8_t checksum; 318 } ext_disp_conn_info; /* exiting long long time */ 319 320 struct available_s_clk_list { 321 /* Maximum clock supported with specified voltage index */ 322 uint32_t supported_s_clk; /* in KHz */ 323 /* The Voltage Index indicated by FUSE for specified SCLK */ 324 uint32_t voltage_index; 325 /* The Voltage ID indicated by FUSE for specified SCLK */ 326 uint32_t voltage_id; 327 } avail_s_clk[NUMBER_OF_AVAILABLE_SCLK]; 328 329 uint8_t memory_type; 330 uint8_t ma_channel_number; 331 uint32_t boot_up_engine_clock; /* in KHz */ 332 uint32_t dentist_vco_freq; /* in KHz */ 333 uint32_t boot_up_uma_clock; /* in KHz */ 334 uint32_t boot_up_req_display_vector; 335 uint32_t other_display_misc; 336 uint32_t gpu_cap_info; 337 uint32_t sb_mmio_base_addr; 338 uint32_t system_config; 339 uint32_t cpu_cap_info; 340 uint32_t max_nb_voltage; 341 uint32_t min_nb_voltage; 342 uint32_t boot_up_nb_voltage; 343 uint32_t ext_disp_conn_info_offset; 344 uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB]; 345 uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB]; 346 uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB]; 347 uint32_t gmc_restore_reset_time; 348 uint32_t minimum_n_clk; 349 uint32_t idle_n_clk; 350 uint32_t ddr_dll_power_up_time; 351 uint32_t ddr_pll_power_up_time; 352 /* start for V6 */ 353 uint32_t pcie_clk_ss_type; 354 uint32_t lvds_ss_percentage; 355 uint32_t lvds_sspread_rate_in_10hz; 356 uint32_t hdmi_ss_percentage; 357 uint32_t hdmi_sspread_rate_in_10hz; 358 uint32_t dvi_ss_percentage; 359 uint32_t dvi_sspread_rate_in_10_hz; 360 uint32_t sclk_dpm_boost_margin; 361 uint32_t sclk_dpm_throttle_margin; 362 uint32_t sclk_dpm_tdp_limit_pg; 363 uint32_t sclk_dpm_tdp_limit_boost; 364 uint32_t boost_engine_clock; 365 uint32_t boost_vid_2bit; 366 uint32_t enable_boost; 367 uint32_t gnb_tdp_limit; 368 /* Start from V7 */ 369 uint32_t max_lvds_pclk_freq_in_single_link; 370 uint32_t lvds_misc; 371 uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms; 372 uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms; 373 uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms; 374 uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms; 375 uint32_t lvds_off_to_on_delay_in_4ms; 376 uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms; 377 uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms; 378 uint32_t lvds_reserved1; 379 uint32_t lvds_bit_depth_control_val; 380 //Start from V9 381 unsigned char dp0_ext_hdmi_slv_addr; 382 unsigned char dp0_ext_hdmi_reg_num; 383 struct i2c_reg_info dp0_ext_hdmi_reg_settings[9]; 384 unsigned char dp0_ext_hdmi_6g_reg_num; 385 struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3]; 386 unsigned char dp1_ext_hdmi_slv_addr; 387 unsigned char dp1_ext_hdmi_reg_num; 388 struct i2c_reg_info dp1_ext_hdmi_reg_settings[9]; 389 unsigned char dp1_ext_hdmi_6g_reg_num; 390 struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3]; 391 unsigned char dp2_ext_hdmi_slv_addr; 392 unsigned char dp2_ext_hdmi_reg_num; 393 struct i2c_reg_info dp2_ext_hdmi_reg_settings[9]; 394 unsigned char dp2_ext_hdmi_6g_reg_num; 395 struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3]; 396 unsigned char dp3_ext_hdmi_slv_addr; 397 unsigned char dp3_ext_hdmi_reg_num; 398 struct i2c_reg_info dp3_ext_hdmi_reg_settings[9]; 399 unsigned char dp3_ext_hdmi_6g_reg_num; 400 struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3]; 401 /* V11 */ 402 uint32_t dp_ss_control; 403 }; 404 405 /** 406 * Power source ids. 407 */ 408 enum power_source { 409 POWER_SOURCE_AC = 0, 410 POWER_SOURCE_DC, 411 POWER_SOURCE_LIMITED_POWER, 412 POWER_SOURCE_LIMITED_POWER_2, 413 POWER_SOURCE_MAX 414 }; 415 416 struct bios_event_info { 417 uint32_t thermal_state; 418 uint32_t backlight_level; 419 enum power_source powerSource; 420 bool has_thermal_state_changed; 421 bool has_power_source_changed; 422 bool has_forced_mode_changed; 423 bool forced_mode; 424 bool backlight_changed; 425 }; 426 427 /* 428 * DFS-bypass flag 429 */ 430 /* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */ 431 enum { 432 DFS_BYPASS_ENABLE = 0x10 433 }; 434 435 enum { 436 INVALID_BACKLIGHT = -1 437 }; 438 439 struct panel_backlight_boundaries { 440 uint32_t min_signal_level; 441 uint32_t max_signal_level; 442 }; 443 444 445 #endif 446
Indexes created Sun Sep 21 15:09:59 GMT 2025