| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/ |
| tu_meta_copy.c | 125 uint64_t src_va = src_bo->iova + src_offset; local
128 unsigned src_shift = src_va & 0x3f;
132 src_va -= src_shift;
149 tu_cs_emit_qw(&cmdbuf->cs, src_va);
233 uint64_t src_va)
245 assert(src_va % vk_format_get_blocksize(format) == 0);
247 src_offset = (src_va & 63) / vk_format_get_blocksize(format);
248 src_va &= ~63;
257 assert(!(src_va & 63));
274 tu_cs_emit_qw(&cmdbuf->cs, src_va);
380 uint64_t src_va = src_buffer->bo->iova + src_buffer->bo_offset + copy_info->bufferOffset + layer_offset * copy_info->bufferImageHeight * src_pitch; local
428 uint64_t src_va = src_image->bo->iova + src_image->bo_offset + src_image->layer_size * layer + src_image->levels[copy_info->imageSubresource.mipLevel].offset; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_meta_buffer.c | 347 uint64_t src_va = radv_buffer_get_va(src_bo); local
349 src_va += src_offset;
355 si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
|
| radv_query.c | 1247 uint64_t src_va = va + query * pool->stride + rb_avail_offset; local
1252 radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va, 0x80000000, 0xffffffff);
1306 uint64_t src_va = va + query * pool->stride; local
1311 for (unsigned j = 0; j < 4; j++, src_va += 8) {
1312 radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va + 4, 0x80000000,
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_cp_dma.c | 53 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
57 uint64_t src_va, unsigned size, unsigned flags,
78 if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) && src_va == dst_va) {
105 radeon_emit(src_va); /* SRC_ADDR_LO [31:0] */
106 radeon_emit(src_va >> 32); /* SRC_ADDR_HI [31:0] */
111 header |= S_411_SRC_ADDR_HI(src_va >> 32);
114 radeon_emit(src_va); /* SRC_ADDR_LO [31:0] */
515 uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset; local
520 radeon_emit(src_va);
521 radeon_emit(src_va >> 32)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_meta_buffer.c | 441 uint64_t src_va = radv_buffer_get_va(src_bo); local
443 src_va += src_offset;
449 si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
|
| radv_query.c | 1314 uint64_t src_va = va + query * pool->stride + pool->stride - 4; local
1320 src_va, 0x80000000, 0xffffffff);
1396 uint64_t src_va = va + query * pool->stride; local
1401 for (unsigned j = 0; j < 4; j++, src_va += 8) {
1403 src_va + 4, 0x80000000,
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_cp_dma.c | 54 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
58 uint64_t dst_va, uint64_t src_va, unsigned size,
86 src_va == dst_va) {
113 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
114 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
119 header |= S_411_SRC_ADDR_HI(src_va >> 32);
122 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
626 uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset; local
632 radeon_emit(cs, src_va);
633 radeon_emit(cs, src_va >> 32)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_clear_blit.c | 1536 uint64_t src_va = tu_buffer_iova(src_buffer) + info->bufferOffset + layer_size * i; local
1537 if ((src_va & 63) || (pitch & 63)) {
1539 uint32_t x = (src_va & 63) / vk_format_get_blocksize(src_format);
1540 ops->src_buffer(cmd, cs, src_format, src_va & ~63, pitch,
1545 src_va += pitch;
1548 ops->src_buffer(cmd, cs, src_format, src_va, pitch, extent.width, extent.height);
1880 uint64_t src_va,
1893 uint32_t src_x = (src_va & 63) / block_size;
1897 ops->src_buffer(cmd, cs, format, src_va & ~63, 0, src_x + width, 1);
1902 src_va += width * block_size
[all...] |
