1 /* $NetBSD: tga.c,v 1.93 2024/02/09 22:08:36 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.93 2024/02/09 22:08:36 andvar Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/pci/wsdisplay_pci.h> 62 63 static int tgamatch(device_t, cfdata_t, void *); 64 static void tgaattach(device_t, device_t, void *); 65 66 CFATTACH_DECL_NEW(tga, sizeof(struct tga_softc), 67 tgamatch, tgaattach, NULL, NULL); 68 69 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 70 pcitag_t tag, struct tga_devconfig *dc); 71 72 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 73 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 74 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 75 static unsigned int tga_getdotclock(struct tga_devconfig *dc); 76 77 static int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 78 static paddr_t tga_mmap(void *, void *, off_t, int); 79 static void tga_copyrows(void *, int, int, int); 80 static void tga_copycols(void *, int, int, int, int); 81 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 82 void **, int *, int *, long *); 83 static void tga_free_screen(void *, void *); 84 static int tga_show_screen(void *, void *, int, 85 void (*) (void *, int, int), void *); 86 static int tga_rop(struct rasops_info *, int, int, int, int, int, 87 struct rasops_info *, int, int); 88 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 89 int, struct rasops_info *, int, int); 90 static void tga_putchar(void *c, int row, int col, u_int uc, long attr); 91 static void tga_eraserows(void *, int, int, long); 92 static void tga_erasecols(void *, int, int, int, long); 93 static void tga2_init(struct tga_devconfig *); 94 95 static void tga_config_interrupts(device_t); 96 97 /* RAMDAC interface functions */ 98 static int tga_sched_update(void *, void (*)(void *)); 99 static void tga_ramdac_wr(void *, u_int, uint8_t); 100 static uint8_t tga_ramdac_rd(void *, u_int); 101 static void tga_bt463_wr(void *, u_int, uint8_t); 102 static uint8_t tga_bt463_rd(void *, u_int); 103 static void tga2_ramdac_wr(void *, u_int, uint8_t); 104 static uint8_t tga2_ramdac_rd(void *, u_int); 105 106 /* Interrupt handler */ 107 static int tga_intr(void *); 108 109 struct tga_devconfig tga_console_dc; 110 111 /* The NULL entries will get filled in by rasops_init(). 112 * XXX and the non-NULL ones will be overwritten; reset after calling it. 113 */ 114 struct wsdisplay_emulops tga_emulops = { 115 .cursor = NULL, 116 .mapchar = NULL, 117 .putchar = tga_putchar, 118 .copycols = tga_copycols, 119 .erasecols = tga_erasecols, 120 .copyrows = tga_copyrows, 121 .eraserows = tga_eraserows, 122 .allocattr = NULL, 123 NULL, 124 }; 125 126 struct wsscreen_descr tga_stdscreen = { 127 .name = "std", 128 .ncols = 0, 129 .nrows = 0, /* will be filled in -- XXX shouldn't, it's global */ 130 .textops = &tga_emulops, 131 .fontwidth = 0, 132 .fontheight = 0, 133 .capabilities = WSSCREEN_REVERSE, 134 .modecookie = NULL, 135 }; 136 137 const struct wsscreen_descr *_tga_scrlist[] = { 138 &tga_stdscreen, 139 /* XXX other formats, graphics screen? */ 140 }; 141 142 struct wsscreen_list tga_screenlist = { 143 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 144 }; 145 146 struct wsdisplay_accessops tga_accessops = { 147 .ioctl = tga_ioctl, 148 .mmap = tga_mmap, 149 .alloc_screen = tga_alloc_screen, 150 .free_screen = tga_free_screen, 151 .show_screen = tga_show_screen, 152 .load_font = NULL, 153 .pollc = NULL, 154 .scroll = NULL, 155 }; 156 157 static void tga_blank(struct tga_devconfig *); 158 static void tga_unblank(struct tga_devconfig *); 159 160 int 161 tga_cnmatch(bus_space_tag_t iot, bus_space_tag_t memt, 162 pci_chipset_tag_t pc, pcitag_t tag) 163 { 164 165 return tga_matchcommon(memt, pc, tag); 166 } 167 168 static int 169 tgamatch(device_t parent, cfdata_t match, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 173 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 174 return (0); 175 176 switch (PCI_PRODUCT(pa->pa_id)) { 177 case PCI_PRODUCT_DEC_21030: 178 case PCI_PRODUCT_DEC_PBXGB: 179 break; 180 default: 181 return 0; 182 } 183 184 #if defined(__alpha__) || defined(arc) 185 /* short-circuit the following test, as we 186 * already have the memory mapped and hence 187 * cannot perform it---and we are the console 188 * anyway. 189 */ 190 if (pa->pa_tag == tga_console_dc.dc_pcitag) 191 return 10; 192 #endif 193 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 194 } 195 196 static int 197 tga_matchcommon(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 198 { 199 struct tga_devconfig tmp_dc; 200 struct tga_devconfig *dc = &tmp_dc; 201 bus_size_t pcisize; 202 203 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 204 dc->dc_tga_type = tga_identify(dc); 205 206 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 207 bus_space_unmap(memt, dc->dc_memh, pcisize); 208 if (dc->dc_tgaconf) 209 return 10; 210 return 0; 211 } 212 213 static void 214 tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 215 bus_size_t *pcisize, struct tga_devconfig *dc) 216 { 217 int flags; 218 219 dc->dc_memt = memt; 220 dc->dc_tgaconf = NULL; 221 222 /* XXX magic number */ 223 if (pci_mapreg_info(pc, tag, 0x10, 224 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 225 &dc->dc_pcipaddr, pcisize, &flags)) 226 panic("tga_mapaddrs: pci_mapreg_info() failed"); 227 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 228 panic("tga memory not prefetchable"); 229 230 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 231 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 232 panic("tga_mapaddrs: could not map TGA address space"); 233 dc->dc_vaddr = (vaddr_t)bus_space_vaddr(memt, dc->dc_memh); 234 235 bus_space_subregion(dc->dc_memt, dc->dc_memh, 236 TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs); 237 } 238 239 static void 240 tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 241 struct tga_devconfig *dc) 242 { 243 const struct tga_conf *tgac; 244 struct rasops_info *rip; 245 int cookie; 246 bus_size_t pcisize; 247 int i; 248 249 dc->dc_pc = pc; 250 dc->dc_pcitag = tag; 251 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 252 dc->dc_tga_type = tga_identify(dc); 253 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 254 #if 0 255 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 256 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 257 panic("tga_init: memory size mismatch?"); 258 #endif 259 260 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 261 case 0x01: 262 case 0x02: 263 case 0x03: 264 case 0x04: 265 dc->dc_tga2 = 0; 266 break; 267 case 0x20: 268 case 0x21: 269 case 0x22: 270 dc->dc_tga2 = 1; 271 break; 272 default: 273 panic("tga_init: TGA Revision not recognized"); 274 } 275 276 if (dc->dc_tga2) 277 tga2_init(dc); 278 279 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 280 case 0: 281 dc->dc_wid = 8192; 282 break; 283 284 case 1: 285 dc->dc_wid = 8196; 286 break; 287 288 default: 289 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 290 break; 291 } 292 293 /* 294 * XXX XXX Turning off "odd" shouldn't be necessary, 295 * XXX XXX but I can't make X work with the weird size. 296 */ 297 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 298 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 299 TGAWREG(dc, TGA_REG_VHCR, 300 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 301 dc->dc_wid -= 4; 302 } 303 304 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 305 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 306 307 /* XXX this seems to be what DEC does */ 308 TGAWREG(dc, TGA_REG_CCBR, 0); 309 TGAWREG(dc, TGA_REG_VVBR, 1); 310 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 311 1 * tgac->tgac_vvbr_units; 312 dc->dc_blanked = 1; 313 tga_unblank(dc); 314 315 /* 316 * Set all bits in the pixel mask, to enable writes to all pixels. 317 * It seems that the console firmware clears some of them 318 * under some circumstances, which causes cute vertical stripes. 319 */ 320 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 321 322 /* clear the screen */ 323 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(uint32_t)) 324 *(uint32_t *)(dc->dc_videobase + i) = 0; 325 326 /* Initialize rasops descriptor */ 327 rip = &dc->dc_rinfo; 328 rip->ri_flg = RI_CENTER; 329 rip->ri_depth = tgac->tgac_phys_depth; 330 rip->ri_bits = (void *)dc->dc_videobase; 331 rip->ri_width = dc->dc_wid; 332 rip->ri_height = dc->dc_ht; 333 rip->ri_stride = dc->dc_rowbytes; 334 rip->ri_hw = dc; 335 if (dc == &tga_console_dc) 336 rip->ri_flg |= RI_NO_AUTO; 337 338 if (tgac->tgac_phys_depth == 32) { 339 rip->ri_rnum = 8; 340 rip->ri_gnum = 8; 341 rip->ri_bnum = 8; 342 rip->ri_rpos = 16; 343 rip->ri_gpos = 8; 344 rip->ri_bpos = 0; 345 } 346 347 wsfont_init(); 348 /* prefer 8 pixel wide font */ 349 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 350 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 351 if (cookie <= 0) 352 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 353 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 354 if (cookie <= 0) { 355 printf("tga: no appropriate fonts.\n"); 356 return; 357 } 358 359 /* the accelerated tga_putchar() needs LSbit left */ 360 if (wsfont_lock(cookie, &rip->ri_font)) { 361 printf("tga: couldn't lock font\n"); 362 return; 363 } 364 rip->ri_wsfcookie = cookie; 365 366 rasops_init(rip, 34, 80); 367 368 /* add our accelerated functions */ 369 /* XXX shouldn't have to do this; rasops should leave non-NULL 370 * XXX entries alone. 371 */ 372 rip->ri_ops.copyrows = tga_copyrows; 373 rip->ri_ops.eraserows = tga_eraserows; 374 rip->ri_ops.erasecols = tga_erasecols; 375 rip->ri_ops.copycols = tga_copycols; 376 rip->ri_ops.putchar = tga_putchar; 377 378 tga_stdscreen.nrows = rip->ri_rows; 379 tga_stdscreen.ncols = rip->ri_cols; 380 tga_stdscreen.textops = &rip->ri_ops; 381 tga_stdscreen.capabilities = rip->ri_caps; 382 383 384 dc->dc_intrenabled = 0; 385 } 386 387 static void 388 tgaattach(device_t parent, device_t self, void *aux) 389 { 390 struct pci_attach_args *pa = aux; 391 struct tga_softc *sc = device_private(self); 392 struct tga_devconfig *dc; 393 struct wsemuldisplaydev_attach_args aa; 394 pci_intr_handle_t intrh; 395 const char *intrstr; 396 uint8_t rev; 397 int console; 398 char intrbuf[PCI_INTRSTR_LEN]; 399 400 sc->sc_dev = self; 401 402 #if defined(__alpha__) || defined(arc) 403 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 404 #else 405 console = 0; 406 #endif 407 if (console) { 408 sc->sc_dc = &tga_console_dc; 409 sc->sc_dc->dc_rinfo.ri_flg &= ~RI_NO_AUTO; 410 sc->nscreens = 1; 411 } else { 412 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 413 M_WAITOK|M_ZERO); 414 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 415 } 416 if (sc->sc_dc->dc_vaddr == 0) { 417 aprint_error(": couldn't map memory space; punt!\n"); 418 return; 419 } 420 421 /* XXX say what's going on. */ 422 intrstr = NULL; 423 if (pci_intr_map(pa, &intrh)) { 424 aprint_error(": couldn't map interrupt"); 425 return; 426 } 427 intrstr = pci_intr_string(pa->pa_pc, intrh, intrbuf, sizeof(intrbuf)); 428 sc->sc_intr = pci_intr_establish_xname(pa->pa_pc, intrh, IPL_TTY, 429 tga_intr, sc->sc_dc, device_xname(self)); 430 if (sc->sc_intr == NULL) { 431 aprint_error(": couldn't establish interrupt"); 432 if (intrstr != NULL) 433 aprint_error("at %s", intrstr); 434 aprint_error("\n"); 435 return; 436 } 437 438 rev = PCI_REVISION(pa->pa_class); 439 switch (rev) { 440 case 0x1: 441 case 0x2: 442 case 0x3: 443 aprint_normal(": DC21030 step %c", 'A' + rev - 1); 444 break; 445 case 0x20: 446 aprint_normal(": TGA2 abstract software model"); 447 break; 448 case 0x21: 449 case 0x22: 450 aprint_normal(": TGA2 pass %d", rev - 0x20); 451 break; 452 453 default: 454 aprint_normal("unknown stepping (0x%x)", rev); 455 break; 456 } 457 aprint_normal(", "); 458 459 /* 460 * Get RAMDAC function vectors and call the RAMDAC functions 461 * to allocate its private storage and pass that back to us. 462 */ 463 464 dc = sc->sc_dc; 465 dc->dc_ramdac_funcs = dc->dc_tgaconf->ramdac_funcs(); 466 if (!dc->dc_tga2) { 467 if (dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 468 dc->dc_ramdac_cookie = 469 dc->dc_ramdac_funcs->ramdac_register(dc, 470 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 471 else 472 dc->dc_ramdac_cookie = 473 dc->dc_ramdac_funcs->ramdac_register(dc, 474 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 475 } else { 476 dc->dc_ramdac_cookie = dc->dc_ramdac_funcs->ramdac_register(dc, 477 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 478 479 /* XXX this is a bit of a hack, setting the dotclock here */ 480 if (dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 481 (*dc->dc_ramdac_funcs->ramdac_set_dotclock) 482 (dc->dc_ramdac_cookie, tga_getdotclock(dc)); 483 } 484 485 /* 486 * Initialize the RAMDAC. Initialization includes disabling 487 * cursor, setting a sane colormap, etc. We presume that we've 488 * filled in the necessary dot clock for PowerStorm 4d20. 489 */ 490 (*dc->dc_ramdac_funcs->ramdac_init)(dc->dc_ramdac_cookie); 491 TGAWREG(dc, TGA_REG_SISR, 0x00000001); /* XXX */ 492 493 if (dc->dc_tgaconf == NULL) { 494 aprint_error("unknown board configuration\n"); 495 return; 496 } 497 aprint_normal("board type %s\n", dc->dc_tgaconf->tgac_name); 498 aprint_normal_dev(self, "%d x %d, %dbpp, %s RAMDAC\n", 499 dc->dc_wid, dc->dc_ht, 500 dc->dc_tgaconf->tgac_phys_depth, 501 dc->dc_ramdac_funcs->ramdac_name); 502 503 if (intrstr != NULL) 504 aprint_normal_dev(self, "interrupting at %s\n", 505 intrstr); 506 507 aa.console = console; 508 aa.scrdata = &tga_screenlist; 509 aa.accessops = &tga_accessops; 510 aa.accesscookie = sc; 511 512 config_found(self, &aa, wsemuldisplaydevprint, CFARGS_NONE); 513 514 config_interrupts(self, tga_config_interrupts); 515 } 516 517 static void 518 tga_config_interrupts(device_t self) 519 { 520 struct tga_softc *sc; 521 522 sc = device_private(self); 523 sc->sc_dc->dc_intrenabled = 1; 524 } 525 526 static int 527 tga_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 528 { 529 struct tga_softc *sc = v; 530 struct tga_devconfig *dc = sc->sc_dc; 531 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 532 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 533 534 switch (cmd) { 535 case WSDISPLAYIO_GTYPE: 536 *(u_int *)data = WSDISPLAY_TYPE_TGA; 537 return 0; 538 539 case WSDISPLAYIO_GINFO: 540 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 541 wsd_fbip->height = sc->sc_dc->dc_ht; 542 wsd_fbip->width = sc->sc_dc->dc_wid; 543 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 544 #if 0 545 wsd_fbip->cmsize = 256; /* XXX ??? */ 546 #else 547 wsd_fbip->cmsize = 1024; /* XXX ??? */ 548 #endif 549 #undef wsd_fbip 550 return 0; 551 552 case WSDISPLAYIO_GETCMAP: 553 return (*dcrf->ramdac_get_cmap)(dcrc, 554 (struct wsdisplay_cmap *)data); 555 556 case WSDISPLAYIO_PUTCMAP: 557 return (*dcrf->ramdac_set_cmap)(dcrc, 558 (struct wsdisplay_cmap *)data); 559 560 case WSDISPLAYIO_SVIDEO: 561 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 562 tga_blank(sc->sc_dc); 563 else 564 tga_unblank(sc->sc_dc); 565 return 0; 566 567 case WSDISPLAYIO_GVIDEO: 568 *(u_int *)data = dc->dc_blanked ? 569 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 570 return 0; 571 572 case WSDISPLAYIO_GCURPOS: 573 return (*dcrf->ramdac_get_curpos)(dcrc, 574 (struct wsdisplay_curpos *)data); 575 576 case WSDISPLAYIO_SCURPOS: 577 return (*dcrf->ramdac_set_curpos)(dcrc, 578 (struct wsdisplay_curpos *)data); 579 580 case WSDISPLAYIO_GCURMAX: 581 return (*dcrf->ramdac_get_curmax)(dcrc, 582 (struct wsdisplay_curpos *)data); 583 584 case WSDISPLAYIO_GCURSOR: 585 return (*dcrf->ramdac_get_cursor)(dcrc, 586 (struct wsdisplay_cursor *)data); 587 588 case WSDISPLAYIO_SCURSOR: 589 return (*dcrf->ramdac_set_cursor)(dcrc, 590 (struct wsdisplay_cursor *)data); 591 592 case WSDISPLAYIO_LINEBYTES: 593 *(u_int *)data = dc->dc_rowbytes; 594 return 0; 595 596 /* PCI config read/write passthrough. */ 597 case PCI_IOC_CFGREAD: 598 case PCI_IOC_CFGWRITE: 599 return pci_devioctl(dc->dc_pc, dc->dc_pcitag, 600 cmd, data, flag, l); 601 602 case WSDISPLAYIO_GET_BUSID: 603 return wsdisplayio_busid_pci(sc->sc_dev, dc->dc_pc, 604 dc->dc_pcitag, data); 605 } 606 return EPASSTHROUGH; 607 } 608 609 static int 610 tga_sched_update(void *v, void (*f)(void *)) 611 { 612 struct tga_devconfig *dc = v; 613 614 if (dc->dc_intrenabled) { 615 /* 616 * Arrange for f to be called at the next end-of-frame 617 * interrupt. 618 */ 619 dc->dc_ramdac_intr = f; 620 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 621 } else { 622 /* Spin until the end-of-frame, then call f */ 623 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 624 TGAREGWB(dc, TGA_REG_SISR, 1); 625 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 626 continue; 627 f(dc->dc_ramdac_cookie); 628 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 629 TGAREGWB(dc, TGA_REG_SISR, 1); 630 } 631 632 return 0; 633 } 634 635 static int 636 tga_intr(void *v) 637 { 638 struct tga_devconfig *dc = v; 639 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 640 641 uint32_t reg; 642 643 reg = TGARREG(dc, TGA_REG_SISR); 644 if (( reg & 0x00010001) != 0x00010001) { 645 /* Odd. We never set any of the other interrupt enables. */ 646 if ((reg & 0x1f) != 0) { 647 /* Clear the mysterious pending interrupts. */ 648 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 649 TGAREGWB(dc, TGA_REG_SISR, 1); 650 /* 651 * This was our interrupt, even if we're puzzled 652 * as to why we got it. Don't make the interrupt 653 * handler think it was a stray. 654 */ 655 return -1; 656 } else { 657 return 0; 658 } 659 } 660 /* if we have something to do, do it */ 661 if (dc->dc_ramdac_intr) { 662 dc->dc_ramdac_intr(dcrc); 663 dc->dc_ramdac_intr = NULL; 664 } 665 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 666 TGAREGWB(dc, TGA_REG_SISR, 1); 667 return 1; 668 } 669 670 static paddr_t 671 tga_mmap(void *v, void *vs, off_t offset, int prot) 672 { 673 struct tga_softc *sc = v; 674 675 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 676 return -1; 677 678 return bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 679 offset, prot, BUS_SPACE_MAP_LINEAR); 680 } 681 682 static int 683 tga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 684 int *curxp, int *curyp, long *attrp) 685 { 686 struct tga_softc *sc = v; 687 long defattr; 688 689 if (sc->nscreens > 0) 690 return ENOMEM; 691 692 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 693 *curxp = 0; 694 *curyp = 0; 695 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 696 0, 0, 0, &defattr); 697 *attrp = defattr; 698 sc->nscreens++; 699 return 0; 700 } 701 702 static void 703 tga_free_screen(void *v, void *cookie) 704 { 705 struct tga_softc *sc = v; 706 707 if (sc->sc_dc == &tga_console_dc) 708 panic("tga_free_screen: console"); 709 710 sc->nscreens--; 711 } 712 713 static int 714 tga_show_screen(void *v, void *cookie, int waitok, 715 void (*cb)(void *, int, int), void *cbarg) 716 { 717 718 return 0; 719 } 720 721 int 722 tga_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 723 pci_chipset_tag_t pc, int bus, int device, int function) 724 { 725 struct tga_devconfig *dcp = &tga_console_dc; 726 long defattr; 727 728 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 729 730 /* sanity checks */ 731 if (dcp->dc_vaddr == 0) 732 panic("tga_console(%d, %d): couldn't map memory space", 733 device, function); 734 if (dcp->dc_tgaconf == NULL) 735 panic("tga_console(%d, %d): unknown board configuration", 736 device, function); 737 738 /* 739 * Initialize the RAMDAC but DO NOT allocate any private storage. 740 * Initialization includes disabling cursor, setting a sane 741 * colormap, etc. It will be reinitialized in tgaattach(). 742 */ 743 if (dcp->dc_tga2) { 744 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 745 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 746 tga2_ramdac_rd); 747 else 748 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 749 tga2_ramdac_rd, tga_getdotclock(dcp)); 750 } else { 751 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 752 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 753 tga_ramdac_rd); 754 else { 755 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 756 tga_bt463_rd); 757 } 758 } 759 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 760 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 761 762 return 0; 763 } 764 765 /* 766 * Functions to blank and unblank the display. 767 */ 768 static void 769 tga_blank(struct tga_devconfig *dc) 770 { 771 772 if (!dc->dc_blanked) { 773 dc->dc_blanked = 1; 774 /* XXX */ 775 TGAWREG(dc, TGA_REG_VVVR, 776 TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 777 } 778 } 779 780 static void 781 tga_unblank(struct tga_devconfig *dc) 782 { 783 784 if (dc->dc_blanked) { 785 dc->dc_blanked = 0; 786 /* XXX */ 787 TGAWREG(dc, TGA_REG_VVVR, 788 TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 789 } 790 } 791 792 /* 793 * Functions to manipulate the built-in cursor handing hardware. 794 */ 795 int 796 tga_builtin_set_cursor(struct tga_devconfig *dc, 797 struct wsdisplay_cursor *cursorp) 798 { 799 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 800 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 801 uint8_t image[512]; 802 u_int count, v; 803 int error; 804 805 v = cursorp->which; 806 if (v & WSDISPLAY_CURSOR_DOCMAP) { 807 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 808 if (error) 809 return error; 810 } 811 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 812 if ((u_int)cursorp->size.x != 64 || 813 (u_int)cursorp->size.y > 64) 814 return EINVAL; 815 /* The cursor is 2 bits deep, and there is no mask */ 816 count = (cursorp->size.y * 64 * 2) / NBBY; 817 error = copyin(cursorp->image, image, count); 818 if (error) 819 return error; 820 } 821 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 822 return EINVAL; 823 824 /* parameters are OK; do it */ 825 if (v & WSDISPLAY_CURSOR_DOCUR) { 826 if (cursorp->enable) 827 /* XXX */ 828 TGAWREG(dc, TGA_REG_VVVR, 829 TGARREG(dc, TGA_REG_VVVR) | 0x04); 830 else 831 /* XXX */ 832 TGAWREG(dc, TGA_REG_VVVR, 833 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 834 } 835 if (v & WSDISPLAY_CURSOR_DOPOS) { 836 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 837 (cursorp->pos.x & 0xfff)); 838 } 839 if (v & WSDISPLAY_CURSOR_DOCMAP) { 840 dcrf->ramdac_set_curcmap(dcrc, cursorp); 841 } 842 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 843 count = ((64 * 2) / NBBY) * cursorp->size.y; 844 TGAWREG(dc, TGA_REG_CCBR, 845 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 846 (cursorp->size.y << 10)); 847 memcpy((void *)(dc->dc_vaddr + 848 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 849 image, count); 850 } 851 return 0; 852 } 853 854 int 855 tga_builtin_get_cursor(struct tga_devconfig *dc, 856 struct wsdisplay_cursor *cursorp) 857 { 858 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 859 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 860 int count, error; 861 862 cursorp->which = WSDISPLAY_CURSOR_DOALL & 863 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 864 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 865 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 866 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 867 cursorp->size.x = 64; 868 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 869 870 if (cursorp->image != NULL) { 871 count = (cursorp->size.y * 64 * 2) / NBBY; 872 error = copyout((char *)(dc->dc_vaddr + 873 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 874 cursorp->image, count); 875 if (error) 876 return error; 877 /* No mask */ 878 } 879 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 880 return error; 881 } 882 883 int 884 tga_builtin_set_curpos(struct tga_devconfig *dc, 885 struct wsdisplay_curpos *curposp) 886 { 887 888 TGAWREG(dc, TGA_REG_CXYR, 889 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 890 return 0; 891 } 892 893 int 894 tga_builtin_get_curpos(struct tga_devconfig *dc, 895 struct wsdisplay_curpos *curposp) 896 { 897 898 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 899 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 900 return 0; 901 } 902 903 int 904 tga_builtin_get_curmax(struct tga_devconfig *dc, 905 struct wsdisplay_curpos *curposp) 906 { 907 908 curposp->x = curposp->y = 64; 909 return 0; 910 } 911 912 /* 913 * Copy columns (characters) in a row (line). 914 */ 915 static void 916 tga_copycols(void *id, int row, int srccol, int dstcol, int ncols) 917 { 918 struct rasops_info *ri = id; 919 int y, srcx, dstx, nx; 920 921 y = ri->ri_font->fontheight * row; 922 srcx = ri->ri_font->fontwidth * srccol; 923 dstx = ri->ri_font->fontwidth * dstcol; 924 nx = ri->ri_font->fontwidth * ncols; 925 926 tga_rop(ri, dstx, y, 927 nx, ri->ri_font->fontheight, RAS_SRC, 928 ri, srcx, y); 929 } 930 931 /* 932 * Copy rows (lines). 933 */ 934 static void 935 tga_copyrows(void *id, int srcrow, int dstrow, int nrows) 936 { 937 struct rasops_info *ri = id; 938 int srcy, dsty, ny; 939 940 srcy = ri->ri_font->fontheight * srcrow; 941 dsty = ri->ri_font->fontheight * dstrow; 942 ny = ri->ri_font->fontheight * nrows; 943 944 tga_rop(ri, 0, dsty, 945 ri->ri_emuwidth, ny, RAS_SRC, 946 ri, 0, srcy); 947 } 948 949 /* Do we need the src? */ 950 static const int needsrc[16] = 951 { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 952 953 /* A mapping between our API and the TGA card */ 954 static const int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 955 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 956 }; 957 958 /* 959 * Generic TGA raster op. 960 * This covers all possible raster ops, and 961 * clips the sizes and all of that. 962 */ 963 static int 964 tga_rop(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 965 struct rasops_info *src, int sx, int sy) 966 { 967 968 if (dst == NULL) 969 return -1; 970 if (needsrc[RAS_GETOP(rop)]) { 971 if (src == NULL) 972 return -1; /* We want a src */ 973 /* Clip against src */ 974 if (sx < 0) { 975 w += sx; 976 sx = 0; 977 } 978 if (sy < 0) { 979 h += sy; 980 sy = 0; 981 } 982 if (sx + w > src->ri_emuwidth) 983 w = src->ri_emuwidth - sx; 984 if (sy + h > src->ri_emuheight) 985 h = src->ri_emuheight - sy; 986 } else { 987 if (src != NULL) 988 return -1; /* We need no src */ 989 } 990 /* Clip against dst. We modify src regardless of using it, 991 * since it really doesn't matter. 992 */ 993 if (dx < 0) { 994 w += dx; 995 sx -= dx; 996 dx = 0; 997 } 998 if (dy < 0) { 999 h += dy; 1000 sy -= dy; 1001 dy = 0; 1002 } 1003 if (dx + w > dst->ri_emuwidth) 1004 w = dst->ri_emuwidth - dx; 1005 if (dy + h > dst->ri_emuheight) 1006 h = dst->ri_emuheight - dy; 1007 if (w <= 0 || h <= 0) 1008 return 0; /* Vacuously true; */ 1009 if (src == NULL) { 1010 /* XXX Punt! */ 1011 return -1; 1012 } 1013 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1014 } 1015 1016 1017 1018 /* 1019 * Video to Video raster ops. 1020 * This function deals with all raster ops that have a src and dst 1021 * that are on the card. 1022 */ 1023 static int 1024 tga_rop_vtov(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 1025 struct rasops_info *src, int sx, int sy) 1026 { 1027 struct tga_devconfig *dc = dst->ri_hw; 1028 int srcb, dstb, tga_srcb, tga_dstb; 1029 int x, y, wb; 1030 int xstart, xdir; 1031 int ystart, yend, ydir, yinc; 1032 int xleft, lastx, lastleft; 1033 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1034 1035 /* 1036 * I don't yet want to deal with unaligned guys, really. And we don't 1037 * deal with copies from one card to another. 1038 */ 1039 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1040 /* XXX Punt! */ 1041 /* XXX should never happen, since it's only being used to 1042 * XXX copy 8-pixel-wide characters. 1043 */ 1044 return -1; 1045 } 1046 1047 srcb = sy * src->ri_stride + sx * (src->ri_depth / 8); 1048 dstb = dy * dst->ri_stride + dx * (dst->ri_depth / 8); 1049 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1050 (sx + src->ri_xorigin) * (src->ri_depth / 8); 1051 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1052 (dx + dst->ri_xorigin) * (dst->ri_depth / 8); 1053 1054 if (sy >= dy) { 1055 ystart = 0; 1056 yend = (h - 1) * dst->ri_stride; 1057 ydir = 1; 1058 } else { 1059 ystart = (h - 1) * dst->ri_stride; 1060 yend = 0; 1061 ydir = -1; 1062 } 1063 yinc = ydir * dst->ri_stride; 1064 1065 wb = w * (dst->ri_depth / 8); 1066 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1067 xstart = 0; 1068 xdir = 1; 1069 } else { /* copy backwards */ 1070 xstart = wb; 1071 xdir = -1; 1072 } 1073 1074 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1075 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1076 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1077 1078 /* 1079 * we have 3 sizes of pixels to move in X direction: 1080 * 4 * 64 (unrolled TGA ops) 1081 * 64 (single TGA op) 1082 * 4 (CPU, using long word) 1083 */ 1084 1085 if (xdir == 1) { /* move to the left */ 1086 1087 if (wb & ~63) 1088 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1089 /* 4 * 64 byte chunks */ 1090 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1091 x += 4 * 64, xleft -= 4 * 64) { 1092 1093 /* 1094 * XXX XXX Eight writes to different addresses 1095 * XXX XXX should fill up the write buffers on 1096 * XXX XXX 21064 and 21164 chips, but later 1097 * XXX XXX CPUs might have larger write buffers 1098 * XXX XXX which require further unrolling of 1099 * XXX XXX this loop, or the insertion of 1100 * XXX XXX memory barriers. 1101 */ 1102 TGAWALREG(dc, TGA_REG_GCSR, 0, 1103 tga_srcb + y + x + 0 * 64); 1104 TGAWALREG(dc, TGA_REG_GCDR, 0, 1105 tga_dstb + y + x + 0 * 64); 1106 TGAWALREG(dc, TGA_REG_GCSR, 1, 1107 tga_srcb + y + x + 1 * 64); 1108 TGAWALREG(dc, TGA_REG_GCDR, 1, 1109 tga_dstb + y + x + 1 * 64); 1110 TGAWALREG(dc, TGA_REG_GCSR, 2, 1111 tga_srcb + y + x + 2 * 64); 1112 TGAWALREG(dc, TGA_REG_GCDR, 2, 1113 tga_dstb + y + x + 2 * 64); 1114 TGAWALREG(dc, TGA_REG_GCSR, 3, 1115 tga_srcb + y + x + 3 * 64); 1116 TGAWALREG(dc, TGA_REG_GCDR, 3, 1117 tga_dstb + y + x + 3 * 64); 1118 } 1119 1120 /* 64 byte chunks */ 1121 for (; xleft >= 64; x += 64, xleft -= 64) { 1122 TGAWALREG(dc, TGA_REG_GCSR, 0, 1123 tga_srcb + y + x + 0 * 64); 1124 TGAWALREG(dc, TGA_REG_GCDR, 0, 1125 tga_dstb + y + x + 0 * 64); 1126 } 1127 } 1128 1129 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1130 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1131 1132 lastleft = wb & 63; 1133 if (lastleft) { 1134 lastx = xstart + (wb & ~63); 1135 for (y = ystart; (ydir * y) <= (ydir * yend); 1136 y += yinc) { 1137 /* 4 byte granularity */ 1138 for (x = lastx, xleft = lastleft; xleft >= 4; 1139 x += 4, xleft -= 4) { 1140 *(uint32_t *)(dst->ri_bits + dstb + 1141 y + x + 0 * 4) = 1142 *(uint32_t *)(dst->ri_bits + srcb + 1143 y + x + 0 * 4); 1144 } 1145 } 1146 } 1147 } else { /* above move to the left, below move to the right */ 1148 1149 if (wb & ~63) 1150 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1151 /* 4 * 64 byte chunks */ 1152 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1153 x -= 4 * 64, xleft -= 4 * 64) { 1154 1155 /* 1156 * XXX XXX Eight writes to different addresses 1157 * XXX XXX should fill up the write buffers on 1158 * XXX XXX 21064 and 21164 chips, but later 1159 * XXX XXX CPUs might have larger write buffers 1160 * XXX XXX which require further unrolling of 1161 * XXX XXX this loop, or the insertion of 1162 * XXX XXX memory barriers. 1163 */ 1164 TGAWALREG(dc, TGA_REG_GCSR, 0, 1165 tga_srcb + y + x - 1 * 64); 1166 TGAWALREG(dc, TGA_REG_GCDR, 0, 1167 tga_dstb + y + x - 1 * 64); 1168 TGAWALREG(dc, TGA_REG_GCSR, 1, 1169 tga_srcb + y + x - 2 * 64); 1170 TGAWALREG(dc, TGA_REG_GCDR, 1, 1171 tga_dstb + y + x - 2 * 64); 1172 TGAWALREG(dc, TGA_REG_GCSR, 2, 1173 tga_srcb + y + x - 3 * 64); 1174 TGAWALREG(dc, TGA_REG_GCDR, 2, 1175 tga_dstb + y + x - 3 * 64); 1176 TGAWALREG(dc, TGA_REG_GCSR, 3, 1177 tga_srcb + y + x - 4 * 64); 1178 TGAWALREG(dc, TGA_REG_GCDR, 3, 1179 tga_dstb + y + x - 4 * 64); 1180 } 1181 1182 /* 64 byte chunks */ 1183 for (; xleft >= 64; x -= 64, xleft -= 64) { 1184 TGAWALREG(dc, TGA_REG_GCSR, 0, 1185 tga_srcb + y + x - 1 * 64); 1186 TGAWALREG(dc, TGA_REG_GCDR, 0, 1187 tga_dstb + y + x - 1 * 64); 1188 } 1189 } 1190 1191 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1192 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1193 1194 lastleft = wb & 63; 1195 if (lastleft) { 1196 lastx = xstart - (wb & ~63); 1197 for (y = ystart; (ydir * y) <= (ydir * yend); 1198 y += yinc) { 1199 /* 4 byte granularity */ 1200 for (x = lastx, xleft = lastleft; xleft >= 4; 1201 x -= 4, xleft -= 4) { 1202 *(uint32_t *)(dst->ri_bits + dstb + 1203 y + x - 1 * 4) = 1204 *(uint32_t *)(dst->ri_bits + srcb + 1205 y + x - 1 * 4); 1206 } 1207 } 1208 } 1209 } 1210 return 0; 1211 } 1212 1213 1214 static void 1215 tga_putchar(void *c, int row, int col, u_int uc, long attr) 1216 { 1217 struct rasops_info *ri = c; 1218 struct tga_devconfig *dc = ri->ri_hw; 1219 int fs, height, width; 1220 uint8_t *fr; 1221 int32_t *rp; 1222 1223 rp = (int32_t *)(ri->ri_bits + 1224 row * ri->ri_yscale + col * ri->ri_xscale); 1225 1226 height = ri->ri_font->fontheight; 1227 width = ri->ri_font->fontwidth; 1228 1229 uc -= ri->ri_font->firstchar; 1230 fr = (uint8_t *)ri->ri_font->data + uc * ri->ri_fontscale; 1231 fs = ri->ri_font->stride; 1232 1233 /* Set foreground and background color. XXX memoize this somehow? 1234 * The rasops code has already expanded the color entry to 32 bits 1235 * for us, even for 8-bit displays, so we don't have to do anything. 1236 */ 1237 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1238 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1239 1240 /* Set raster operation to "copy"... */ 1241 if (ri->ri_depth == 8) 1242 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1243 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1244 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1245 1246 /* Set which pixels we're drawing (of a possible 32). */ 1247 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1248 1249 /* Set drawing mode to opaque stipple. */ 1250 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1251 1252 /* Insert write barrier before actually sending data */ 1253 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1254 TGAREGWB(dc, TGA_REG_GMOR, 1); 1255 1256 while (height--) { 1257 /* The actual stipple write */ 1258 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1259 1260 fr += fs; 1261 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1262 } 1263 1264 /* Do underline */ 1265 if ((attr & 1) != 0) { 1266 rp = (int32_t *)((uint8_t *)rp - (ri->ri_stride << 1)); 1267 *rp = 0xffffffff; 1268 } 1269 1270 /* Set graphics mode back to normal. */ 1271 TGAWREG(dc, TGA_REG_GMOR, 0); 1272 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1273 } 1274 1275 static void 1276 tga_eraserows(void *c, int row, int num, long attr) 1277 { 1278 struct rasops_info *ri = c; 1279 struct tga_devconfig *dc = ri->ri_hw; 1280 int32_t color, lines, pixels; 1281 int32_t *rp; 1282 1283 color = ri->ri_devcmap[(attr >> 16) & 15]; 1284 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1285 lines = num * ri->ri_font->fontheight; 1286 pixels = ri->ri_emuwidth - 1; 1287 1288 /* Set fill color in block-color registers */ 1289 TGAWREG(dc, TGA_REG_GBCR0, color); 1290 TGAWREG(dc, TGA_REG_GBCR1, color); 1291 if (ri->ri_depth != 8) { 1292 TGAWREG(dc, TGA_REG_GBCR2, color); 1293 TGAWREG(dc, TGA_REG_GBCR3, color); 1294 TGAWREG(dc, TGA_REG_GBCR4, color); 1295 TGAWREG(dc, TGA_REG_GBCR5, color); 1296 TGAWREG(dc, TGA_REG_GBCR6, color); 1297 TGAWREG(dc, TGA_REG_GBCR7, color); 1298 } 1299 1300 /* Set raster operation to "copy"... */ 1301 if (ri->ri_depth == 8) 1302 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1303 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1304 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1305 1306 /* Set which pixels we're drawing (of a possible 32). */ 1307 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1308 1309 /* Set drawing mode to block fill. */ 1310 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1311 1312 /* Insert write barrier before actually sending data */ 1313 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1314 TGAREGWB(dc, TGA_REG_GMOR, 1); 1315 1316 while (lines--) { 1317 *rp = pixels; 1318 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1319 } 1320 1321 /* Set graphics mode back to normal. */ 1322 TGAWREG(dc, TGA_REG_GMOR, 0); 1323 } 1324 1325 static void 1326 tga_erasecols (void *c, int row, int col, int num, long attr) 1327 { 1328 struct rasops_info *ri = c; 1329 struct tga_devconfig *dc = ri->ri_hw; 1330 int32_t color, lines, pixels; 1331 int32_t *rp; 1332 1333 color = ri->ri_devcmap[(attr >> 16) & 15]; 1334 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1335 lines = ri->ri_font->fontheight; 1336 pixels = (num * ri->ri_font->fontwidth) - 1; 1337 1338 /* Set fill color in block-color registers */ 1339 TGAWREG(dc, TGA_REG_GBCR0, color); 1340 TGAWREG(dc, TGA_REG_GBCR1, color); 1341 if (ri->ri_depth != 8) { 1342 TGAWREG(dc, TGA_REG_GBCR2, color); 1343 TGAWREG(dc, TGA_REG_GBCR3, color); 1344 TGAWREG(dc, TGA_REG_GBCR4, color); 1345 TGAWREG(dc, TGA_REG_GBCR5, color); 1346 TGAWREG(dc, TGA_REG_GBCR6, color); 1347 TGAWREG(dc, TGA_REG_GBCR7, color); 1348 } 1349 1350 /* Set raster operation to "copy"... */ 1351 if (ri->ri_depth == 8) 1352 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1353 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1354 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1355 1356 /* Set which pixels we're drawing (of a possible 32). */ 1357 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1358 1359 /* Set drawing mode to block fill. */ 1360 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1361 1362 /* Insert write barrier before actually sending data */ 1363 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1364 TGAREGWB(dc, TGA_REG_GMOR, 1); 1365 1366 while (lines--) { 1367 *rp = pixels; 1368 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1369 } 1370 1371 /* Set graphics mode back to normal. */ 1372 TGAWREG(dc, TGA_REG_GMOR, 0); 1373 } 1374 1375 1376 static void 1377 tga_ramdac_wr(void *v, u_int btreg, uint8_t val) 1378 { 1379 struct tga_devconfig *dc = v; 1380 1381 if (btreg > BT485_REG_MAX) 1382 panic("tga_ramdac_wr: reg %d out of range", btreg); 1383 1384 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1385 TGAREGWB(dc, TGA_REG_EPDR, 1); 1386 } 1387 1388 static void 1389 tga2_ramdac_wr(void *v, u_int btreg, uint8_t val) 1390 { 1391 struct tga_devconfig *dc = v; 1392 bus_space_handle_t ramdac; 1393 1394 if (btreg > BT485_REG_MAX) 1395 panic("tga_ramdac_wr: reg %d out of range", btreg); 1396 1397 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1398 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1399 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1400 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1401 } 1402 1403 static uint8_t 1404 tga_bt463_rd(void *v, u_int btreg) 1405 { 1406 struct tga_devconfig *dc = v; 1407 tga_reg_t rdval; 1408 1409 /* 1410 * Strobe CE# (high->low->high) since status and data are latched on 1411 * the falling and rising edges (respectively) of this active-low 1412 * signal. 1413 */ 1414 1415 TGAREGWB(dc, TGA_REG_EPSR, 1); 1416 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1417 TGAREGWB(dc, TGA_REG_EPSR, 1); 1418 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1419 1420 TGAREGRB(dc, TGA_REG_EPSR, 1); 1421 1422 rdval = TGARREG(dc, TGA_REG_EPDR); 1423 TGAREGWB(dc, TGA_REG_EPSR, 1); 1424 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1425 1426 return (rdval >> 16) & 0xff; 1427 } 1428 1429 static void 1430 tga_bt463_wr(void *v, u_int btreg, uint8_t val) 1431 { 1432 struct tga_devconfig *dc = v; 1433 1434 /* 1435 * In spite of the 21030 documentation, to set the MPU bus bits for 1436 * a write, you set them in the upper bits of EPDR, not EPSR. 1437 */ 1438 1439 /* 1440 * Strobe CE# (high->low->high) since status and data are latched on 1441 * the falling and rising edges of this active-low signal. 1442 */ 1443 1444 TGAREGWB(dc, TGA_REG_EPDR, 1); 1445 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1446 TGAREGWB(dc, TGA_REG_EPDR, 1); 1447 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1448 TGAREGWB(dc, TGA_REG_EPDR, 1); 1449 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1450 } 1451 1452 static uint8_t 1453 tga_ramdac_rd(void *v, u_int btreg) 1454 { 1455 struct tga_devconfig *dc = v; 1456 tga_reg_t rdval; 1457 1458 if (btreg > BT485_REG_MAX) 1459 panic("tga_ramdac_rd: reg %d out of range", btreg); 1460 1461 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1462 TGAREGWB(dc, TGA_REG_EPSR, 1); 1463 1464 rdval = TGARREG(dc, TGA_REG_EPDR); 1465 return (rdval >> 16) & 0xff; /* XXX */ 1466 } 1467 1468 static uint8_t 1469 tga2_ramdac_rd(void *v, u_int btreg) 1470 { 1471 struct tga_devconfig *dc = v; 1472 bus_space_handle_t ramdac; 1473 uint8_t retval; 1474 1475 if (btreg > BT485_REG_MAX) 1476 panic("tga_ramdac_rd: reg %d out of range", btreg); 1477 1478 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1479 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1480 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1481 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1482 return retval; 1483 } 1484 1485 #include <dev/ic/decmonitors.c> 1486 static void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1487 1488 static struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1489 1490 static void 1491 tga2_init(struct tga_devconfig *dc) 1492 { 1493 struct monitor *m = tga_getmonitor(dc); 1494 1495 /* Deal with the dot clocks. 1496 */ 1497 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1498 /* 1499 * Set this up as a reference clock for the 1500 * ibm561's PLL. 1501 */ 1502 tga2_ics9110_wr(dc, 14300000); 1503 /* 1504 * XXX Can't set up the dotclock properly, until such time 1505 * as the RAMDAC is configured. 1506 */ 1507 } else { 1508 /* otherwise the ics9110 is our clock. */ 1509 tga2_ics9110_wr(dc, m->dotclock); 1510 } 1511 #if 0 1512 TGAWREG(dc, TGA_REG_VHCR, 1513 ((m->hbp / 4) << 21) | 1514 ((m->hsync / 4) << 14) | 1515 (((m->hfp - 4) / 4) << 9) | 1516 ((m->cols + 4) / 4)); 1517 #else 1518 TGAWREG(dc, TGA_REG_VHCR, 1519 ((m->hbp / 4) << 21) | 1520 ((m->hsync / 4) << 14) | 1521 (((m->hfp) / 4) << 9) | 1522 ((m->cols) / 4)); 1523 #endif 1524 TGAWREG(dc, TGA_REG_VVCR, 1525 (m->vbp << 22) | 1526 (m->vsync << 16) | 1527 (m->vfp << 11) | 1528 (m->rows)); 1529 TGAWREG(dc, TGA_REG_VVBR, 1); 1530 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1531 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1532 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1533 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1534 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1535 } 1536 1537 void 1538 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock) 1539 { 1540 bus_space_handle_t clock; 1541 uint32_t valU; 1542 int N, M, R, V, X; 1543 int i; 1544 1545 switch (dotclock) { 1546 case 130808000: 1547 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1548 case 119840000: 1549 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1550 case 108180000: 1551 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1552 case 103994000: 1553 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1554 case 175000000: 1555 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1556 case 75000000: 1557 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1558 case 74000000: 1559 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1560 case 69000000: 1561 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1562 case 65000000: 1563 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1564 case 50000000: 1565 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1566 case 40000000: 1567 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1568 case 31500000: 1569 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1570 case 25175000: 1571 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1572 case 135000000: 1573 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1574 case 110000000: 1575 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1576 case 202500000: 1577 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1578 case 14300000: /* this one is just a ref clock */ 1579 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1580 default: 1581 panic("unrecognized clock rate %d", dotclock); 1582 } 1583 1584 /* XXX -- hard coded, bad */ 1585 valU = N | ( M << 7 ) | (V << 14); 1586 valU |= (X << 15) | (R << 17); 1587 valU |= 0x17 << 19; 1588 1589 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1590 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1591 1592 for (i = 24; i > 0; i--) { 1593 uint32_t writeval; 1594 1595 writeval = valU & 0x1; 1596 if (i == 1) 1597 writeval |= 0x2; 1598 valU >>= 1; 1599 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1600 bus_space_barrier(dc->dc_memt, clock, 0, 4, 1601 BUS_SPACE_BARRIER_WRITE); 1602 } 1603 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1604 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1605 &clock); /* XXX */ 1606 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1607 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1608 } 1609 1610 static struct monitor * 1611 tga_getmonitor(struct tga_devconfig *dc) 1612 { 1613 1614 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1615 } 1616 1617 static unsigned int 1618 tga_getdotclock(struct tga_devconfig *dc) 1619 { 1620 1621 return tga_getmonitor(dc)->dotclock; 1622 } 1623
Indexes created Sat Sep 20 22:09:52 GMT 2025