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  /xsrc/external/mit/MesaLib/dist/src/compiler/nir/tests/
builder_tests.cpp 102 nir_ssa_def *srcs[] = { local
107 store_test_val(nir_extract_bits(b, srcs, 2, 24, 1, 64));
118 nir_ssa_def *srcs[] = { local
123 store_test_val(nir_extract_bits(b, srcs, 2, 16, 1, 64));
134 nir_ssa_def *srcs[] = { local
142 store_test_val(nir_extract_bits(b, srcs, 4, 24, 2, 32));
  /xsrc/external/mit/MesaLib/dist/src/compiler/nir/
nir_opt_constant_folding.c 94 nir_const_value *srcs[NIR_MAX_VEC_COMPONENTS]; local
97 srcs[i] = src[i];
99 bit_size, srcs,
nir_opt_shrink_vectors.c 114 nir_ssa_def *srcs[NIR_MAX_VEC_COMPONENTS] = { 0 }; local
118 srcs[index++] = nir_ssa_for_alu_src(b, instr, i);
121 nir_ssa_def *new_vec = nir_vec(b, srcs, num_components);
nir_lower_bit_size.c 57 nir_ssa_def *srcs[NIR_MAX_VEC_COMPONENTS] = { NULL }; local
70 srcs[i] = src;
77 lowered_dst = nir_imul(bld, srcs[0], srcs[1]);
83 lowered_dst = nir_build_alu_src_arr(bld, op, srcs);
nir_search.h 160 const nir_search_value *srcs[4]; member in struct:__anon809
nir_lower_vars_to_ssa.c 656 nir_ssa_def *srcs[NIR_MAX_VEC_COMPONENTS]; local
659 srcs[i] = nir_channel(&b, value, i);
661 srcs[i] = nir_channel(&b, old_def, i);
664 new_def = nir_vec(&b, srcs, intrin->num_components);
  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_vec4_surface_builder.cpp 193 const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD); local
196 bld.MOV(writemask(srcs, WRITEMASK_X),
201 bld.MOV(writemask(srcs, WRITEMASK_Y),
208 emit_insert(bld, src_reg(srcs), size, has_simd4x2),
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
nir_lower_bit_size.c 55 nir_ssa_def *srcs[4] = { NULL, NULL, NULL, NULL }; local
61 srcs[i] = convert_to_bit_size(bld, src, type, bit_size);
63 srcs[i] = src;
68 nir_build_alu(bld, op, srcs[0], srcs[1], srcs[2], srcs[3]);
nir_opt_constant_folding.c 92 nir_const_value *srcs[NIR_MAX_VEC_COMPONENTS]; local
95 srcs[i] = src[i];
97 bit_size, srcs);
nir_search.h 152 const nir_search_value *srcs[4]; member in struct:__anon3419
nir_lower_vars_to_ssa.c 600 nir_ssa_def *srcs[NIR_MAX_VEC_COMPONENTS]; local
603 srcs[i] = nir_channel(&b, value, i);
605 srcs[i] = nir_channel(&b, old_def, i);
608 new_def = nir_vec(&b, srcs, intrin->num_components);
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/spirv/
vtn_opencl.c 35 unsigned num_srcs, nir_ssa_def **srcs,
46 nir_ssa_def *srcs[3] = { NULL }; local
47 vtn_assert(num_srcs <= ARRAY_SIZE(srcs));
49 srcs[i] = vtn_ssa_value(b, w[i + 5])->def;
52 nir_ssa_def *result = handler(b, opcode, num_srcs, srcs, dest_type);
109 nir_ssa_def **srcs, const struct glsl_type *dest_type)
112 srcs[0], srcs[1], srcs[2], NULL);
117 nir_ssa_def **srcs, const struct glsl_type *dest_type
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/gp/
disasm.c 360 unsigned srcs; member in struct:__anon3720
366 .srcs = _srcs \
394 acc0_op.srcs = 1;
408 if (acc0_op.srcs > 1) {
426 acc1_op.srcs = 1;
440 if (acc1_op.srcs > 1) {
  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_vec4_surface_builder.cpp 195 const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD); local
198 bld.MOV(writemask(srcs, WRITEMASK_X),
203 bld.MOV(writemask(srcs, WRITEMASK_Y),
210 emit_insert(bld, src_reg(srcs), size, has_simd4x2),
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/gp/
disasm.c 373 unsigned srcs; member in struct:__anon1254
379 .srcs = _srcs \
409 acc0_op.srcs = 1;
423 if (acc0_op.srcs > 1) {
442 acc1_op.srcs = 1;
456 if (acc1_op.srcs > 1) {
  /xsrc/external/mit/MesaLib/dist/src/asahi/compiler/
agx_opcodes.py 29 def __init__(self, name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32):
32 self.srcs = srcs
60 def op(name, encoding_32, dests = 1, srcs = 0, imms = [], is_float = False, can_eliminate = True, encoding_16 = None):
64 opcodes[name] = Opcode(name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32)
129 srcs = 1, is_float = True)
149 srcs = 2, is_float = True)
154 srcs = 3, is_float = True)
159 srcs = 2, is_float = True)
168 srcs = 2, imms = [SHIFT]
184 srcs = 2) variable
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/pp/
disasm.c 34 unsigned srcs; member in struct:__anon1307
356 .srcs = _srcs \
362 .srcs = 2
411 if (op.srcs > 1) {
422 .srcs = _srcs \
472 if (op.srcs > 1) {
484 .srcs = _srcs \
490 .srcs = 2
533 if (op.srcs > 1) {
545 .srcs = _srcs
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/
sfn_nir_lower_fs_out_to_vector.cpp 91 nir_ssa_def **srcs, unsigned first_comp, unsigned num_comps) = 0;
104 nir_ssa_def **srcs, unsigned first_comp, unsigned num_comps) override;
107 nir_ssa_def *create_combined_vector(nir_builder *b, nir_ssa_def **srcs,
359 nir_ssa_def *srcs[4]; local
361 srcs[i] = &instr_undef->def;
363 srcs[var->data.location_frac] = intr->src[1].ssa;
378 if (srcs[var2->data.location_frac] == &instr_undef->def) {
381 srcs[var2->data.location_frac] = intr2->src[1].ssa;
386 create_new_io(b, intr, new_var, srcs, new_var->data.location_frac,
398 nir_ssa_def **srcs, unsigned first_comp, unsigned num_comps
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
si_shaderlib_tgsi.c 184 struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)}; local
185 ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2, load_qualifier,
196 struct ureg_src srcs[] = {ureg_src(store_addr), is_copy ? values[d] : value}; local
197 ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2, store_qualifier,
732 struct ureg_src srcs[] = {image, ureg_src(coord)}; local
733 ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &sample[i], 1, srcs, 2, TGSI_MEMORY_RESTRICT, target,
742 struct ureg_src srcs[] = {ureg_src(coord), ureg_src(sample[i])}; local
743 ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst_image, 1, srcs, 2, TGSI_MEMORY_RESTRICT,
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/pp/
disasm.c 34 unsigned srcs; member in struct:__anon3773
321 .srcs = _srcs \
327 .srcs = 2
376 if (op.srcs > 1) {
387 .srcs = _srcs \
437 if (op.srcs > 1) {
449 .srcs = _srcs \
455 .srcs = 2
498 if (op.srcs > 1) {
510 .srcs = _srcs
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
si_shaderlib_tgsi.c 196 struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)}; local
197 ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2,
209 struct ureg_src srcs[] = local
211 ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2,
  /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
ir3.c 265 unsigned components = instr->srcs[2]->uim_val;
436 (nsrc * sizeof(instr->srcs[0]));
442 instr->srcs = instr->dsts + ndst;
467 struct ir3_register **dsts, **srcs; local
470 srcs = new_instr->srcs;
473 new_instr->srcs = srcs;
495 new_instr->address = new_instr->srcs[instr->srcs_count - 1];
521 instr->srcs[instr->srcs_count++] = reg
    [all...]
ir3_ra_validate.c 237 struct ir3_register *src = split->srcs[0];
256 struct reg_state srcs[size]; local
259 struct ir3_register *src = collect->srcs[i];
263 srcs[dst_offset + j] = (struct reg_state){
269 srcs[dst_offset + j] = file->regs[src_physreg + j];
275 file->regs[dst_physreg + i] = srcs[i];
283 size += reg_size(pcopy->srcs[i]);
286 struct reg_state srcs[size]; local
291 struct ir3_register *src = pcopy->srcs[i];
296 srcs[offset + j] = (struct reg_state)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/microsoft/clc/
clc_compiler_test.cpp 1422 std::vector<const char *> srcs = { foo_src, kernel_source }; local
1427 run_shader(srcs, inout.size(), 1, 1, inout);
  /xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
ir3_sched.c 191 deepest(struct ir3_instruction **srcs, unsigned nsrcs)
196 while ((i < nsrcs) && !(d = srcs[id = i]))
203 if (srcs[i] && (srcs[i]->sun > d->sun))
204 d = srcs[id = i];
206 srcs[id] = NULL;
304 /* calculate delay for instruction (maximum of delay for all srcs): */
435 struct ir3_instruction *srcs[__ssa_src_cnt(instr)]; local
453 /* find unscheduled srcs: */
456 debug_assert(nsrcs < ARRAY_SIZE(srcs));
    [all...]

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