amdgpu_dcn10_hw_sequencer.c | 3138 uint32_t *start_line, 3155 *start_line = start_position; 3157 *start_line = dc_crtc_timing->v_total + start_position - 1; 3159 *end_line = *start_line + 2; 3169 uint32_t *start_line, 3184 start_line, 3204 uint32_t start_line = 0; local in function:dcn10_setup_periodic_interrupt 3207 dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line); 3209 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line); 3221 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx) local in function:dcn10_setup_vupdate_interrupt [all...] |