1 /* $NetBSD: cycv_platform.c,v 1.20 2025/09/06 21:02:39 thorpej Exp $ */ 2 3 /* This file is in the public domain. */ 4 5 #include "arml2cc.h" 6 #include "opt_console.h" 7 #include "opt_multiprocessor.h" 8 9 #include <sys/cdefs.h> 10 __KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.20 2025/09/06 21:02:39 thorpej Exp $"); 11 12 #define _ARM32_BUS_DMA_PRIVATE 13 #include <sys/param.h> 14 #include <sys/bus.h> 15 #include <sys/cpu.h> 16 #include <sys/device.h> 17 18 #include <uvm/uvm_extern.h> 19 20 #include <arm/arm32/machdep.h> 21 22 #include <arm/altera/cycv_reg.h> 23 #include <arm/altera/cycv_var.h> 24 #include <arm/cortex/a9tmr_var.h> 25 #include <arm/cortex/pl310_var.h> 26 #include <arm/cortex/scu_reg.h> 27 28 #include <arm/bootconfig.h> 29 #include <arm/cpufunc.h> 30 31 #include <dev/fdt/fdtvar.h> 32 #include <dev/fdt/fdt_platform.h> 33 34 #include <arm/fdt/arm_fdtvar.h> 35 #include <dev/ic/comreg.h> 36 37 void cycv_platform_early_putchar(char); 38 39 void __noasan 40 cycv_platform_early_putchar(char c) { 41 #ifdef CONSADDR 42 #define CONSADDR_VA (CONSADDR - CYCV_PERIPHERAL_BASE + CYCV_PERIPHERAL_VBASE) 43 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 44 (volatile uint32_t *) CONSADDR_VA : 45 (volatile uint32_t *) CONSADDR; 46 47 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 48 ; 49 50 uartaddr[com_data] = htole32(c); 51 #endif 52 } 53 54 static const struct pmap_devmap * 55 cycv_platform_devmap(void) { 56 static const struct pmap_devmap devmap[] = { 57 DEVMAP_ENTRY(CYCV_PERIPHERAL_VBASE, 58 CYCV_PERIPHERAL_BASE, 59 CYCV_PERIPHERAL_SIZE), 60 DEVMAP_ENTRY_END 61 }; 62 63 return devmap; 64 } 65 66 static void 67 cycv_platform_bootstrap(void) 68 { 69 bus_space_tag_t bst = &armv7_generic_bs_tag; 70 bus_space_handle_t bsh_l2c; 71 72 bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c); 73 74 #if NARML2CC > 0 75 arml2cc_init(bst, bsh_l2c, 0); 76 #endif 77 78 arm_fdt_cpu_bootstrap(); 79 } 80 81 static int 82 cycv_mpstart(void) 83 { 84 int ret = 0; 85 86 #ifdef MULTIPROCESSOR 87 bus_space_tag_t bst = &armv7_generic_bs_tag; 88 bus_space_handle_t bsh_rst; 89 bus_space_handle_t bsh_scu; 90 91 bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst); 92 bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu); 93 94 /* Enable Snoop Control Unit */ 95 bus_space_write_4(bst, bsh_scu, SCU_INV_ALL_REG, 0xff); 96 bus_space_write_4(bst, bsh_scu, SCU_CTL, 97 bus_space_read_4(bst, bsh_scu, SCU_CTL) | SCU_CTL_SCU_ENA); 98 99 const uint32_t startfunc = 100 (uint32_t) KERN_VTOPHYS((vaddr_t) cpu_mpstart); 101 102 /* 103 * We place a "LDR PC, =cpu_mpstart" at address 0 in order to bootstrap 104 * CPU 1. We can't use the similar feature of the Boot ROM because 105 * it was unmapped by u-boot in favor of the SDRAM. 106 */ 107 pmap_map_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, CYCV_SDRAM_BASE, 108 L1_S_SIZE, VM_PROT_READ|VM_PROT_WRITE, PMAP_NOCACHE); 109 110 /* 0: LDR PC, [PC, #0x18] -> loads address at 0x20 into PC */ 111 *(volatile uint32_t *) CYCV_SDRAM_VBASE = htole32(0xe59ff018); 112 *(volatile uint32_t *) (CYCV_SDRAM_VBASE + 0x20) = startfunc; 113 114 pmap_unmap_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, L1_S_SIZE); 115 116 bus_space_write_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST, 117 bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) & 118 ~CYCV_RSTMGR_MPUMODRST_CPU1); 119 120 /* Wait for secondary processor to start */ 121 int i; 122 for (i = 0x10000000; i > 0; i--) { 123 if (cpu_hatched_p(1)) 124 break; 125 } 126 if (i == 0) { 127 aprint_error("cpu%d: WARNING: AP failed to start\n", 1); 128 ret++; 129 } 130 #endif 131 132 return ret; 133 } 134 135 static void 136 cycv_platform_init_attach_args(struct fdt_attach_args *faa) { 137 faa->faa_bst = &armv7_generic_bs_tag; 138 faa->faa_dmat = &arm_generic_dma_tag; 139 } 140 141 static void 142 cycv_platform_device_register(device_t dev, void *aux) 143 { 144 prop_dictionary_t dict = device_properties(dev); 145 146 if (device_is_a(dev, "arma9tmr")) { 147 prop_dictionary_set_uint32(dict, "frequency", 148 cycv_clkmgr_early_get_mpu_clk() / 4); 149 } 150 } 151 152 static void 153 cycv_platform_reset(void) { 154 bus_space_tag_t bst = &armv7_generic_bs_tag; 155 bus_space_handle_t bsh; 156 uint32_t val; 157 158 bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh); 159 val = bus_space_read_4(bst, bsh, CYCV_RSTMGR_CTRL); 160 bus_space_write_4(bst, bsh, CYCV_RSTMGR_CTRL, 161 val | CYCV_RSTMGR_CTRL_SWCOLDRSTREQ); 162 } 163 164 static u_int 165 cycv_platform_uart_freq(void) { 166 return cycv_clkmgr_early_get_l4_sp_clk(); 167 } 168 169 static const struct fdt_platform cycv_platform = { 170 .fp_devmap = cycv_platform_devmap, 171 .fp_bootstrap = cycv_platform_bootstrap, 172 .fp_init_attach_args = cycv_platform_init_attach_args, 173 .fp_device_register = cycv_platform_device_register, 174 .fp_reset = cycv_platform_reset, 175 .fp_delay = a9tmr_delay, 176 .fp_uart_freq = cycv_platform_uart_freq, 177 .fp_mpstart = cycv_mpstart, 178 }; 179 180 FDT_PLATFORM(cycv, "altr,socfpga-cyclone5", &cycv_platform); 181
Indexes created Sat Sep 20 22:09:52 GMT 2025