| /src/sys/dev/ic/ |
| rtl8169.c | 1543 const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ? local in function:re_intr
1558 if ((status & status_mask) == 0)
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_lcdc.c | 453 const uint32_t status_mask = crtc_index == 0 ? local in function:sunxi_lcdc_intr
457 if ((val & status_mask) != 0) {
458 TCON_WRITE(sc, TCON_GINT0_REG, val & ~status_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vi.c | 868 u32 status_mask; local in function:vi_set_vce_clocks
874 status_mask = 0x00010000;
879 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
890 if (RREG32_SMC(reg_status) & status_mask)
904 if (RREG32_SMC(reg_status) & status_mask)
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_irq.c | 421 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; local in function:i915_pipestat_enable_mask
422 u32 enable_mask = status_mask << 16;
433 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
439 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
445 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
447 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
452 status_mask & ~PIPESTAT_INT_STATUS_MASK,
453 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
454 pipe_name(pipe), enable_mask, status_mask);
460 enum pipe pipe, u32 status_mask)
1314 u32 status_mask, enable_mask, iir_bit = 0; local in function:i9xx_pipestat_irq_ack
[all...] |
