1 /* $NetBSD: stg.c,v 1.6 2011/10/30 21:08:33 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 Frank Wille. 5 * All rights reserved. 6 * 7 * Written by Frank Wille for The NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 33 #include <netinet/in.h> 34 #include <netinet/in_systm.h> 35 36 #include <lib/libsa/stand.h> 37 #include <lib/libsa/net.h> 38 39 #include "globals.h" 40 41 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) 42 #define CSR_READ_1(l, r) in8((l)->csr+(r)) 43 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 44 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 46 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 47 #define VTOPHYS(va) (uint32_t)(va) 48 #define DEVTOV(pa) (uint32_t)(pa) 49 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 50 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 51 #define DELAY(n) delay(n) 52 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 53 54 struct desc { 55 uint64_t xd0, xd1, xd2, dummy; 56 }; 57 #define T1_EMPTY (1U << 31) /* no Tx frame available */ 58 #define T1_NOALIGN (3U << 16) /* allow any Tx alignment */ 59 #define T1_CNTSHIFT 24 /* Tx fragment count */ 60 #define T2_LENSHIFT 48 /* Tx fragment length */ 61 #define R1_DONE (1U << 31) /* desc has a Rx frame */ 62 #define R1_FL_MASK 0xffff /* Rx frame length */ 63 #define R1_ER_MASK 0x3f0000 /* Rx error indication */ 64 #define R2_LENSHIFT 48 /* Rx fragment length */ 65 66 #define STGE_DMACtrl 0x00 67 #define DMAC_RxDMAPollNow (1U << 4) 68 #define DMAC_TxDMAPollNow (1U << 12) 69 #define STGE_TFDListPtrLo 0x10 70 #define STGE_TFDListPtrHi 0x14 71 #define STGE_RFDListPtrLo 0x1c 72 #define STGE_RFDListPtrHi 0x20 73 #define STGE_DebugCtrl 0x2c 74 #define STGE_AsicCtrl 0x30 75 #define AC_PhyMedia (1U << 7) 76 #define AC_GlobalReset (1U << 16) 77 #define AC_RxReset (1U << 17) 78 #define AC_TxReset (1U << 18) 79 #define AC_DMA (1U << 19) 80 #define AC_FIFO (1U << 20) 81 #define AC_Network (1U << 21) 82 #define AC_Host (1U << 22) 83 #define AC_AutoInit (1U << 23) 84 #define AC_RstOut (1U << 24) 85 #define AC_ResetBusy (1U << 26) 86 #define STGE_EepromData 0x48 87 #define STGE_EepromCtrl 0x4a 88 #define EC_EepromAddress(x) ((x) & 0xff) 89 #define EC_EepromOpcode(x) ((x) << 8) 90 #define EC_OP_RR 2 91 #define EC_EepromBusy (1U << 15) 92 #define STGE_IntEnable 0x5c 93 #define STGE_MACCtrl 0x6c 94 #define MC_DuplexSelect (1U << 5) 95 #define MC_StatisticsDisable (1U << 22) 96 #define MC_TxEnable (1U << 24) 97 #define MC_RxEnable (1U << 27) 98 #define STGE_PhyCtrl 0x76 99 #define PC_MgmtClk (1U << 0) 100 #define PC_MgmtData (1U << 1) 101 #define PC_MgmtDir (1U << 2) 102 #define PC_PhyDuplexPolarity (1U << 3) 103 #define PC_PhyDuplexStatus (1U << 4) 104 #define PC_PhyLnkPolarity (1U << 5) 105 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 106 #define PC_LinkSpeed_Down 0 107 #define PC_LinkSpeed_10 1 108 #define PC_LinkSpeed_100 2 109 #define PC_LinkSpeed_1000 3 110 #define STGE_StationAddress0 0x78 111 #define STGE_StationAddress1 0x7a 112 #define STGE_StationAddress2 0x7c 113 #define STGE_MaxFrameSize 0x84 114 #define STGE_ReceiveMode 0x88 115 #define RM_ReceiveUnicast (1U << 0) 116 #define RM_ReceiveMulticast (1U << 1) 117 #define RM_ReceiveBroadcast (1U << 2) 118 #define RM_ReceiveAllFrames (1U << 3) 119 #define RM_ReceiveMulticastHash (1U << 4) 120 #define RM_ReceiveIPMulticast (1U << 5) 121 122 #define STGE_EEPROM_SA0 0x10 123 124 #define FRAMESIZE 1536 125 126 struct local { 127 struct desc txd[2]; 128 struct desc rxd[2]; 129 uint8_t rxstore[2][FRAMESIZE]; 130 unsigned csr, rx, tx, phy; 131 uint16_t bmsr, anlpar; 132 uint8_t phyctrl_saved; 133 }; 134 135 static void stg_reset(struct local *); 136 static int mii_read(struct local *, int, int); 137 static void mii_write(struct local *, int, int, int); 138 static void mii_initphy(struct local *); 139 static void mii_dealan(struct local *, unsigned); 140 static void mii_bitbang_sync(struct local *); 141 static void mii_bitbang_send(struct local *, uint32_t, int); 142 static void mii_bitbang_clk(struct local *, uint8_t); 143 static int eeprom_wait(struct local *); 144 145 int 146 stg_match(unsigned tag, void *data) 147 { 148 unsigned v; 149 150 v = pcicfgread(tag, PCI_ID_REG); 151 switch (v) { 152 case PCI_DEVICE(0x13f0, 0x1023): /* ST1023, IP1000A */ 153 return 1; 154 } 155 return 0; 156 } 157 158 void * 159 stg_init(unsigned tag, void *data) 160 { 161 struct local *l; 162 struct desc *txd, *rxd; 163 uint8_t *en; 164 unsigned i; 165 uint32_t macctl, reg; 166 static uint8_t bad[2][6] = { 167 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 168 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } 169 }; 170 171 l = ALLOC(struct local, 32); /* desc alignment */ 172 memset(l, 0, sizeof(struct local)); 173 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* first try mem space */ 174 if (l->csr == 0) 175 l->csr = DEVTOV(PCI_XIOBASE + (pcicfgread(tag, 0x10) & ~01)); 176 177 stg_reset(l); 178 179 mii_initphy(l); 180 181 /* read ethernet address */ 182 en = data; 183 for (i = 0; i < 6; i++) 184 en[i] = CSR_READ_1(l, STGE_StationAddress0 + i); 185 186 if (memcmp(en, bad[0], 6) == 0 || memcmp(en, bad[1], 6) == 0) { 187 uint16_t addr[3]; 188 189 for (i = 0; i < 3; i++) { 190 if (eeprom_wait(l) != 0) 191 printf("NIC: serial EEPROM is not ready!\n"); 192 CSR_WRITE_2(l, STGE_EepromCtrl, 193 EC_EepromAddress(STGE_EEPROM_SA0 + i) | 194 EC_EepromOpcode(EC_OP_RR)); 195 if (eeprom_wait(l) != 0) 196 printf("NIC: serial EEPROM read time out!\n"); 197 addr[i] = le16toh(CSR_READ_2(l, STGE_EepromData)); 198 } 199 (void)memcpy(en, addr, 6); 200 201 /* try to read MAC from Flash, when EEPROM is empty/missing */ 202 if (memcmp(en, bad[0], 6) == 0 || memcmp(en, bad[1], 6) == 0) 203 read_mac_from_flash(en); 204 205 /* set the station address now */ 206 for (i = 0; i < 6; i++) 207 CSR_WRITE_1(l, STGE_StationAddress0 + i, en[i]); 208 } 209 210 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 211 en[0], en[1], en[2], en[3], en[4], en[5]); 212 213 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, 214 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); 215 216 /* setup descriptors */ 217 txd = &l->txd[0]; 218 txd[0].xd0 = htole64(VTOPHYS(&txd[1])); 219 txd[0].xd1 = htole64(T1_EMPTY); 220 txd[1].xd0 = htole64(VTOPHYS(&txd[0])); 221 txd[1].xd1 = htole64(T1_EMPTY); 222 rxd = &l->rxd[0]; 223 rxd[0].xd0 = htole64(VTOPHYS(&rxd[1])); 224 rxd[0].xd2 = htole64(VTOPHYS(l->rxstore[0]) | 225 ((uint64_t)FRAMESIZE << 48)); 226 rxd[1].xd0 = htole64(VTOPHYS(&rxd[0])); 227 rxd[1].xd2 = htole64(VTOPHYS(l->rxstore[1]) | 228 ((uint64_t)FRAMESIZE << 48)); 229 wbinv(l, sizeof(struct local)); 230 231 CSR_WRITE_2(l, STGE_IntEnable, 0); 232 CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast | 233 RM_ReceiveBroadcast | RM_ReceiveAllFrames | RM_ReceiveMulticast); 234 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0); 235 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd)); 236 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0); 237 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd)); 238 CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE); 239 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */ 240 macctl = MC_StatisticsDisable | MC_TxEnable | MC_RxEnable; 241 242 if (PCI_REVISION(pcicfgread(tag, PCI_CLASS_REG)) >= 6) { 243 /* some workarounds for revisions >= 6 */ 244 CSR_WRITE_2(l, STGE_DebugCtrl, 245 CSR_READ_2(l, STGE_DebugCtrl) | 0x0200); 246 CSR_WRITE_2(l, STGE_DebugCtrl, 247 CSR_READ_2(l, STGE_DebugCtrl) | 0x0010); 248 CSR_WRITE_2(l, STGE_DebugCtrl, 249 CSR_READ_2(l, STGE_DebugCtrl) | 0x0020); 250 } 251 252 /* auto negotiation, set the current media */ 253 mii_dealan(l, 5); 254 255 reg = CSR_READ_1(l, STGE_PhyCtrl); 256 switch (PC_LinkSpeed(reg)) { 257 case PC_LinkSpeed_1000: 258 printf("1000Mbps"); 259 break; 260 case PC_LinkSpeed_100: 261 printf("100Mbps"); 262 break; 263 case PC_LinkSpeed_10: 264 printf("10Mbps"); 265 break; 266 } 267 if (reg & PC_PhyDuplexStatus) { 268 macctl |= MC_DuplexSelect; 269 printf("-FDX"); 270 } 271 printf("\n"); 272 CSR_WRITE_4(l, STGE_MACCtrl, macctl); 273 274 return l; 275 } 276 277 void 278 stg_shutdown(void *dev) 279 { 280 struct local *l = dev; 281 282 /* 283 * We have to reset the chip, when we don't need it anymore, 284 * otherwise bad things will happen (e.g. the DSM-G600 will no 285 * longer be able to reboot). 286 */ 287 stg_reset(l); 288 } 289 290 int 291 stg_send(void *dev, char *buf, unsigned len) 292 { 293 struct local *l = dev; 294 volatile struct desc *txd; 295 unsigned loop; 296 297 wbinv(buf, len); 298 txd = &l->txd[l->tx]; 299 txd->xd2 = htole64(VTOPHYS(buf) | ((uint64_t)len << 48)); 300 txd->xd1 = htole64(T1_NOALIGN | (1 << 24)); 301 wbinv(txd, sizeof(struct desc)); 302 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow); 303 loop = 100; 304 do { 305 if ((le64toh(txd->xd1) & T1_EMPTY) != 0) 306 goto done; 307 DELAY(10); 308 inv(txd, sizeof(struct desc)); 309 } while (--loop > 0); 310 printf("xmit failed\n"); 311 return -1; 312 done: 313 l->tx ^= 1; 314 return len; 315 } 316 317 int 318 stg_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 319 { 320 struct local *l = dev; 321 volatile struct desc *rxd; 322 uint32_t sts; 323 unsigned bound, len; 324 uint8_t *ptr; 325 326 bound = 1000 * timo; 327 again: 328 rxd = &l->rxd[l->rx]; 329 do { 330 inv(rxd, sizeof(struct desc)); 331 sts = (uint32_t)le64toh(rxd->xd1); 332 if ((sts & R1_DONE) != 0) 333 goto gotone; 334 DELAY(1000); /* 1 milli second */ 335 } while (--bound > 0); 336 errno = 0; 337 return -1; 338 gotone: 339 if ((sts & R1_ER_MASK) != 0) { 340 rxd->xd1 = 0; 341 wbinv(rxd, sizeof(struct desc)); 342 l->rx ^= 1; 343 goto again; 344 } 345 len = sts & R1_FL_MASK; 346 if (len > maxlen) 347 len = maxlen; 348 ptr = l->rxstore[l->rx]; 349 inv(ptr, len); 350 memcpy(buf, ptr, len); 351 rxd->xd1 = 0; 352 wbinv(rxd, sizeof(struct desc)); 353 l->rx ^= 1; 354 return len; 355 } 356 357 static void 358 stg_reset(struct local *l) 359 { 360 uint32_t reg; 361 int i; 362 363 reg = CSR_READ_4(l, STGE_AsicCtrl); 364 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset | 365 AC_TxReset | AC_DMA | AC_FIFO | AC_Network | AC_Host | 366 AC_AutoInit | ((reg & AC_PhyMedia) ? AC_RstOut : 0)); 367 DELAY(50000); 368 for (i = 0; i < 1000; i++) { 369 DELAY(5000); 370 if ((CSR_READ_4(l, STGE_AsicCtrl) & AC_ResetBusy) == 0) 371 break; 372 } 373 if (i >= 1000) 374 printf("NIC reset failed to complete!\n"); 375 DELAY(1000); 376 } 377 378 #define R0110 6 /* 0110b read op */ 379 #define W0101 5 /* 0101b write op */ 380 #define A10 2 /* 10b ack turn around */ 381 382 /* read the MII by bitbanging STGE_PhyCtrl */ 383 static int 384 mii_read(struct local *l, int phy, int reg) 385 { 386 unsigned data; 387 int i; 388 uint8_t v; 389 390 /* initiate read access */ 391 data = (R0110 << 10) | (phy << 5) | reg; 392 mii_bitbang_sync(l); 393 mii_bitbang_send(l, data, 14); /* 4OP + 5PHY + 5REG */ 394 395 /* switch direction to PHY->host */ 396 v = l->phyctrl_saved; 397 CSR_WRITE_1(l, STGE_PhyCtrl, v); 398 399 /* read data */ 400 data = 0; 401 for (i = 0; i < 18; i++) { /* 2TA + 16DATA */ 402 data <<= 1; 403 data |= !!(CSR_READ_1(l, STGE_PhyCtrl) & PC_MgmtData); 404 mii_bitbang_clk(l, v); 405 } 406 407 return data & 0xffff; 408 } 409 410 /* write the MII by bitbanging STGE_PhyCtrl */ 411 static void 412 mii_write(struct local *l, int phy, int reg, int val) 413 { 414 unsigned data; 415 416 data = (W0101 << 28) | (phy << 23) | (reg << 18) | (A10 << 16); 417 data |= val; 418 419 mii_bitbang_sync(l); 420 mii_bitbang_send(l, data, 32); /* 4OP + 5PHY + 5REG + 2TA + 16DATA */ 421 } 422 423 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 424 #define BMCR_RESET 0x8000 /* reset */ 425 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 426 #define BMCR_ISO 0x0400 /* isolate */ 427 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 428 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 429 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 430 #define BMSR_LINK 0x0004 /* Link status */ 431 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 432 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 433 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 434 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 435 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 436 #define ANAR_10 0x0020 /* local device supports 10bT */ 437 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 438 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 439 440 static void 441 mii_initphy(struct local *l) 442 { 443 int phy, ctl, sts, bound; 444 445 l->phyctrl_saved = CSR_READ_1(l, STGE_PhyCtrl) & 446 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 447 448 for (phy = 0; phy < 32; phy++) { 449 ctl = mii_read(l, phy, MII_BMCR); 450 sts = mii_read(l, phy, MII_BMSR); 451 if (ctl != 0xffff && sts != 0xffff && sts != 0) 452 goto found; 453 } 454 printf("MII: no PHY found\n"); 455 return; 456 457 found: 458 ctl = mii_read(l, phy, MII_BMCR); 459 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 460 461 bound = 100; 462 do { 463 DELAY(10); 464 ctl = mii_read(l, phy, MII_BMCR); 465 if (ctl == 0xffff) { 466 printf("MII: PHY %d has died after reset\n", phy); 467 return; 468 } 469 } while (bound-- > 0 && (ctl & BMCR_RESET)); 470 if (bound == 0) 471 printf("PHY %d reset failed\n", phy); 472 473 ctl &= ~BMCR_ISO; 474 mii_write(l, phy, MII_BMCR, ctl); 475 sts = mii_read(l, phy, MII_BMSR) | 476 mii_read(l, phy, MII_BMSR); /* read twice */ 477 l->phy = phy; 478 l->bmsr = sts; 479 } 480 481 static void 482 mii_dealan(struct local *l, unsigned timo) 483 { 484 unsigned anar, bound; 485 486 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 487 mii_write(l, l->phy, MII_ANAR, anar); 488 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 489 l->anlpar = 0; 490 bound = getsecs() + timo; 491 do { 492 l->bmsr = mii_read(l, l->phy, MII_BMSR) | 493 mii_read(l, l->phy, MII_BMSR); /* read twice */ 494 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 495 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 496 break; 497 } 498 DELAY(10 * 1000); 499 } while (getsecs() < bound); 500 } 501 502 static void 503 mii_bitbang_sync(struct local *l) 504 { 505 int i; 506 uint8_t v; 507 508 v = l->phyctrl_saved | PC_MgmtDir | PC_MgmtData; 509 CSR_WRITE_1(l, STGE_PhyCtrl, v); 510 DELAY(1); 511 for (i = 0; i < 32; i++) 512 mii_bitbang_clk(l, v); 513 } 514 515 static void 516 mii_bitbang_send(struct local *l, uint32_t data, int nbits) 517 { 518 uint32_t i; 519 uint8_t v; 520 521 v = l->phyctrl_saved | PC_MgmtDir; 522 CSR_WRITE_1(l, STGE_PhyCtrl, v); 523 DELAY(1); 524 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 525 if (data & i) 526 v |= PC_MgmtData; 527 else 528 v &= ~PC_MgmtData; 529 CSR_WRITE_1(l, STGE_PhyCtrl, v); 530 DELAY(1); 531 mii_bitbang_clk(l, v); 532 } 533 } 534 535 static void 536 mii_bitbang_clk(struct local *l, uint8_t v) 537 { 538 539 CSR_WRITE_1(l, STGE_PhyCtrl, v | PC_MgmtClk); 540 DELAY(1); 541 CSR_WRITE_1(l, STGE_PhyCtrl, v); 542 DELAY(1); 543 } 544 545 static int 546 eeprom_wait(struct local *l) 547 { 548 int i; 549 550 for (i = 0; i < 1000; i++) { 551 DELAY(1000); 552 if ((CSR_READ_2(l, STGE_EepromCtrl) & EC_EepromBusy) == 0) 553 return 0; 554 } 555 return 1; 556 } 557
Indexes created Sat Sep 20 22:09:52 GMT 2025