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    Searched defs:stream_res (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 92 * Groups in stream_res are stored as +1 from HW registers, i.e.
93 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
110 if (pipe_ctx->stream_res.gsl_group > 0)
115 pipe_ctx->stream_res.gsl_group = group_idx;
137 group_idx = pipe_ctx->stream_res.gsl_group;
141 pipe_ctx->stream_res.gsl_group = 0;
165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
167 pipe_ctx->stream_res.tg->funcs->set_gsl(
168 pipe_ctx->stream_res.tg
941 struct stream_resource *stream_res = &pipe_ctx->stream_res; local in function:dcn20_blank_pixel_data
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 100 tg = pipe_ctx->stream_res.tg;
469 struct timing_generator *tg = pipe_ctx->stream_res.tg;
798 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
802 &pipe_ctx->stream_res.pix_clk_params,
808 pipe_ctx->stream_res.tg->funcs->program_timing(
809 pipe_ctx->stream_res.tg,
822 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
824 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
825 pipe_ctx->stream_res.opp
2370 struct stream_resource *stream_res = &pipe_ctx->stream_res; local in function:dcn10_blank_pixel_data
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 283 struct stream_resource stream_res; member in struct:pipe_ctx

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