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      1 /*	$NetBSD: sh_arch.cpp,v 1.15 2008/04/28 20:23:20 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <hpcboot.h>
     33 #include <hpcmenu.h>
     34 #include <sh3/sh_arch.h>
     35 
     36 SH_BOOT_FUNC_(7707);
     37 SH_BOOT_FUNC_(7709);
     38 SH_BOOT_FUNC_(7709A);
     39 SH_BOOT_FUNC_(7750);
     40 
     41 static int _cpu_type;
     42 
     43 int
     44 SHArchitecture::cpu_type()
     45 {
     46 	if (_cpu_type == 0) {
     47 #if _WIN32_WCE == 101
     48 		_cpu_type = 3;
     49 #else
     50 		SYSTEM_INFO si;
     51 		GetSystemInfo(&si);
     52 		_cpu_type = si.wProcessorLevel;
     53 #endif
     54 	}
     55 
     56 	return _cpu_type;
     57 }
     58 
     59 BOOL
     60 SHArchitecture::init()
     61 {
     62 
     63 	if (!_mem->init()) {
     64 		DPRINTF((TEXT("can't initialize memory manager.\n")));
     65 		return FALSE;
     66 	}
     67 	// D-RAM information
     68 	DPRINTF((TEXT("Memory Bank:\n")));
     69 
     70 	return TRUE;
     71 }
     72 
     73 void
     74 SHArchitecture::systemInfo()
     75 {
     76 
     77 	// Windows CE common information.
     78 	super::systemInfo();
     79 
     80 	// CPU specific.
     81 	_dev->dump(HPC_MENU._cons_parameter);
     82 }
     83 
     84 BOOL
     85 SHArchitecture::setupLoader()
     86 {
     87 	vaddr_t v;
     88 
     89 	if (!_mem->getPage(v , _loader_addr)) {
     90 		DPRINTF((TEXT("can't get page for 2nd loader.\n")));
     91 		return FALSE;
     92 	}
     93 	_loader_addr = ptokv(_loader_addr);
     94 
     95 	DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"),
     96 	    (unsigned)v,(unsigned)_loader_addr));
     97 
     98 	memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize());
     99 
    100 	return TRUE;
    101 }
    102 
    103 void
    104 SHArchitecture::jump(paddr_t info, paddr_t pvec)
    105 {
    106 	kaddr_t sp;
    107 	vaddr_t v;
    108 	paddr_t p;
    109 
    110 	// stack for bootloader
    111 	_mem->getPage(v, p);
    112 	sp = ptokv(p + _mem->getPageSize() / 2);
    113 
    114 	info = ptokv(info);
    115 	pvec = ptokv(pvec);
    116 
    117 	DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"),
    118 	    info, sp));
    119 
    120 	// Change to privilege-mode.
    121 	SetKMode(1);
    122 
    123 	// Cache flush(for 2nd bootloader)
    124 	//
    125 	// SH4 uses WinCE CacheSync(). this routine may causes TLB
    126 	// exception. so calls before suspendIntr().
    127 	//
    128 	cache_flush();
    129 
    130 	// Disable external interrupt.
    131 	suspendIntr();
    132 
    133 	// jump to 2nd loader.(run P1) at this time I still use MMU.
    134 	__asm(
    135 	    "mov	r6, r15\n"
    136 	    "jmp	@r7\n"
    137 	    "nop	\n", info, pvec, sp, _loader_addr);
    138 	// NOTREACHED
    139 }
    140 
    141 // disable external interrupt and save its priority.
    142 uint32_t
    143 suspendIntr()
    144 {
    145 	uint32_t sr;
    146 
    147 	__asm(
    148 	    "stc	sr, r0\n"
    149 	    "mov.l	r0, @r4\n"
    150 	    "or		r5, r0\n"
    151 	    "ldc	r0, sr\n", &sr, 0x000000f0);
    152 	return sr & 0x000000f0;
    153 }
    154 
    155 // resume external interrupt priority.
    156 void
    157 resumeIntr(uint32_t s)
    158 {
    159 
    160 	__asm(
    161 	    "stc	sr, r0\n"
    162 	    "and	r5, r0\n"
    163 	    "or		r4, r0\n"
    164 	    "ldc	r0, sr\n", s, 0xffffff0f);
    165 }
    166