/src/sys/arch/powerpc/ibm4xx/dev/ |
wdog.c | 148 uint32_t tcr = mfspr(SPR_TCR); local in function:wdog_setmode 149 tcr |= TCR_WP_2_29 | TCR_WRC_SYSTEM; 150 mtspr(SPR_TCR, tcr);
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/src/sys/arch/powerpc/booke/dev/ |
e500wdog.c | 123 uint32_t tcr = mfspr(SPR_TCR); local in function:e500wdog_setmode 125 tcr = (tcr & ~TCR_WRC) | TCR_WRC_RESET | TCR_WIE; 128 tcr &= ~(TCR_WP|TCR_WPEXT); 129 tcr |= __SHIFTIN(wp, TCR_WP) | __SHIFTIN(wp >> 2, TCR_WPEXT); 130 mtspr(SPR_TCR, tcr); 150 const uint32_t tcr = mfspr(SPR_TCR); local in function:e500wdog_attach 151 u_int wp = __SHIFTOUT(tcr, TCR_WP) | (__SHIFTOUT(tcr, TCR_WPEXT) << 2); 154 printf(" tcr=%#x wp=%u", tcr, wp) [all...] |
/src/sys/arch/pmax/ibus/ |
dz_ibus.c | 125 uint16_t tcr; /* 10 Tcr: transmit console */ member in struct:dzregs 189 i = dz->tcr; 191 dz->tcr = 0; 194 dz->tcr = 1; 197 dz->tcr = i; 292 dzcn->tcr = (1 << line); 339 uint16_t tcr; local in function:dz_ibus_cnputc 347 tcr = dzcn->tcr; 431 uint16_t tcr; local in function:dzputc [all...] |
/src/sys/arch/vax/vsa/ |
dz_vsbus.c | 80 REG(tcr); /* 08 Tcr: transmit console register */ 117 i = dzP->tcr; 119 dzP->tcr = 0; 121 dzP->tcr = 1; 123 dzP->tcr = i; 284 dz->tcr = (1 << minor(cndev->cn_dev)); /* Turn on xmitter */ 294 dz->tcr = (1 << minor(cndev->cn_dev)); /* Turn on xmitter */ 305 u_short tcr; local in function:dzcnputc 311 tcr = dz->tcr; /* remember which lines to scan * 364 u_short tcr; local in function:dzputc [all...] |
/src/sys/dev/dec/ |
dz.c | 312 u_char tcr; local in function:dzxint 353 tcr = dz_read2(sc, sc->sc_dr.dr_tcrw); 354 tcr &= 255; 355 tcr &= ~(1 << line); 356 dz_write1(sc, sc->sc_dr.dr_tcr, tcr);
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/src/sys/arch/aarch64/aarch64/ |
cpufunc.c | 477 uint64_t tcr; local in function:aarch64_hafdbs_init 519 tcr = reg_tcr_el1_read(); 526 reg_tcr_el1_write(tcr | TCR_HA); 531 reg_tcr_el1_write(tcr | TCR_HD | TCR_HA);
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aarch64_machdep.c | 179 uint64_t tcr = reg_tcr_el1_read(); local in function:cpu_kernel_vm_init 180 reg_tcr_el1_write(tcr | TCR_EPD0); 462 uint64_t tcr = reg_tcr_el1_read(); local in function:set_user_tagged_address 465 tcr |= TCR_TBI0; 467 tcr &= ~TCR_TBI0; 468 reg_tcr_el1_write(tcr); 476 uint64_t tcr; local in function:sysctl_machdep_tagged_address 478 tcr = reg_tcr_el1_read(); 479 cur = val = (tcr & TCR_TBI0) ? 1 : 0;
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pmap.c | 1409 uint64_t tcr = reg_tcr_el1_read(); local in function:pmap_activate_efirt 1410 reg_tcr_el1_write(tcr & ~TCR_EPD0); 1422 uint64_t tcr; local in function:pmap_activate 1445 tcr = reg_tcr_el1_read(); 1446 reg_tcr_el1_write(tcr & ~TCR_EPD0); 1466 uint64_t tcr = reg_tcr_el1_read(); local in function:pmap_deactivate_efirt 1467 reg_tcr_el1_write(tcr | TCR_EPD0); 1486 uint64_t tcr; local in function:pmap_deactivate 1495 tcr = reg_tcr_el1_read(); 1496 reg_tcr_el1_write(tcr | TCR_EPD0) [all...] |
/src/sys/arch/arm/sunxi/ |
sun6i_spi.c | 194 uint32_t tcr, cctl; local in function:sun6ispi_configure 206 tcr = SPI_TCR_SS_LEVEL | SPI_TCR_SPOL; 210 tcr |= 0; 213 tcr |= SPI_TCR_CPHA; 216 tcr |= SPI_TCR_CPOL; 219 tcr |= SPI_TCR_CPHA|SPI_TCR_CPOL; 225 sc->sc_TCR = tcr; 240 device_printf(sc->sc_dev, "tcr 0x%x, cctl 0x%x, CLK %uHz, SCLK %uHz\n", 241 tcr, cctl, sc->sc_modclkrate, 271 uint32_t isr, tcr; local in function:sun6ispi_start [all...] |
/src/sys/dev/sbus/ |
bpp.c | 228 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 254 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 354 uint8_t tcr; local in function:bppwrite 370 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 372 tcr &= ~BPP_TCR_DIR; 374 L64854_REG_TCR, tcr);
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/src/sys/arch/amiga/dev/ |
if_es.c | 209 printf("TCR %04x EPHSR %04x RCR %04x ECR %04x MIR %04x MCR %04x\n", 210 SWAP(smc->b0.tcr), SWAP(smc->b0.ephsr), SWAP(smc->b0.rcr), 245 smc->b0.tcr = 0; 285 smc->b0.tcr = TCR_PAD_EN | (TCR_TXENA + TCR_MON_CSN); 431 u_short save_ptr, ephsr, tcr; local in function:esintr 448 tcr = smc->b0.tcr; /* and TCR */ 462 if ((smc->b2.data & EPHSR_TX_SUC) == 0 && (tcr & TCR_TXENA) == 0) { 470 smc->b0.tcr |= TCR_TXENA [all...] |
if_esreg.h | 34 volatile u_short tcr; /* Transmit Control Register */ member in struct:smcregs::__anonf052b2be0108
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/src/sys/arch/sandpoint/stand/altboot/ |
rge.c | 124 unsigned tcr, rcr; member in struct:local 216 l->tcr = (03 << 24) | (07 << 8); 221 CSR_WRITE_4(l, RGE_TCR, l->tcr);
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/src/sys/arch/evbppc/virtex/dev/ |
if_temac.c | 582 uint32_t rcr, tcr; local in function:temac_init 600 tcr = (gmi_read_4(TEMAC_GMI_TXCF) | GMI_TX_ENABLE) & 602 gmi_write_4(TEMAC_GMI_TXCF, tcr); 1252 uint32_t rcr, tcr; local in function:temac_reset 1263 tcr = gmi_read_4(TEMAC_GMI_TXCF) & ~GMI_TX_ENABLE; 1264 gmi_write_4(TEMAC_GMI_TXCF, tcr);
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/src/sys/arch/arm/imx/ |
if_enet.c | 1121 uint32_t tcr, tcr0; local in function:enet_miibus_statchg 1130 tcr0 = tcr = ENET_REG_READ(sc, ENET_TCR); 1139 tcr |= ENET_TCR_FDEN; /* full duplex */ 1142 tcr &= ~ENET_TCR_FDEN; /* half duplex */ 1146 if ((tcr ^ tcr0) & ENET_TCR_FDEN) { 1172 tcr = tcr0; 1189 if (tcr != tcr0) 1190 ENET_REG_WRITE(sc, ENET_TCR, tcr);
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/src/sys/arch/powerpc/booke/ |
e500_intr.c | 1404 uint32_t tcr = mfspr(SPR_TCR); local in function:e500_intr_cpu_hatch 1405 tcr |= TCR_WIE; 1406 mtspr(SPR_TCR, tcr);
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/src/sys/dev/ic/ |
rtw.c | 347 uint32_t tcr; local in function:rtw_continuous_tx_enable 348 tcr = RTW_READ(regs, RTW_TCR); 349 tcr &= ~RTW_TCR_LBK_MASK; 351 tcr |= RTW_TCR_LBK_CONT; 353 tcr |= RTW_TCR_LBK_NORMAL; 354 RTW_WRITE(regs, RTW_TCR, tcr); 519 uint32_t tcr; local in function:rtw_chip_reset 522 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | 525 RTW_WRITE(regs, RTW_TCR, tcr); 2591 uint32_t tcr; local in function:rtw_transmit_config [all...] |