1 /* $NetBSD: tegra210_pinmux.c,v 1.2 2019/09/28 07:42:47 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_pinmux.c,v 1.2 2019/09/28 07:42:47 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/types.h> 36 37 #include <arm/nvidia/tegra_pinmux.h> 38 39 #define TEGRA_PIN(n, r, f1, f2, f3, f4) \ 40 { \ 41 .tpp_name = n, \ 42 .tpp_reg = (r), \ 43 .tpp_type = TEGRA_PINMUX, \ 44 .tpp_functions = { \ 45 f1, f2, f3, f4 \ 46 } \ 47 } 48 49 #define TEGRA_PINGROUP(n, r, drvdn_m, drvup_m, slwrr_m, slwrf_m) \ 50 { \ 51 .tpp_name = "drive_" n, \ 52 .tpp_reg = (r) - 0x8d4, \ 53 .tpp_type = TEGRA_PADCTRL, \ 54 .tpp_dg = { \ 55 .drvdn_mask = drvdn_m, \ 56 .drvup_mask = drvup_m, \ 57 .slwrr_mask = slwrr_m, \ 58 .slwrf_mask = slwrf_m \ 59 } \ 60 } 61 62 // 9.15 Pinmux registers 63 static const struct tegra_pinmux_pins tegra210_pins[] = { 64 TEGRA_PIN("sdmmc1_clk_pm0", 0x00, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 65 TEGRA_PIN("sdmmc1_cmd_pm1", 0x04, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 66 TEGRA_PIN("sdmmc1_dat3_pm2", 0x08, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 67 TEGRA_PIN("sdmmc1_dat2_pm3", 0x0c, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 68 TEGRA_PIN("sdmmc1_dat1_pm4", 0x10, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 69 TEGRA_PIN("sdmmc1_dat0_pm5", 0x14, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 70 TEGRA_PIN("sdmmc3_clk_pp0", 0x1c, "sdmmc3", "rsvd1", "rsvd2", "rsvd3"), 71 TEGRA_PIN("sdmmc3_cmd_pp1", 0x20, "sdmmc3", "rsvd1", "rsvd2", "rsvd3"), 72 TEGRA_PIN("sdmmc3_dat0_pp5", 0x24, "sdmmc3", "rsvd1", "rsvd2", "rsvd3"), 73 TEGRA_PIN("sdmmc3_dat1_pp4", 0x28, "sdmmc3", "rsvd1", "rsvd2", "rsvd3"), 74 TEGRA_PIN("sdmmc3_dat2_pp3", 0x2c, "sdmmc3", "rsvd1", "rsvd2", "rsvd3"), 75 TEGRA_PIN("sdmmc3_dat3_pp2", 0x30, "sdmmc3", "rsvd1", "rsvd2", "rsvd3"), 76 TEGRA_PIN("pex_l0_rst_n_pa0", 0x38, "pe0", "rsvd1", "rsvd2", "rsvd3"), 77 TEGRA_PIN("pex_l0_clkreq_n_pa1", 0x3c, "pe0", "rsvd1", "rsvd2", "rsvd3"), 78 TEGRA_PIN("pex_wake_n_pa2", 0x40, "pe", "rsvd1", "rsvd2", "rsvd3"), 79 TEGRA_PIN("pex_l1_rst_n_pa3", 0x44, "pe1", "rsvd1", "rsvd2", "rsvd3"), 80 TEGRA_PIN("pex_l1_clkreq_n_pa4", 0x48, "pe1", "rsvd1", "rsvd2", "rsvd3"), 81 TEGRA_PIN("sata_led_active_pa5", 0x4c, "sata", "rsvd1", "rsvd2", "rsvd3"), 82 TEGRA_PIN("spi1_mosi_pc0", 0x50, "spi1", "rsvd1", "rsvd2", "rsvd3"), 83 TEGRA_PIN("spi1_miso_pc1", 0x54, "spi1", "rsvd1", "rsvd2", "rsvd3"), 84 TEGRA_PIN("spi1_sck_pc2", 0x58, "spi1", "rsvd1", "rsvd2", "rsvd3"), 85 TEGRA_PIN("spi1_cs0_pc3", 0x5c, "spi1", "rsvd1", "rsvd2", "rsvd3"), 86 TEGRA_PIN("spi1_cs1_pc4", 0x60, "spi1", "rsvd1", "rsvd2", "rsvd3"), 87 TEGRA_PIN("spi2_mosi_pb4", 0x64, "spi2", "dtv", "rsvd2", "rsvd3"), 88 TEGRA_PIN("spi2_miso_pb5", 0x68, "spi2", "dtv", "rsvd2", "rsvd3"), 89 TEGRA_PIN("spi2_sck_pb6", 0x6c, "spi2", "dtv", "rsvd2", "rsvd3"), 90 TEGRA_PIN("spi2_cs0_pb7", 0x70, "spi2", "dtv", "rsvd2", "rsvd3"), 91 TEGRA_PIN("spi2_cs1_pdd0", 0x74, "spi2", "rsvd1", "rsvd2", "rsvd3"), 92 TEGRA_PIN("spi4_mosi_pc7", 0x78, "spi4", "rsvd1", "rsvd2", "rsvd3"), 93 TEGRA_PIN("spi4_miso_pd0", 0x7c, "spi4", "rsvd1", "rsvd2", "rsvd3"), 94 TEGRA_PIN("spi4_sck_pc5", 0x80, "spi4", "rsvd1", "rsvd2", "rsvd3"), 95 TEGRA_PIN("spi4_cs0_pc6", 0x84, "spi4", "rsvd1", "rsvd2", "rsvd3"), 96 TEGRA_PIN("qspi_sck_pee0", 0x88, "qspi", "rsvd1", "rsvd2", "rsvd3"), 97 TEGRA_PIN("qspi_cs_n_pee1", 0x8c, "qspi", "rsvd1", "rsvd2", "rsvd3"), 98 TEGRA_PIN("qspi_io0_pee2", 0x90, "qspi", "rsvd1", "rsvd2", "rsvd3"), 99 TEGRA_PIN("qspi_io1_pee3", 0x94, "qspi", "rsvd1", "rsvd2", "rsvd3"), 100 TEGRA_PIN("qspi_io2_pee4", 0x98, "qspi", "rsvd1", "rsvd2", "rsvd3"), 101 TEGRA_PIN("qspi_io3_pee5", 0x9c, "qspi", "rsvd1", "rsvd2", "rsvd3"), 102 TEGRA_PIN("dmic1_clk_pe0", 0xa4, "dmic1", "i2s3", "rsvd2", "rsvd3"), 103 TEGRA_PIN("dmic1_dat_pe1", 0xa8, "dmic1", "i2s3", "rsvd2", "rsvd3"), 104 TEGRA_PIN("dmic2_clk_pe2", 0xac, "dmic2", "i2s3", "rsvd2", "rsvd3"), 105 TEGRA_PIN("dmic2_dat_pe3", 0xb0, "dmic2", "i2s3", "rsvd2", "rsvd3"), 106 TEGRA_PIN("dmic3_clk_pe4", 0xb4, "dmic3", "i2s5a", "rsvd2", "rsvd3"), 107 TEGRA_PIN("dmic3_dat_pe5", 0xb8, "dmic3", "i2s5a", "rsvd2", "rsvd3"), 108 TEGRA_PIN("gen1_i2c_scl_pj1", 0xbc, "i2c1", "rsvd1", "rsvd2", "rsvd3"), 109 TEGRA_PIN("gen1_i2c_sda_pj0", 0xc0, "i2c1", "rsvd1", "rsvd2", "rsvd3"), 110 TEGRA_PIN("gen2_i2c_scl_pj2", 0xc4, "i2c2", "rsvd1", "rsvd2", "rsvd3"), 111 TEGRA_PIN("gen2_i2c_sda_pj3", 0xc8, "i2c2", "rsvd1", "rsvd2", "rsvd3"), 112 TEGRA_PIN("gen3_i2c_scl_pf0", 0xcc, "i2c3", "rsvd1", "rsvd2", "rsvd3"), 113 TEGRA_PIN("gen3_i2c_sda_pf1", 0xd0, "i2c3", "rsvd1", "rsvd2", "rsvd3"), 114 TEGRA_PIN("cam_i2c_scl_ps2", 0xd4, "i2c3", "i2cvi", "rsvd2", "rsvd3"), 115 TEGRA_PIN("cam_i2c_sda_ps3", 0xd8, "i2c3", "i2cvi", "rsvd2", "rsvd3"), 116 TEGRA_PIN("pwr_i2c_scl_py3", 0xdc, "i2cpmu", "rsvd1", "rsvd2", "rsvd3"), 117 TEGRA_PIN("pwr_i2c_sda_py4", 0xe0, "i2cpmu", "rsvd1", "rsvd2", "rsvd3"), 118 TEGRA_PIN("uart1_tx_pu0", 0xe4, "uarta", "rsvd1", "rsvd2", "rsvd3"), 119 TEGRA_PIN("uart1_rx_pu1", 0xe8, "uarta", "rsvd1", "rsvd2", "rsvd3"), 120 TEGRA_PIN("uart1_rts_pu2", 0xec, "uarta", "rsvd1", "rsvd2", "rsvd3"), 121 TEGRA_PIN("uart1_cts_pu3", 0xf0, "uarta", "rsvd1", "rsvd2", "rsvd3"), 122 TEGRA_PIN("uart2_tx_pg0", 0xf4, "uartb", "i2s4a", "spdif", "uart"), 123 TEGRA_PIN("uart2_rx_pg1", 0xf8, "uartb", "i2s4a", "spdif", "uart"), 124 TEGRA_PIN("uart2_rts_pg2", 0xfc, "uartb", "i2s4a", "rsvd2", "uart"), 125 TEGRA_PIN("uart2_cts_pg3", 0x100, "uartb", "i2s4a", "rsvd2", "uart"), 126 TEGRA_PIN("uart3_tx_pd1", 0x104, "uartc", "spi4", "rsvd2", "rsvd3"), 127 TEGRA_PIN("uart3_rx_pd2", 0x108, "uartc", "spi4", "rsvd2", "rsvd3"), 128 TEGRA_PIN("uart3_rts_pd3", 0x10c, "uartc", "spi4", "rsvd2", "rsvd3"), 129 TEGRA_PIN("uart3_cts_pd4", 0x110, "uartc", "spi4", "rsvd2", "rsvd3"), 130 TEGRA_PIN("uart4_tx_pi4", 0x114, "uartd", "uart", "rsvd2", "rsvd3"), 131 TEGRA_PIN("uart4_rx_pi5", 0x118, "uartd", "uart", "rsvd2", "rsvd3"), 132 TEGRA_PIN("uart4_rts_pi6", 0x11c, "uartd", "uart", "rsvd2", "rsvd3"), 133 TEGRA_PIN("uart4_cts_pi7", 0x120, "uartd", "uart", "rsvd2", "rsvd3"), 134 TEGRA_PIN("dap1_fs_pb0", 0x124, "i2s1", "rsvd1", "rsvd2", "rsvd3"), 135 TEGRA_PIN("dap1_din_pb1", 0x128, "i2s1", "rsvd1", "rsvd2", "rsvd3"), 136 TEGRA_PIN("dap1_dout_pb2", 0x12c, "i2s1", "rsvd1", "rsvd2", "rsvd3"), 137 TEGRA_PIN("dap1_sclk_pb3", 0x130, "i2s1", "rsvd1", "rsvd2", "rsvd3"), 138 TEGRA_PIN("dap2_fs_paa0", 0x134, "i2s2", "rsvd1", "rsvd2", "rsvd3"), 139 TEGRA_PIN("dap2_din_paa2", 0x138, "i2s2", "rsvd1", "rsvd2", "rsvd3"), 140 TEGRA_PIN("dap2_dout_paa3", 0x13c, "i2s2", "rsvd1", "rsvd2", "rsvd3"), 141 TEGRA_PIN("dap2_sclk_paa1", 0x140, "i2s2", "rsvd1", "rsvd2", "rsvd3"), 142 TEGRA_PIN("dap4_fs_pj4", 0x144, "i2s4b", "rsvd1", "rsvd2", "rsvd3"), 143 TEGRA_PIN("dap4_din_pj5", 0x148, "i2s4b", "rsvd1", "rsvd2", "rsvd3"), 144 TEGRA_PIN("dap4_dout_pj6", 0x14c, "i2s4b", "rsvd1", "rsvd2", "rsvd3"), 145 TEGRA_PIN("dap4_sclk_pj7", 0x150, "i2s4b", "rsvd1", "rsvd2", "rsvd3"), 146 TEGRA_PIN("cam1_mclk_ps0", 0x154, "extperiph3", "rsvd1", "rsvd2", "rsvd3"), 147 TEGRA_PIN("cam2_mclk_ps1", 0x158, "extperiph3", "rsvd1", "rsvd2", "rsvd3"), 148 TEGRA_PIN("jtag_rtck", 0x15c, "jtag", "rsvd1", "rsvd2", "rsvd3"), 149 TEGRA_PIN("clk_32k_in", 0x160, NULL, NULL, NULL, NULL), 150 TEGRA_PIN("clk_32k_out_py5", 0x164, "soc", "blink", "rsvd2", "rsvd3"), 151 TEGRA_PIN("batt_bcl", 0x168, "bcl", "rsvd1", "rsvd2", "rsvd3"), 152 TEGRA_PIN("clk_req", 0x16c, NULL, NULL, NULL, NULL), 153 TEGRA_PIN("cpu_pwr_req", 0x170, NULL, NULL, NULL, NULL), 154 TEGRA_PIN("pwr_int_n", 0x174, NULL, NULL, NULL, NULL), 155 TEGRA_PIN("shutdown", 0x178, NULL, NULL, NULL, NULL), 156 TEGRA_PIN("core_pwr_req", 0x17c, NULL, NULL, NULL, NULL), 157 TEGRA_PIN("aud_mclk_pbb0", 0x180, "aud", "rsvd1", "rsvd2", "rsvd3"), 158 TEGRA_PIN("dvfs_pwm_pbb1", 0x184, "rsvd0", "cldvfs", "spi3", "rsvd3"), 159 TEGRA_PIN("dvfs_clk_pbb2", 0x188, "rsvd0", "cldvfs", "spi3", "rsvd3"), 160 TEGRA_PIN("gpio_x1_aud_pbb3", 0x18c, "rsvd0", "rsvd1", "spi3", "rsvd3"), 161 TEGRA_PIN("gpio_x3_aud_pbb4", 0x190, "rsvd0", "rsvd1", "spi3", "rsvd3"), 162 TEGRA_PIN("pcc7", 0x194, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 163 TEGRA_PIN("hdmi_cec_pcc0", 0x198, "cec", "rsvd1", "rsvd2", "rsvd3"), 164 TEGRA_PIN("hdmi_int_dp_hpd_pcc1", 0x19c, "dp", "rsvd1", "rsvd2", "rsvd3"), 165 TEGRA_PIN("spdif_out_pcc2", 0x1a0, "spdif", "rsvd1", "rsvd2", "rsvd3"), 166 TEGRA_PIN("spdif_in_pcc3", 0x1a4, "spdif", "rsvd1", "rsvd2", "rsvd3"), 167 TEGRA_PIN("usb_vbus_en0_pcc4", 0x1a8, "usb", "rsvd1", "rsvd2", "rsvd3"), 168 TEGRA_PIN("usb_vbus_en1_pcc5", 0x1ac, "usb", "rsvd1", "rsvd2", "rsvd3"), 169 TEGRA_PIN("dp_hpd0_pcc6", 0x1b0, "dp", "rsvd1", "rsvd2", "rsvd3"), 170 TEGRA_PIN("wifi_en_ph0", 0x1b4, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 171 TEGRA_PIN("wifi_rst_ph1", 0x1b8, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 172 TEGRA_PIN("wifi_wake_ap_ph2", 0x1bc, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 173 TEGRA_PIN("ap_wake_bt_ph3", 0x1c0, "rsvd0", "uartb", "spdif", "rsvd3"), 174 TEGRA_PIN("bt_rst_ph4", 0x1c4, "rsvd0", "uartb", "spdif", "rsvd3"), 175 TEGRA_PIN("bt_wake_ap_ph5", 0x1c8, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 176 TEGRA_PIN("ap_wake_nfc_ph7", 0x1cc, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 177 TEGRA_PIN("nfc_en_pi0", 0x1d0, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 178 TEGRA_PIN("nfc_int_pi1", 0x1d4, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 179 TEGRA_PIN("gps_en_pi2", 0x1d8, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 180 TEGRA_PIN("gps_rst_pi3", 0x1dc, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 181 TEGRA_PIN("cam_rst_ps4", 0x1e0, "vgp1", "rsvd1", "rsvd2", "rsvd3"), 182 TEGRA_PIN("cam_af_en_ps5", 0x1e4, "vimclk", "vgp2", "rsvd2", "rsvd3"), 183 TEGRA_PIN("cam_flash_en_ps6", 0x1e8, "vimclk", "vgp3", "rsvd2", "rsvd3"), 184 TEGRA_PIN("cam1_pwdn_ps7", 0x1ec, "vgp4", "rsvd1", "rsvd2", "rsvd3"), 185 TEGRA_PIN("cam2_pwdn_pt0", 0x1f0, "vgp5", "rsvd1", "rsvd2", "rsvd3"), 186 TEGRA_PIN("cam1_strobe_pt1", 0x1f4, "vgp6", "rsvd1", "rsvd2", "rsvd3"), 187 TEGRA_PIN("lcd_te_py2", 0x1f8, "displaya", "rsvd1", "rsvd2", "rsvd3"), 188 TEGRA_PIN("lcd_bl_pwm_pv0", 0x1fc, "displaya", "pwm0", "sor0", "rsvd3"), 189 TEGRA_PIN("lcd_bl_en_pv1", 0x200, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 190 TEGRA_PIN("lcd_rst_pv2", 0x204, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 191 TEGRA_PIN("lcd_gpio1_pv3", 0x208, "displayb", "rsvd1", "rsvd2", "rsvd3"), 192 TEGRA_PIN("lcd_gpio2_pv4", 0x20c, "displayb", "pwm1", "rsvd2", "sor1"), 193 TEGRA_PIN("ap_ready_pv5", 0x210, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 194 TEGRA_PIN("touch_rst_pv6", 0x214, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 195 TEGRA_PIN("touch_clk_pv7", 0x218, "touch", "rsvd1", "rsvd2", "rsvd3"), 196 TEGRA_PIN("modem_wake_ap_px0", 0x21c, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 197 TEGRA_PIN("touch_int_px1", 0x220, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 198 TEGRA_PIN("motion_int_px2", 0x224, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 199 TEGRA_PIN("als_prox_int_px3", 0x228, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 200 TEGRA_PIN("temp_alert_px4", 0x22c, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 201 TEGRA_PIN("button_power_on_px5", 0x230, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 202 TEGRA_PIN("button_vol_up_px6", 0x234, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 203 TEGRA_PIN("button_vol_down_px7", 0x238, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 204 TEGRA_PIN("button_slide_sw_py0", 0x23c, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 205 TEGRA_PIN("button_home_py1", 0x240, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 206 TEGRA_PIN("pa6", 0x244, "sata", "rsvd1", "rsvd2", "rsvd3"), 207 TEGRA_PIN("pe6", 0x248, "rsvd0", "i2s5a", "pwm2", "rsvd3"), 208 TEGRA_PIN("pe7", 0x24c, "rsvd0", "i2s5a", "pwm3", "rsvd3"), 209 TEGRA_PIN("ph6", 0x250, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 210 TEGRA_PIN("pk0", 0x254, "iqc0", "i2s5b", "rsvd2", "rsvd3"), 211 TEGRA_PIN("pk1", 0x258, "iqc0", "i2s5b", "rsvd2", "rsvd3"), 212 TEGRA_PIN("pk2", 0x25c, "iqc0", "i2s5b", "rsvd2", "rsvd3"), 213 TEGRA_PIN("pk3", 0x260, "iqc0", "i2s5b", "rsvd2", "rsvd3"), 214 TEGRA_PIN("pk4", 0x264, "iqc1", "rsvd1", "rsvd2", "rsvd3"), 215 TEGRA_PIN("pk5", 0x268, "iqc1", "rsvd1", "rsvd2", "rsvd3"), 216 TEGRA_PIN("pk6", 0x26c, "iqc1", "rsvd1", "rsvd2", "rsvd3"), 217 TEGRA_PIN("pk7", 0x270, "iqc1", "rsvd1", "rsvd2", "rsvd3"), 218 TEGRA_PIN("pl0", 0x274, "rsvd0", "rsvd1", "rsvd2", "rsvd3"), 219 TEGRA_PIN("pl1", 0x278, "soc", "rsvd1", "rsvd2", "rsvd3"), 220 TEGRA_PIN("pz0", 0x27c, "vimclk2", "rsvd1", "rsvd2", "rsvd3"), 221 TEGRA_PIN("pz1", 0x280, "vimclk2", "sdmmc1", "rsvd2", "rsvd3"), 222 TEGRA_PIN("pz2", 0x284, "sdmmc3", "ccla", "rsvd2", "rsvd3"), 223 TEGRA_PIN("pz3", 0x288, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 224 TEGRA_PIN("pz4", 0x28c, "sdmmc1", "rsvd1", "rsvd2", "rsvd3"), 225 TEGRA_PIN("pz5", 0x290, "soc", "rsvd1", "rsvd2", "rsvd3"), 226 227 TEGRA_PINGROUP("pa6", 0x9c0, __BITS(16, 12), __BITS(24, 20), 0, 0), 228 TEGRA_PINGROUP("pcc7", 0x9c4, __BITS(16, 12), __BITS(24, 20), 0, 0), 229 TEGRA_PINGROUP("pe6", 0x9c8, __BITS(16, 12), __BITS(24, 20), 0, 0), 230 TEGRA_PINGROUP("pe7", 0x9cc, __BITS(16, 12), __BITS(24, 20), 0, 0), 231 TEGRA_PINGROUP("ph6", 0x9d0, __BITS(16, 12), __BITS(24, 20), 0, 0), 232 TEGRA_PINGROUP("pk0", 0x9d4, 0, 0, __BITS(30, 28), __BITS(31, 30)), 233 TEGRA_PINGROUP("pk1", 0x9d8, 0, 0, __BITS(30, 28), __BITS(31, 30)), 234 TEGRA_PINGROUP("pk2", 0x9dc, 0, 0, __BITS(30, 28), __BITS(31, 30)), 235 TEGRA_PINGROUP("pk3", 0x9e0, 0, 0, __BITS(30, 28), __BITS(31, 30)), 236 TEGRA_PINGROUP("pk4", 0x9e4, 0, 0, __BITS(30, 28), __BITS(31, 30)), 237 TEGRA_PINGROUP("pk5", 0x9e8, 0, 0, __BITS(30, 28), __BITS(31, 30)), 238 TEGRA_PINGROUP("pk6", 0x9ec, 0, 0, __BITS(30, 28), __BITS(31, 30)), 239 TEGRA_PINGROUP("pk7", 0x9f0, 0, 0, __BITS(30, 28), __BITS(31, 30)), 240 TEGRA_PINGROUP("pl0", 0x9f4, 0, 0, __BITS(30, 28), __BITS(31, 30)), 241 TEGRA_PINGROUP("pl1", 0x9f8, 0, 0, __BITS(30, 28), __BITS(31, 30)), 242 TEGRA_PINGROUP("pz0", 0x9fc, __BITS(18, 12), __BITS(26, 20), 0, 0), 243 TEGRA_PINGROUP("pz1", 0xa00, __BITS(18, 12), __BITS(26, 20), 0, 0), 244 TEGRA_PINGROUP("pz2", 0xa04, __BITS(18, 12), __BITS(26, 20), 0, 0), 245 TEGRA_PINGROUP("pz3", 0xa08, __BITS(18, 12), __BITS(26, 20), 0, 0), 246 TEGRA_PINGROUP("pz4", 0xa0c, __BITS(18, 12), __BITS(26, 20), 0, 0), 247 TEGRA_PINGROUP("pz5", 0xa10, __BITS(18, 12), __BITS(26, 20), 0, 0), 248 TEGRA_PINGROUP("sdmmc1",0xa98, __BITS(18, 12), __BITS(26, 20), __BITS(30, 28), __BITS(31, 30)), 249 TEGRA_PINGROUP("sdmmc2",0xa9c, __BITS(7, 2), __BITS(13, 8), __BITS(30, 28), __BITS(31, 30)), 250 TEGRA_PINGROUP("sdmmc3",0xab0, __BITS(18, 12), __BITS(26, 20), __BITS(30, 28), __BITS(31, 30)), 251 TEGRA_PINGROUP("sdmmc4",0xab4, __BITS(7, 2), __BITS(13, 8), __BITS(30, 28), __BITS(31, 30)), 252 }; 253 254 255 const struct tegra_pinmux_conf tegra210_pinmux_conf = { 256 .npins = __arraycount(tegra210_pins), 257 .pins = tegra210_pins, 258 }; 259
Indexes created Tue Sep 30 11:09:46 GMT 2025