1 /* $NetBSD: tegra_gpio.c,v 1.14 2021/08/07 16:18:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_gpio.c,v 1.14 2021/08/07 16:18:44 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <dev/gpio/gpiovar.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_gpioreg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 const struct tegra_gpio_pinbank { 50 const char *name; 51 bus_size_t base; 52 } tegra_gpio_pinbanks [] = { 53 { "A", 0x000 }, 54 { "B", 0x004 }, 55 { "C", 0x008 }, 56 { "D", 0x00c }, 57 { "E", 0x100 }, 58 { "F", 0x104 }, 59 { "G", 0x108 }, 60 { "H", 0x10c }, 61 { "I", 0x200 }, 62 { "J", 0x204 }, 63 { "K", 0x208 }, 64 { "L", 0x20c }, 65 { "M", 0x300 }, 66 { "N", 0x304 }, 67 { "O", 0x308 }, 68 { "P", 0x30c }, 69 { "Q", 0x400 }, 70 { "R", 0x404 }, 71 { "S", 0x408 }, 72 { "T", 0x40c }, 73 { "U", 0x500 }, 74 { "V", 0x504 }, 75 { "W", 0x508 }, 76 { "X", 0x50c }, 77 { "Y", 0x600 }, 78 { "Z", 0x604 }, 79 { "AA", 0x608 }, 80 { "BB", 0x60c }, 81 { "CC", 0x700 }, 82 { "DD", 0x704 }, 83 { "EE", 0x708 } 84 }; 85 86 static int tegra_gpio_match(device_t, cfdata_t, void *); 87 static void tegra_gpio_attach(device_t, device_t, void *); 88 89 static void * tegra_gpio_fdt_acquire(device_t, const void *, 90 size_t, int); 91 static void tegra_gpio_fdt_release(device_t, void *); 92 static int tegra_gpio_fdt_read(device_t, void *, bool); 93 static void tegra_gpio_fdt_write(device_t, void *, int, bool); 94 95 struct fdtbus_gpio_controller_func tegra_gpio_funcs = { 96 .acquire = tegra_gpio_fdt_acquire, 97 .release = tegra_gpio_fdt_release, 98 .read = tegra_gpio_fdt_read, 99 .write = tegra_gpio_fdt_write 100 }; 101 102 struct tegra_gpio_softc; 103 104 struct tegra_gpio_bank { 105 struct tegra_gpio_softc *bank_sc; 106 const struct tegra_gpio_pinbank *bank_pb; 107 device_t bank_dev; 108 struct gpio_chipset_tag bank_gc; 109 gpio_pin_t bank_pins[8]; 110 }; 111 112 struct tegra_gpio_softc { 113 device_t sc_dev; 114 bus_space_tag_t sc_bst; 115 bus_space_handle_t sc_bsh; 116 117 struct tegra_gpio_bank *sc_banks; 118 }; 119 120 struct tegra_gpio_pin { 121 struct tegra_gpio_softc *pin_sc; 122 struct tegra_gpio_bank pin_bank; 123 int pin_no; 124 u_int pin_flags; 125 bool pin_actlo; 126 }; 127 128 static void tegra_gpio_attach_bank(struct tegra_gpio_softc *, u_int); 129 130 static int tegra_gpio_pin_read(void *, int); 131 static void tegra_gpio_pin_write(void *, int, int); 132 static void tegra_gpio_pin_ctl(void *, int, int); 133 134 static int tegra_gpio_cfprint(void *, const char *); 135 136 CFATTACH_DECL_NEW(tegra_gpio, sizeof(struct tegra_gpio_softc), 137 tegra_gpio_match, tegra_gpio_attach, NULL, NULL); 138 139 #define GPIO_WRITE(bank, reg, val) \ 140 bus_space_write_4((bank)->bank_sc->sc_bst, \ 141 (bank)->bank_sc->sc_bsh, \ 142 (bank)->bank_pb->base + (reg), (val)) 143 #define GPIO_READ(bank, reg) \ 144 bus_space_read_4((bank)->bank_sc->sc_bst, \ 145 (bank)->bank_sc->sc_bsh, \ 146 (bank)->bank_pb->base + (reg)) 147 148 static const struct device_compatible_entry compat_data[] = { 149 { .compat = "nvidia,tegra210-gpio" }, 150 { .compat = "nvidia,tegra124-gpio" }, 151 { .compat = "nvidia,tegra30-gpio" }, 152 DEVICE_COMPAT_EOL 153 }; 154 155 static int 156 tegra_gpio_match(device_t parent, cfdata_t cf, void *aux) 157 { 158 struct fdt_attach_args * const faa = aux; 159 160 return of_compatible_match(faa->faa_phandle, compat_data); 161 } 162 163 static void 164 tegra_gpio_attach(device_t parent, device_t self, void *aux) 165 { 166 struct tegra_gpio_softc * const sc = device_private(self); 167 struct fdt_attach_args * const faa = aux; 168 bus_addr_t addr; 169 bus_size_t size; 170 int error; 171 u_int n; 172 173 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 174 aprint_error(": couldn't get registers\n"); 175 return; 176 } 177 178 sc->sc_dev = self; 179 sc->sc_bst = faa->faa_bst; 180 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 181 if (error) { 182 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 183 return; 184 } 185 186 aprint_naive("\n"); 187 aprint_normal(": GPIO\n"); 188 189 const u_int nbank = __arraycount(tegra_gpio_pinbanks); 190 sc->sc_banks = kmem_zalloc(sizeof(*sc->sc_banks) * nbank, KM_SLEEP); 191 for (n = 0; n < nbank; n++) { 192 tegra_gpio_attach_bank(sc, n); 193 } 194 195 fdtbus_register_gpio_controller(self, faa->faa_phandle, 196 &tegra_gpio_funcs); 197 } 198 199 static void 200 tegra_gpio_attach_bank(struct tegra_gpio_softc *sc, u_int bankno) 201 { 202 struct tegra_gpio_bank *bank = &sc->sc_banks[bankno]; 203 struct gpiobus_attach_args gba; 204 u_int pin; 205 206 bank->bank_sc = sc; 207 bank->bank_pb = &tegra_gpio_pinbanks[bankno]; 208 bank->bank_gc.gp_cookie = bank; 209 bank->bank_gc.gp_pin_read = tegra_gpio_pin_read; 210 bank->bank_gc.gp_pin_write = tegra_gpio_pin_write; 211 bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl; 212 213 const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG); 214 215 for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) { 216 bank->bank_pins[pin].pin_num = pin; 217 /* skip pins in SFIO mode */ 218 if ((cnf & __BIT(pin)) == 0) 219 continue; 220 bank->bank_pins[pin].pin_caps = 221 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 222 GPIO_PIN_TRISTATE; 223 bank->bank_pins[pin].pin_state = 224 tegra_gpio_pin_read(bank, pin); 225 } 226 227 memset(&gba, 0, sizeof(gba)); 228 gba.gba_gc = &bank->bank_gc; 229 gba.gba_pins = bank->bank_pins; 230 gba.gba_npins = __arraycount(bank->bank_pins); 231 232 bank->bank_dev = 233 config_found(sc->sc_dev, &gba, tegra_gpio_cfprint, CFARGS_NONE); 234 } 235 236 static int 237 tegra_gpio_cfprint(void *priv, const char *pnp) 238 { 239 struct gpiobus_attach_args *gba = priv; 240 struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie; 241 const char *bankname = bank->bank_pb->name; 242 243 if (pnp) 244 aprint_normal("gpiobus at %s", pnp); 245 246 aprint_normal(" (%s)", bankname); 247 248 return UNCONF; 249 } 250 251 static int 252 tegra_gpio_pin_read(void *priv, int pin) 253 { 254 struct tegra_gpio_bank *bank = priv; 255 256 const uint32_t v = GPIO_READ(bank, GPIO_IN_REG); 257 258 return (v >> pin) & 1; 259 } 260 261 static void 262 tegra_gpio_pin_write(void *priv, int pin, int val) 263 { 264 struct tegra_gpio_bank *bank = priv; 265 uint32_t v; 266 267 v = (1 << (pin + 8)); 268 v |= (val << pin); 269 GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v); 270 } 271 272 static void 273 tegra_gpio_pin_ctl(void *priv, int pin, int flags) 274 { 275 struct tegra_gpio_bank *bank = priv; 276 uint32_t v; 277 278 if (flags & GPIO_PIN_INPUT) { 279 v = (1 << (pin + 8)); 280 GPIO_WRITE(bank, GPIO_MSK_OE_REG, v); 281 } else if (flags & GPIO_PIN_OUTPUT) { 282 v = (1 << (pin + 8)); 283 v |= (1 << pin); 284 GPIO_WRITE(bank, GPIO_MSK_OE_REG, v); 285 } 286 } 287 288 static void * 289 tegra_gpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 290 { 291 struct tegra_gpio_bank gbank; 292 struct tegra_gpio_pin *gpin; 293 const u_int *gpio = data; 294 295 if (len != 12) 296 return NULL; 297 298 const u_int bank = be32toh(gpio[1]) >> 3; 299 const u_int pin = be32toh(gpio[1]) & 7; 300 const bool actlo = be32toh(gpio[2]) & 1; 301 302 if (bank >= __arraycount(tegra_gpio_pinbanks) || pin > 8) 303 return NULL; 304 305 gbank.bank_sc = device_private(dev); 306 gbank.bank_pb = &tegra_gpio_pinbanks[bank]; 307 308 const uint32_t cnf = GPIO_READ(&gbank, GPIO_CNF_REG); 309 if ((cnf & __BIT(pin)) == 0) 310 GPIO_WRITE(&gbank, GPIO_CNF_REG, cnf | __BIT(pin)); 311 312 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 313 gpin->pin_bank = gbank; 314 gpin->pin_no = pin; 315 gpin->pin_flags = flags; 316 gpin->pin_actlo = actlo; 317 318 tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags); 319 320 return gpin; 321 } 322 323 static void 324 tegra_gpio_fdt_release(device_t dev, void *priv) 325 { 326 struct tegra_gpio_pin *gpin = priv; 327 328 tegra_gpio_release(gpin); 329 } 330 331 static int 332 tegra_gpio_fdt_read(device_t dev, void *priv, bool raw) 333 { 334 struct tegra_gpio_pin *gpin = priv; 335 int val; 336 337 val = tegra_gpio_read(gpin); 338 339 if (!raw && gpin->pin_actlo) 340 val = !val; 341 342 return val; 343 } 344 345 static void 346 tegra_gpio_fdt_write(device_t dev, void *priv, int val, bool raw) 347 { 348 struct tegra_gpio_pin *gpin = priv; 349 350 if (!raw && gpin->pin_actlo) 351 val = !val; 352 353 tegra_gpio_write(gpin, val); 354 } 355 356 static const struct tegra_gpio_pinbank * 357 tegra_gpio_pin_lookup(const char *pinname, int *ppin) 358 { 359 char bankname[3]; 360 u_int n; 361 int pin; 362 363 KASSERT(strlen(pinname) == 2 || strlen(pinname) == 3); 364 365 memset(bankname, 0, sizeof(bankname)); 366 bankname[0] = pinname[0]; 367 if (strlen(pinname) == 2) { 368 pin = pinname[1] - '0'; 369 } else { 370 bankname[1] = pinname[1]; 371 pin = pinname[2] - '0'; 372 } 373 374 for (n = 0; n < __arraycount(tegra_gpio_pinbanks); n++) { 375 const struct tegra_gpio_pinbank *pb = 376 &tegra_gpio_pinbanks[n]; 377 if (strcmp(pb->name, bankname) == 0) { 378 *ppin = pin; 379 return pb; 380 } 381 } 382 383 return NULL; 384 } 385 386 struct tegra_gpio_pin * 387 tegra_gpio_acquire(const char *pinname, u_int flags) 388 { 389 struct tegra_gpio_bank bank; 390 struct tegra_gpio_pin *gpin; 391 int pin; 392 device_t dev; 393 394 dev = device_find_by_driver_unit("tegragpio", 0); 395 if (dev == NULL) 396 return NULL; 397 398 bank.bank_sc = device_private(dev); 399 bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin); 400 if (bank.bank_pb == NULL) 401 return NULL; 402 403 const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG); 404 if ((cnf & __BIT(pin)) == 0) 405 GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin)); 406 407 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 408 gpin->pin_bank = bank; 409 gpin->pin_no = pin; 410 gpin->pin_flags = flags; 411 412 tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags); 413 414 return gpin; 415 } 416 417 void 418 tegra_gpio_release(struct tegra_gpio_pin *gpin) 419 { 420 tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, GPIO_PIN_INPUT); 421 kmem_free(gpin, sizeof(*gpin)); 422 } 423 424 int 425 tegra_gpio_read(struct tegra_gpio_pin *gpin) 426 { 427 int ret; 428 429 if (gpin->pin_flags & GPIO_PIN_INPUT) { 430 ret = tegra_gpio_pin_read(&gpin->pin_bank, gpin->pin_no); 431 } else { 432 const uint32_t v = GPIO_READ(&gpin->pin_bank, GPIO_OUT_REG); 433 ret = (v >> gpin->pin_no) & 1; 434 } 435 436 return ret; 437 } 438 439 void 440 tegra_gpio_write(struct tegra_gpio_pin *gpin, int val) 441 { 442 KASSERT((gpin->pin_flags & GPIO_PIN_OUTPUT) != 0); 443 444 tegra_gpio_pin_write(&gpin->pin_bank, gpin->pin_no, val); 445 } 446
Indexes created Sat Sep 20 22:09:52 GMT 2025