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      1 /*	$NetBSD: r100_track.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $	*/
      2 
      3 /* SPDX-License-Identifier: MIT */
      4 
      5 #include "radeon.h"
      6 
      7 #define R100_TRACK_MAX_TEXTURE 3
      8 #define R200_TRACK_MAX_TEXTURE 6
      9 #define R300_TRACK_MAX_TEXTURE 16
     10 
     11 #define R100_MAX_CB 1
     12 #define R300_MAX_CB 4
     13 
     14 /*
     15  * CS functions
     16  */
     17 struct r100_cs_track_cb {
     18 	struct radeon_bo	*robj;
     19 	unsigned		pitch;
     20 	unsigned		cpp;
     21 	unsigned		offset;
     22 };
     23 
     24 struct r100_cs_track_array {
     25 	struct radeon_bo	*robj;
     26 	unsigned		esize;
     27 };
     28 
     29 struct r100_cs_cube_info {
     30 	struct radeon_bo	*robj;
     31 	unsigned		offset;
     32 	unsigned		width;
     33 	unsigned		height;
     34 };
     35 
     36 #define R100_TRACK_COMP_NONE   0
     37 #define R100_TRACK_COMP_DXT1   1
     38 #define R100_TRACK_COMP_DXT35  2
     39 
     40 struct r100_cs_track_texture {
     41 	struct radeon_bo	*robj;
     42 	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
     43 	unsigned		pitch;
     44 	unsigned		width;
     45 	unsigned		height;
     46 	unsigned		num_levels;
     47 	unsigned		cpp;
     48 	unsigned		tex_coord_type;
     49 	unsigned		txdepth;
     50 	unsigned		width_11;
     51 	unsigned		height_11;
     52 	bool			use_pitch;
     53 	bool			enabled;
     54 	bool                    lookup_disable;
     55 	bool			roundup_w;
     56 	bool			roundup_h;
     57 	unsigned                compress_format;
     58 };
     59 
     60 struct r100_cs_track {
     61 	unsigned			num_cb;
     62 	unsigned                        num_texture;
     63 	unsigned			maxy;
     64 	unsigned			vtx_size;
     65 	unsigned			vap_vf_cntl;
     66 	unsigned			vap_alt_nverts;
     67 	unsigned			immd_dwords;
     68 	unsigned			num_arrays;
     69 	unsigned			max_indx;
     70 	unsigned			color_channel_mask;
     71 	struct r100_cs_track_array	arrays[16];
     72 	struct r100_cs_track_cb 	cb[R300_MAX_CB];
     73 	struct r100_cs_track_cb 	zb;
     74 	struct r100_cs_track_cb 	aa;
     75 	struct r100_cs_track_texture	textures[R300_TRACK_MAX_TEXTURE];
     76 	bool				z_enabled;
     77 	bool                            separate_cube;
     78 	bool				zb_cb_clear;
     79 	bool				blend_read_enable;
     80 	bool				cb_dirty;
     81 	bool				zb_dirty;
     82 	bool				tex_dirty;
     83 	bool				aa_dirty;
     84 	bool				aaresolve;
     85 };
     86 
     87 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
     88 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
     89 
     90 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
     91 
     92 int r200_packet0_check(struct radeon_cs_parser *p,
     93 		       struct radeon_cs_packet *pkt,
     94 		       unsigned idx, unsigned reg);
     95 
     96 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
     97 			    struct radeon_cs_packet *pkt,
     98 			    unsigned idx,
     99 			    unsigned reg);
    100 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
    101 			     struct radeon_cs_packet *pkt,
    102 			     int idx);
    103