| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 219 struct timing_generator *tg = local in function:dce110_vblank_set
220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
223 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
|
| /src/sbin/routed/ |
| input.c | 155 struct tgate *tg = 0; local in function:input
582 tg = tgates;
583 while (tg->tgate_addr != FROM_NADDR) {
584 tg = tg->tgate_next;
585 if (tg == 0) {
685 if (tg && (tn = tg->tgate_nets)->mask != 0) {
|
| parms.c | 592 struct tgate *tg; local in function:parse_parms
822 tg = (struct tgate *)rtmalloc(sizeof(*tg),
825 memset(tg, 0, sizeof(*tg));
826 tg->tgate_addr = addr;
834 || !getnet(buf2, &tg->tgate_nets[i].net,
835 &tg->tgate_nets[i].mask)
836 || tg->tgate_nets[i].net == RIP_DEFAULT
837 || tg->tgate_nets[i].mask == 0)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 432 struct timing_generator *tg = pool->timing_generators[i]; local in function:dcn10_get_otg_states
436 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
444 tg->inst,
499 struct timing_generator *tg = pool->timing_generators[i]; local in function:dcn10_clear_otpc_underflow
502 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
505 tg->funcs->clear_optc_underflow(tg);
|
| amdgpu_dcn10_hw_sequencer.c | 95 struct timing_generator *tg; local in function:dcn10_lock_all_pipes
100 tg = pipe_ctx->stream_res.tg;
102 * Only lock the top pipe's tg to prevent redundant
107 !tg->funcs->is_tg_enabled(tg))
111 tg->funcs->lock(tg);
113 tg->funcs->unlock(tg);
346 struct timing_generator *tg = pool->timing_generators[i]; local in function:dcn10_log_hw_state
469 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_did_underflow_occur
1146 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn10_init_pipes
1184 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn10_init_pipes
2518 struct timing_generator *tg; local in function:dcn10_apply_ctx_for_surface
2890 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_update_pending_status
3201 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_setup_periodic_interrupt
3220 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn10_setup_vupdate_interrupt
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_stream.c | 516 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; local in function:dc_stream_get_vblank_counter
521 return tg->funcs->get_frame_count(tg);
575 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; local in function:dc_stream_get_scanoutpos
580 tg->funcs->get_scanoutpos(tg,
|
| amdgpu_dc.c | 294 if (pipe->stream == stream && pipe->stream_res.tg) {
350 struct timing_generator *tg; local in function:dc_stream_configure_crc
376 tg = pipe->stream_res.tg;
379 if (tg->funcs->configure_crc)
380 return tg->funcs->configure_crc(tg, ¶m);
399 struct timing_generator *tg; local in function:dc_stream_get_crc
410 tg = pipe->stream_res.tg;
1049 struct timing_generator *tg; local in function:dc_validate_seamless_boot_timing
[all...] |
| amdgpu_dc_resource.c | 1244 split_pipe->stream_res.tg = pool->timing_generators[i];
1319 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1646 pipe_ctx->stream_res.tg = pool->timing_generators[i];
1917 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2001 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2041 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2804 struct timing_generator *tg = dc->res_pool->timing_generators[0]; local in function:dc_validate_stream
2809 if (!tg->funcs->validate_timing(tg, &stream->timing)
[all...] |
| /src/sys/dev/scsipi/ |
| ch.c | 1166 struct page_transport_geometry_parameters tg; member in union:ch_get_params::scsi_mode_sense_data::__anonb83edb5f010a
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
167 pipe_ctx->stream_res.tg->funcs->set_gsl(
168 pipe_ctx->stream_res.tg,
171 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
172 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
278 struct timing_generator *tg)
293 tg->funcs->get_otg_active_size(tg,
298 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1)
2000 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn20_setup_vupdate_interrupt
2225 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dcn20_enable_stream
2320 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2327 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2351 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2382 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
2398 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:dcn20_fpga_init_hw
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_connector.c | 2321 struct drm_tile_group *tg = container_of(kref, struct drm_tile_group, refcount); local in function:drm_tile_group_free
2322 struct drm_device *dev = tg->dev;
2324 idr_remove(&dev->mode_config.tile_idr, tg->id);
2326 kfree(tg);
2332 * @tg: tile group to drop reference to.
2337 struct drm_tile_group *tg)
2339 kref_put(&tg->refcount, drm_tile_group_free);
2356 struct drm_tile_group *tg; local in function:drm_mode_get_tile_group
2359 idr_for_each_entry(&dev->mode_config.tile_idr, tg, id) {
2360 if (!memcmp(tg->group_data, topology, 8))
2386 struct drm_tile_group *tg; local in function:drm_mode_create_tile_group
[all...] |
| drm_edid.c | 5709 struct drm_tile_group *tg; local in function:drm_parse_tiled_block
5736 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5737 if (!tg) {
5738 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5740 if (!tg)
5743 if (connector->tile_group != tg) {
5749 connector->tile_group = tg;
5752 drm_mode_put_tile_group(connector->dev, tg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 667 struct timing_generator *tg = pipe_ctx->stream_res.tg; local in function:dce110_enable_stream
690 tg->funcs->set_early_control(tg, early_control);
1185 pipe_ctx->stream_res.tg->inst + 1);
1197 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1252 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1261 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1262 pipe_ctx->stream_res.tg,
1285 pipe_ctx->stream_res.tg->funcs->set_blank_color
1499 struct timing_generator *tg; local in function:disable_vga_and_power_gate_all_controllers
2398 struct timing_generator *tg = dc->res_pool->timing_generators[i]; local in function:init_hw
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 233 struct timing_generator *tg; member in struct:stream_resource
|
